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23#include "pp_debug.h"
24#include "smumgr.h"
25#include "smu_ucode_xfer_vi.h"
26#include "vegam_smumgr.h"
27#include "smu/smu_7_1_3_d.h"
28#include "smu/smu_7_1_3_sh_mask.h"
29#include "gmc/gmc_8_1_d.h"
30#include "gmc/gmc_8_1_sh_mask.h"
31#include "oss/oss_3_0_d.h"
32#include "gca/gfx_8_0_d.h"
33#include "bif/bif_5_0_d.h"
34#include "bif/bif_5_0_sh_mask.h"
35#include "ppatomctrl.h"
36#include "cgs_common.h"
37#include "smu7_ppsmc.h"
38
39#include "smu7_dyn_defaults.h"
40
41#include "smu7_hwmgr.h"
42#include "hardwaremanager.h"
43#include "ppatomctrl.h"
44#include "atombios.h"
45#include "pppcielanes.h"
46
47#include "dce/dce_11_2_d.h"
48#include "dce/dce_11_2_sh_mask.h"
49
50#define PPVEGAM_TARGETACTIVITY_DFLT 50
51
52#define VOLTAGE_VID_OFFSET_SCALE1 625
53#define VOLTAGE_VID_OFFSET_SCALE2 100
54#define POWERTUNE_DEFAULT_SET_MAX 1
55#define VDDC_VDDCI_DELTA 200
56#define MC_CG_ARB_FREQ_F1 0x0b
57
58#define STRAP_ASIC_RO_LSB 2168
59#define STRAP_ASIC_RO_MSB 2175
60
61#define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
62#define PPSMC_MSG_EnableModeSwitchRLCNotification ((uint16_t) 0x305)
63
64static const struct vegam_pt_defaults
65vegam_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
66
67
68 { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
69 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
70 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
71};
72
73static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
74 {VCO_2_4, POSTDIV_DIV_BY_16, 75, 160, 112},
75 {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
76 {VCO_2_4, POSTDIV_DIV_BY_8, 75, 160, 112},
77 {VCO_3_6, POSTDIV_DIV_BY_8, 112, 224, 160},
78 {VCO_2_4, POSTDIV_DIV_BY_4, 75, 160, 112},
79 {VCO_3_6, POSTDIV_DIV_BY_4, 112, 216, 160},
80 {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108},
81 {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} };
82
83static int vegam_smu_init(struct pp_hwmgr *hwmgr)
84{
85 struct vegam_smumgr *smu_data;
86
87 smu_data = kzalloc(sizeof(struct vegam_smumgr), GFP_KERNEL);
88 if (smu_data == NULL)
89 return -ENOMEM;
90
91 hwmgr->smu_backend = smu_data;
92
93 if (smu7_init(hwmgr)) {
94 kfree(smu_data);
95 return -EINVAL;
96 }
97
98 return 0;
99}
100
101static int vegam_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
102{
103 int result = 0;
104
105
106
107
108
109 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
110 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
111
112 result = smu7_upload_smu_firmware_image(hwmgr);
113 if (result != 0)
114 return result;
115
116
117 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
118
119 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
120 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
121
122
123 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
124 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
125
126
127 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
128
129
130
131 smu7_send_msg_to_smc_offset(hwmgr);
132
133
134
135
136 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
137
138 if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
139 SMU_STATUS, SMU_PASS))
140 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
141
142 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
143
144 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
145 SMC_SYSCON_RESET_CNTL, rst_reg, 1);
146
147 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
148 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
149
150
151 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
152
153 return result;
154}
155
156static int vegam_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
157{
158 int result = 0;
159
160
161 PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
162
163
164
165 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
166 ixFIRMWARE_FLAGS, 0);
167
168 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
169 SMC_SYSCON_RESET_CNTL,
170 rst_reg, 1);
171
172 result = smu7_upload_smu_firmware_image(hwmgr);
173 if (result != 0)
174 return result;
175
176
177 smu7_program_jump_on_start(hwmgr);
178
179 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
180 SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
181
182 PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
183 SMC_SYSCON_RESET_CNTL, rst_reg, 0);
184
185
186
187 PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
188 FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
189
190 return result;
191}
192
193static int vegam_start_smu(struct pp_hwmgr *hwmgr)
194{
195 int result = 0;
196 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
197
198
199 if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
200 smu_data->protected_mode = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
201 CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
202 smu_data->smu7_data.security_hard_key = (uint8_t)(PHM_READ_VFPF_INDIRECT_FIELD(
203 hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
204
205
206 if (smu_data->protected_mode == 0)
207 result = vegam_start_smu_in_non_protection_mode(hwmgr);
208 else
209 result = vegam_start_smu_in_protection_mode(hwmgr);
210
211 if (result != 0)
212 PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
213 }
214
215
216 smu7_read_smc_sram_dword(hwmgr,
217 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU75_Firmware_Header, SoftRegisters),
218 &(smu_data->smu7_data.soft_regs_start),
219 0x40000);
220
221 result = smu7_request_smu_load_fw(hwmgr);
222
223 return result;
224}
225
226static int vegam_process_firmware_header(struct pp_hwmgr *hwmgr)
227{
228 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
229 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
230 uint32_t tmp;
231 int result;
232 bool error = false;
233
234 result = smu7_read_smc_sram_dword(hwmgr,
235 SMU7_FIRMWARE_HEADER_LOCATION +
236 offsetof(SMU75_Firmware_Header, DpmTable),
237 &tmp, SMC_RAM_END);
238
239 if (0 == result)
240 smu_data->smu7_data.dpm_table_start = tmp;
241
242 error |= (0 != result);
243
244 result = smu7_read_smc_sram_dword(hwmgr,
245 SMU7_FIRMWARE_HEADER_LOCATION +
246 offsetof(SMU75_Firmware_Header, SoftRegisters),
247 &tmp, SMC_RAM_END);
248
249 if (!result) {
250 data->soft_regs_start = tmp;
251 smu_data->smu7_data.soft_regs_start = tmp;
252 }
253
254 error |= (0 != result);
255
256 result = smu7_read_smc_sram_dword(hwmgr,
257 SMU7_FIRMWARE_HEADER_LOCATION +
258 offsetof(SMU75_Firmware_Header, mcRegisterTable),
259 &tmp, SMC_RAM_END);
260
261 if (!result)
262 smu_data->smu7_data.mc_reg_table_start = tmp;
263
264 result = smu7_read_smc_sram_dword(hwmgr,
265 SMU7_FIRMWARE_HEADER_LOCATION +
266 offsetof(SMU75_Firmware_Header, FanTable),
267 &tmp, SMC_RAM_END);
268
269 if (!result)
270 smu_data->smu7_data.fan_table_start = tmp;
271
272 error |= (0 != result);
273
274 result = smu7_read_smc_sram_dword(hwmgr,
275 SMU7_FIRMWARE_HEADER_LOCATION +
276 offsetof(SMU75_Firmware_Header, mcArbDramTimingTable),
277 &tmp, SMC_RAM_END);
278
279 if (!result)
280 smu_data->smu7_data.arb_table_start = tmp;
281
282 error |= (0 != result);
283
284 result = smu7_read_smc_sram_dword(hwmgr,
285 SMU7_FIRMWARE_HEADER_LOCATION +
286 offsetof(SMU75_Firmware_Header, Version),
287 &tmp, SMC_RAM_END);
288
289 if (!result)
290 hwmgr->microcode_version_info.SMC = tmp;
291
292 error |= (0 != result);
293
294 return error ? -1 : 0;
295}
296
297static bool vegam_is_dpm_running(struct pp_hwmgr *hwmgr)
298{
299 return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
300 CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
301 ? true : false;
302}
303
304static uint32_t vegam_get_mac_definition(uint32_t value)
305{
306 switch (value) {
307 case SMU_MAX_LEVELS_GRAPHICS:
308 return SMU75_MAX_LEVELS_GRAPHICS;
309 case SMU_MAX_LEVELS_MEMORY:
310 return SMU75_MAX_LEVELS_MEMORY;
311 case SMU_MAX_LEVELS_LINK:
312 return SMU75_MAX_LEVELS_LINK;
313 case SMU_MAX_ENTRIES_SMIO:
314 return SMU75_MAX_ENTRIES_SMIO;
315 case SMU_MAX_LEVELS_VDDC:
316 return SMU75_MAX_LEVELS_VDDC;
317 case SMU_MAX_LEVELS_VDDGFX:
318 return SMU75_MAX_LEVELS_VDDGFX;
319 case SMU_MAX_LEVELS_VDDCI:
320 return SMU75_MAX_LEVELS_VDDCI;
321 case SMU_MAX_LEVELS_MVDD:
322 return SMU75_MAX_LEVELS_MVDD;
323 case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
324 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE |
325 SMU7_VCE_MCLK_HANDSHAKE_DISABLE;
326 }
327
328 pr_warn("can't get the mac of %x\n", value);
329 return 0;
330}
331
332static int vegam_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
333{
334 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
335 uint32_t mm_boot_level_offset, mm_boot_level_value;
336 struct phm_ppt_v1_information *table_info =
337 (struct phm_ppt_v1_information *)(hwmgr->pptable);
338
339 smu_data->smc_state_table.UvdBootLevel = 0;
340 if (table_info->mm_dep_table->count > 0)
341 smu_data->smc_state_table.UvdBootLevel =
342 (uint8_t) (table_info->mm_dep_table->count - 1);
343 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU75_Discrete_DpmTable,
344 UvdBootLevel);
345 mm_boot_level_offset /= 4;
346 mm_boot_level_offset *= 4;
347 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
348 CGS_IND_REG__SMC, mm_boot_level_offset);
349 mm_boot_level_value &= 0x00FFFFFF;
350 mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
351 cgs_write_ind_register(hwmgr->device,
352 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
353
354 if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
355 PHM_PlatformCaps_UVDDPM) ||
356 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
357 PHM_PlatformCaps_StablePState))
358 smum_send_msg_to_smc_with_parameter(hwmgr,
359 PPSMC_MSG_UVDDPM_SetEnabledMask,
360 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel));
361 return 0;
362}
363
364static int vegam_update_vce_smc_table(struct pp_hwmgr *hwmgr)
365{
366 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
367 uint32_t mm_boot_level_offset, mm_boot_level_value;
368 struct phm_ppt_v1_information *table_info =
369 (struct phm_ppt_v1_information *)(hwmgr->pptable);
370
371 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
372 PHM_PlatformCaps_StablePState))
373 smu_data->smc_state_table.VceBootLevel =
374 (uint8_t) (table_info->mm_dep_table->count - 1);
375 else
376 smu_data->smc_state_table.VceBootLevel = 0;
377
378 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
379 offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
380 mm_boot_level_offset /= 4;
381 mm_boot_level_offset *= 4;
382 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
383 CGS_IND_REG__SMC, mm_boot_level_offset);
384 mm_boot_level_value &= 0xFF00FFFF;
385 mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
386 cgs_write_ind_register(hwmgr->device,
387 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
388
389 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
390 smum_send_msg_to_smc_with_parameter(hwmgr,
391 PPSMC_MSG_VCEDPM_SetEnabledMask,
392 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel);
393 return 0;
394}
395
396static int vegam_update_samu_smc_table(struct pp_hwmgr *hwmgr)
397{
398 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
399 uint32_t mm_boot_level_offset, mm_boot_level_value;
400
401
402 smu_data->smc_state_table.SamuBootLevel = 0;
403 mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
404 offsetof(SMU75_Discrete_DpmTable, SamuBootLevel);
405
406 mm_boot_level_offset /= 4;
407 mm_boot_level_offset *= 4;
408 mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
409 CGS_IND_REG__SMC, mm_boot_level_offset);
410 mm_boot_level_value &= 0xFFFFFF00;
411 mm_boot_level_value |= smu_data->smc_state_table.SamuBootLevel << 0;
412 cgs_write_ind_register(hwmgr->device,
413 CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
414
415 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
416 PHM_PlatformCaps_StablePState))
417 smum_send_msg_to_smc_with_parameter(hwmgr,
418 PPSMC_MSG_SAMUDPM_SetEnabledMask,
419 (uint32_t)(1 << smu_data->smc_state_table.SamuBootLevel));
420 return 0;
421}
422
423
424static int vegam_update_bif_smc_table(struct pp_hwmgr *hwmgr)
425{
426 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
427 struct phm_ppt_v1_information *table_info =
428 (struct phm_ppt_v1_information *)(hwmgr->pptable);
429 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
430 int max_entry, i;
431
432 max_entry = (SMU75_MAX_LEVELS_LINK < pcie_table->count) ?
433 SMU75_MAX_LEVELS_LINK :
434 pcie_table->count;
435
436 for (i = 0; i < max_entry; i++)
437 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
438 return 0;
439}
440
441static int vegam_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
442{
443 switch (type) {
444 case SMU_UVD_TABLE:
445 vegam_update_uvd_smc_table(hwmgr);
446 break;
447 case SMU_VCE_TABLE:
448 vegam_update_vce_smc_table(hwmgr);
449 break;
450 case SMU_SAMU_TABLE:
451 vegam_update_samu_smc_table(hwmgr);
452 break;
453 case SMU_BIF_TABLE:
454 vegam_update_bif_smc_table(hwmgr);
455 break;
456 default:
457 break;
458 }
459 return 0;
460}
461
462static void vegam_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
463{
464 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
465 struct phm_ppt_v1_information *table_info =
466 (struct phm_ppt_v1_information *)(hwmgr->pptable);
467
468 if (table_info &&
469 table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
470 table_info->cac_dtp_table->usPowerTuneDataSetID)
471 smu_data->power_tune_defaults =
472 &vegam_power_tune_data_set_array
473 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
474 else
475 smu_data->power_tune_defaults = &vegam_power_tune_data_set_array[0];
476
477}
478
479static int vegam_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
480 SMU75_Discrete_DpmTable *table)
481{
482 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
483 uint32_t count, level;
484
485 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
486 count = data->mvdd_voltage_table.count;
487 if (count > SMU_MAX_SMIO_LEVELS)
488 count = SMU_MAX_SMIO_LEVELS;
489 for (level = 0; level < count; level++) {
490 table->SmioTable2.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
491 data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
492
493 table->SmioTable2.Pattern[level].Smio =
494 (uint8_t) level;
495 table->Smio[level] |=
496 data->mvdd_voltage_table.entries[level].smio_low;
497 }
498 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
499
500 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
501 }
502
503 return 0;
504}
505
506static int vegam_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
507 struct SMU75_Discrete_DpmTable *table)
508{
509 uint32_t count, level;
510 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
511
512 count = data->vddci_voltage_table.count;
513
514 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
515 if (count > SMU_MAX_SMIO_LEVELS)
516 count = SMU_MAX_SMIO_LEVELS;
517 for (level = 0; level < count; ++level) {
518 table->SmioTable1.Pattern[level].Voltage = PP_HOST_TO_SMC_US(
519 data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
520 table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
521
522 table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
523 }
524 }
525
526 table->SmioMask1 = data->vddci_voltage_table.mask_low;
527
528 return 0;
529}
530
531static int vegam_populate_cac_table(struct pp_hwmgr *hwmgr,
532 struct SMU75_Discrete_DpmTable *table)
533{
534 uint32_t count;
535 uint8_t index;
536 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
537 struct phm_ppt_v1_information *table_info =
538 (struct phm_ppt_v1_information *)(hwmgr->pptable);
539 struct phm_ppt_v1_voltage_lookup_table *lookup_table =
540 table_info->vddc_lookup_table;
541
542
543
544
545
546 for (count = 0; count < lookup_table->count; count++) {
547 index = phm_get_voltage_index(lookup_table,
548 data->vddc_voltage_table.entries[count].value);
549 table->BapmVddcVidLoSidd[count] =
550 convert_to_vid(lookup_table->entries[index].us_cac_low);
551 table->BapmVddcVidHiSidd[count] =
552 convert_to_vid(lookup_table->entries[index].us_cac_mid);
553 table->BapmVddcVidHiSidd2[count] =
554 convert_to_vid(lookup_table->entries[index].us_cac_high);
555 }
556
557 return 0;
558}
559
560static int vegam_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
561 struct SMU75_Discrete_DpmTable *table)
562{
563 vegam_populate_smc_vddci_table(hwmgr, table);
564 vegam_populate_smc_mvdd_table(hwmgr, table);
565 vegam_populate_cac_table(hwmgr, table);
566
567 return 0;
568}
569
570static int vegam_populate_ulv_level(struct pp_hwmgr *hwmgr,
571 struct SMU75_Discrete_Ulv *state)
572{
573 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
574 struct phm_ppt_v1_information *table_info =
575 (struct phm_ppt_v1_information *)(hwmgr->pptable);
576
577 state->CcPwrDynRm = 0;
578 state->CcPwrDynRm1 = 0;
579
580 state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
581 state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
582 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
583
584 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
585
586 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
587 CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
588 CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
589
590 return 0;
591}
592
593static int vegam_populate_ulv_state(struct pp_hwmgr *hwmgr,
594 struct SMU75_Discrete_DpmTable *table)
595{
596 return vegam_populate_ulv_level(hwmgr, &table->Ulv);
597}
598
599static int vegam_populate_smc_link_level(struct pp_hwmgr *hwmgr,
600 struct SMU75_Discrete_DpmTable *table)
601{
602 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
603 struct vegam_smumgr *smu_data =
604 (struct vegam_smumgr *)(hwmgr->smu_backend);
605 struct smu7_dpm_table *dpm_table = &data->dpm_table;
606 int i;
607
608
609
610 for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
611 table->LinkLevel[i].PcieGenSpeed =
612 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
613 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
614 dpm_table->pcie_speed_table.dpm_levels[i].param1);
615 table->LinkLevel[i].EnabledForActivity = 1;
616 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
617 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
618 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
619 }
620
621 smu_data->smc_state_table.LinkLevelCount =
622 (uint8_t)dpm_table->pcie_speed_table.count;
623
624
625 data->dpm_level_enable_mask.pcie_dpm_enable_mask =
626 phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
627
628 return 0;
629}
630
631static int vegam_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
632 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
633 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
634{
635 uint32_t i;
636 uint16_t vddci;
637 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
638
639 *voltage = *mvdd = 0;
640
641
642 if (dep_table->count == 0)
643 return -EINVAL;
644
645 for (i = 0; i < dep_table->count; i++) {
646
647 if (dep_table->entries[i].clk >= clock) {
648 *voltage |= (dep_table->entries[i].vddc *
649 VOLTAGE_SCALE) << VDDC_SHIFT;
650 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
651 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
652 VOLTAGE_SCALE) << VDDCI_SHIFT;
653 else if (dep_table->entries[i].vddci)
654 *voltage |= (dep_table->entries[i].vddci *
655 VOLTAGE_SCALE) << VDDCI_SHIFT;
656 else {
657 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
658 (dep_table->entries[i].vddc -
659 (uint16_t)VDDC_VDDCI_DELTA));
660 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
661 }
662
663 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
664 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
665 VOLTAGE_SCALE;
666 else if (dep_table->entries[i].mvdd)
667 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
668 VOLTAGE_SCALE;
669
670 *voltage |= 1 << PHASES_SHIFT;
671 return 0;
672 }
673 }
674
675
676 *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
677 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
678 (dep_table->entries[i - 1].vddc -
679 (uint16_t)VDDC_VDDCI_DELTA));
680
681 if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
682 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
683 VOLTAGE_SCALE) << VDDCI_SHIFT;
684 else if (dep_table->entries[i - 1].vddci)
685 *voltage |= (dep_table->entries[i - 1].vddci *
686 VOLTAGE_SCALE) << VDDC_SHIFT;
687 else
688 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
689
690 if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
691 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
692 else if (dep_table->entries[i].mvdd)
693 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
694
695 return 0;
696}
697
698static void vegam_get_sclk_range_table(struct pp_hwmgr *hwmgr,
699 SMU75_Discrete_DpmTable *table)
700{
701 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
702 uint32_t i, ref_clk;
703
704 struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
705
706 ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
707
708 if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
709 for (i = 0; i < NUM_SCLK_RANGE; i++) {
710 table->SclkFcwRangeTable[i].vco_setting =
711 range_table_from_vbios.entry[i].ucVco_setting;
712 table->SclkFcwRangeTable[i].postdiv =
713 range_table_from_vbios.entry[i].ucPostdiv;
714 table->SclkFcwRangeTable[i].fcw_pcc =
715 range_table_from_vbios.entry[i].usFcw_pcc;
716
717 table->SclkFcwRangeTable[i].fcw_trans_upper =
718 range_table_from_vbios.entry[i].usFcw_trans_upper;
719 table->SclkFcwRangeTable[i].fcw_trans_lower =
720 range_table_from_vbios.entry[i].usRcw_trans_lower;
721
722 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
723 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
724 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
725 }
726 return;
727 }
728
729 for (i = 0; i < NUM_SCLK_RANGE; i++) {
730 smu_data->range_table[i].trans_lower_frequency =
731 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
732 smu_data->range_table[i].trans_upper_frequency =
733 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
734
735 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
736 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
737 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
738
739 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
740 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
741
742 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
743 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
744 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
745 }
746}
747
748static int vegam_calculate_sclk_params(struct pp_hwmgr *hwmgr,
749 uint32_t clock, SMU_SclkSetting *sclk_setting)
750{
751 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
752 const SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
753 struct pp_atomctrl_clock_dividers_ai dividers;
754 uint32_t ref_clock;
755 uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
756 uint8_t i;
757 int result;
758 uint64_t temp;
759
760 sclk_setting->SclkFrequency = clock;
761
762 result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock, ÷rs);
763 if (result == 0) {
764 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
765 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
766 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
767 sclk_setting->PllRange = dividers.ucSclkPllRange;
768 sclk_setting->Sclk_slew_rate = 0x400;
769 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
770 sclk_setting->Pcc_down_slew_rate = 0xffff;
771 sclk_setting->SSc_En = dividers.ucSscEnable;
772 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
773 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
774 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
775 return result;
776 }
777
778 ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
779
780 for (i = 0; i < NUM_SCLK_RANGE; i++) {
781 if (clock > smu_data->range_table[i].trans_lower_frequency
782 && clock <= smu_data->range_table[i].trans_upper_frequency) {
783 sclk_setting->PllRange = i;
784 break;
785 }
786 }
787
788 sclk_setting->Fcw_int = (uint16_t)
789 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
790 ref_clock);
791 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
792 temp <<= 0x10;
793 do_div(temp, ref_clock);
794 sclk_setting->Fcw_frac = temp & 0xffff;
795
796 pcc_target_percent = 10;
797 pcc_target_freq = clock - (clock * pcc_target_percent / 100);
798 sclk_setting->Pcc_fcw_int = (uint16_t)
799 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
800 ref_clock);
801
802 ss_target_percent = 2;
803 sclk_setting->SSc_En = 0;
804 if (ss_target_percent) {
805 sclk_setting->SSc_En = 1;
806 ss_target_freq = clock - (clock * ss_target_percent / 100);
807 sclk_setting->Fcw1_int = (uint16_t)
808 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) /
809 ref_clock);
810 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
811 temp <<= 0x10;
812 do_div(temp, ref_clock);
813 sclk_setting->Fcw1_frac = temp & 0xffff;
814 }
815
816 return 0;
817}
818
819static uint8_t vegam_get_sleep_divider_id_from_clock(uint32_t clock,
820 uint32_t clock_insr)
821{
822 uint8_t i;
823 uint32_t temp;
824 uint32_t min = max(clock_insr, (uint32_t)SMU7_MINIMUM_ENGINE_CLOCK);
825
826 PP_ASSERT_WITH_CODE((clock >= min),
827 "Engine clock can't satisfy stutter requirement!",
828 return 0);
829 for (i = 31; ; i--) {
830 temp = clock / (i + 1);
831
832 if (temp >= min || i == 0)
833 break;
834 }
835 return i;
836}
837
838static int vegam_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
839 uint32_t clock, struct SMU75_Discrete_GraphicsLevel *level)
840{
841 int result;
842
843 uint32_t mvdd;
844 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
845 struct phm_ppt_v1_information *table_info =
846 (struct phm_ppt_v1_information *)(hwmgr->pptable);
847 SMU_SclkSetting curr_sclk_setting = { 0 };
848
849 result = vegam_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
850
851
852 result = vegam_get_dependency_volt_by_clk(hwmgr,
853 table_info->vdd_dep_on_sclk, clock,
854 &level->MinVoltage, &mvdd);
855
856 PP_ASSERT_WITH_CODE((0 == result),
857 "can not find VDDC voltage value for "
858 "VDDC engine clock dependency table",
859 return result);
860 level->ActivityLevel = (uint16_t)(SclkDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
861
862 level->CcPwrDynRm = 0;
863 level->CcPwrDynRm1 = 0;
864 level->EnabledForActivity = 0;
865 level->EnabledForThrottle = 1;
866 level->VoltageDownHyst = 0;
867 level->PowerThrottle = 0;
868 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
869
870 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
871 level->DeepSleepDivId = vegam_get_sleep_divider_id_from_clock(clock,
872 hwmgr->display_config->min_core_set_clock_in_sr);
873
874 level->SclkSetting = curr_sclk_setting;
875
876 CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
877 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
878 CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
879 CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
880 CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
881 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
882 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
883 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
884 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
885 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
886 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
887 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
888 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
889 CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
890 return 0;
891}
892
893static int vegam_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
894{
895 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
896 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
897 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
898 struct phm_ppt_v1_information *table_info =
899 (struct phm_ppt_v1_information *)(hwmgr->pptable);
900 struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
901 uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
902 int result = 0;
903 uint32_t array = smu_data->smu7_data.dpm_table_start +
904 offsetof(SMU75_Discrete_DpmTable, GraphicsLevel);
905 uint32_t array_size = sizeof(struct SMU75_Discrete_GraphicsLevel) *
906 SMU75_MAX_LEVELS_GRAPHICS;
907 struct SMU75_Discrete_GraphicsLevel *levels =
908 smu_data->smc_state_table.GraphicsLevel;
909 uint32_t i, max_entry;
910 uint8_t hightest_pcie_level_enabled = 0,
911 lowest_pcie_level_enabled = 0,
912 mid_pcie_level_enabled = 0,
913 count = 0;
914
915 vegam_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
916
917 for (i = 0; i < dpm_table->sclk_table.count; i++) {
918
919 result = vegam_populate_single_graphic_level(hwmgr,
920 dpm_table->sclk_table.dpm_levels[i].value,
921 &(smu_data->smc_state_table.GraphicsLevel[i]));
922 if (result)
923 return result;
924
925 levels[i].UpHyst = (uint8_t)
926 (SclkDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
927 levels[i].DownHyst = (uint8_t)
928 (SclkDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
929
930 if (i > 1)
931 levels[i].DeepSleepDivId = 0;
932 }
933 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
934 PHM_PlatformCaps_SPLLShutdownSupport))
935 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
936
937 smu_data->smc_state_table.GraphicsDpmLevelCount =
938 (uint8_t)dpm_table->sclk_table.count;
939 hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
940 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
941
942 for (i = 0; i < dpm_table->sclk_table.count; i++)
943 levels[i].EnabledForActivity =
944 (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask >> i) & 0x1;
945
946 if (pcie_table != NULL) {
947 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
948 "There must be 1 or more PCIE levels defined in PPTable.",
949 return -EINVAL);
950 max_entry = pcie_entry_cnt - 1;
951 for (i = 0; i < dpm_table->sclk_table.count; i++)
952 levels[i].pcieDpmLevel =
953 (uint8_t) ((i < max_entry) ? i : max_entry);
954 } else {
955 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
956 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
957 (1 << (hightest_pcie_level_enabled + 1))) != 0))
958 hightest_pcie_level_enabled++;
959
960 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
961 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
962 (1 << lowest_pcie_level_enabled)) == 0))
963 lowest_pcie_level_enabled++;
964
965 while ((count < hightest_pcie_level_enabled) &&
966 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
967 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
968 count++;
969
970 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
971 hightest_pcie_level_enabled ?
972 (lowest_pcie_level_enabled + 1 + count) :
973 hightest_pcie_level_enabled;
974
975
976 for (i = 2; i < dpm_table->sclk_table.count; i++)
977 levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
978
979
980 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
981
982
983 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
984 }
985
986 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
987 (uint32_t)array_size, SMC_RAM_END);
988
989 return result;
990}
991
992static int vegam_calculate_mclk_params(struct pp_hwmgr *hwmgr,
993 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
994{
995 struct pp_atomctrl_memory_clock_param_ai mpll_param;
996
997 PP_ASSERT_WITH_CODE(!atomctrl_get_memory_pll_dividers_ai(hwmgr,
998 clock, &mpll_param),
999 "Failed to retrieve memory pll parameter.",
1000 return -EINVAL);
1001
1002 mem_level->MclkFrequency = (uint32_t)mpll_param.ulClock;
1003 mem_level->Fcw_int = (uint16_t)mpll_param.ulMclk_fcw_int;
1004 mem_level->Fcw_frac = (uint16_t)mpll_param.ulMclk_fcw_frac;
1005 mem_level->Postdiv = (uint8_t)mpll_param.ulPostDiv;
1006
1007 return 0;
1008}
1009
1010static int vegam_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1011 uint32_t clock, struct SMU75_Discrete_MemoryLevel *mem_level)
1012{
1013 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1014 struct phm_ppt_v1_information *table_info =
1015 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1016 int result = 0;
1017 uint32_t mclk_stutter_mode_threshold = 60000;
1018
1019
1020 if (table_info->vdd_dep_on_mclk) {
1021 result = vegam_get_dependency_volt_by_clk(hwmgr,
1022 table_info->vdd_dep_on_mclk, clock,
1023 &mem_level->MinVoltage, &mem_level->MinMvdd);
1024 PP_ASSERT_WITH_CODE(!result,
1025 "can not find MinVddc voltage value from memory "
1026 "VDDC voltage dependency table", return result);
1027 }
1028
1029 result = vegam_calculate_mclk_params(hwmgr, clock, mem_level);
1030 PP_ASSERT_WITH_CODE(!result,
1031 "Failed to calculate mclk params.",
1032 return -EINVAL);
1033
1034 mem_level->EnabledForThrottle = 1;
1035 mem_level->EnabledForActivity = 0;
1036 mem_level->VoltageDownHyst = 0;
1037 mem_level->ActivityLevel = (uint16_t)
1038 (MemoryDPMTuning_VEGAM >> DPMTuning_Activity_Shift);
1039 mem_level->StutterEnable = false;
1040 mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1041
1042 data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1043
1044 if (mclk_stutter_mode_threshold &&
1045 (clock <= mclk_stutter_mode_threshold) &&
1046 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1047 STUTTER_ENABLE) & 0x1))
1048 mem_level->StutterEnable = true;
1049
1050 if (!result) {
1051 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1052 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1053 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_int);
1054 CONVERT_FROM_HOST_TO_SMC_US(mem_level->Fcw_frac);
1055 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1056 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1057 }
1058
1059 return result;
1060}
1061
1062static int vegam_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1063{
1064 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1065 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1066 struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1067 int result;
1068
1069 uint32_t array = smu_data->smu7_data.dpm_table_start +
1070 offsetof(SMU75_Discrete_DpmTable, MemoryLevel);
1071 uint32_t array_size = sizeof(SMU75_Discrete_MemoryLevel) *
1072 SMU75_MAX_LEVELS_MEMORY;
1073 struct SMU75_Discrete_MemoryLevel *levels =
1074 smu_data->smc_state_table.MemoryLevel;
1075 uint32_t i;
1076
1077 for (i = 0; i < dpm_table->mclk_table.count; i++) {
1078 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1079 "can not populate memory level as memory clock is zero",
1080 return -EINVAL);
1081 result = vegam_populate_single_memory_level(hwmgr,
1082 dpm_table->mclk_table.dpm_levels[i].value,
1083 &levels[i]);
1084
1085 if (result)
1086 return result;
1087
1088 levels[i].UpHyst = (uint8_t)
1089 (MemoryDPMTuning_VEGAM >> DPMTuning_Uphyst_Shift);
1090 levels[i].DownHyst = (uint8_t)
1091 (MemoryDPMTuning_VEGAM >> DPMTuning_Downhyst_Shift);
1092 }
1093
1094 smu_data->smc_state_table.MemoryDpmLevelCount =
1095 (uint8_t)dpm_table->mclk_table.count;
1096 hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1097 phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1098
1099 for (i = 0; i < dpm_table->mclk_table.count; i++)
1100 levels[i].EnabledForActivity =
1101 (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask >> i) & 0x1;
1102
1103 levels[dpm_table->mclk_table.count - 1].DisplayWatermark =
1104 PPSMC_DISPLAY_WATERMARK_HIGH;
1105
1106
1107 result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1108 (uint32_t)array_size, SMC_RAM_END);
1109
1110 return result;
1111}
1112
1113static int vegam_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1114 uint32_t mclk, SMIO_Pattern *smio_pat)
1115{
1116 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1117 struct phm_ppt_v1_information *table_info =
1118 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1119 uint32_t i = 0;
1120
1121 if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1122
1123 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1124 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1125 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1126 break;
1127 }
1128 }
1129 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1130 "MVDD Voltage is outside the supported range.",
1131 return -EINVAL);
1132 } else
1133 return -EINVAL;
1134
1135 return 0;
1136}
1137
1138static int vegam_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1139 SMU75_Discrete_DpmTable *table)
1140{
1141 int result = 0;
1142 uint32_t sclk_frequency;
1143 const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1144 struct phm_ppt_v1_information *table_info =
1145 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1146 SMIO_Pattern vol_level;
1147 uint32_t mvdd;
1148 uint16_t us_mvdd;
1149
1150 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1151
1152
1153
1154 sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1155 result = vegam_get_dependency_volt_by_clk(hwmgr,
1156 table_info->vdd_dep_on_sclk,
1157 sclk_frequency,
1158 &table->ACPILevel.MinVoltage, &mvdd);
1159 PP_ASSERT_WITH_CODE(!result,
1160 "Cannot find ACPI VDDC voltage value "
1161 "in Clock Dependency Table",
1162 );
1163
1164 result = vegam_calculate_sclk_params(hwmgr, sclk_frequency,
1165 &(table->ACPILevel.SclkSetting));
1166 PP_ASSERT_WITH_CODE(!result,
1167 "Error retrieving Engine Clock dividers from VBIOS.",
1168 return result);
1169
1170 table->ACPILevel.DeepSleepDivId = 0;
1171 table->ACPILevel.CcPwrDynRm = 0;
1172 table->ACPILevel.CcPwrDynRm1 = 0;
1173
1174 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1175 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1176 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1177 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1178
1179 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1180 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1181 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1182 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1183 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1184 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1185 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1186 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1187 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1188 CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1189
1190
1191
1192 table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1193 result = vegam_get_dependency_volt_by_clk(hwmgr,
1194 table_info->vdd_dep_on_mclk,
1195 table->MemoryACPILevel.MclkFrequency,
1196 &table->MemoryACPILevel.MinVoltage, &mvdd);
1197 PP_ASSERT_WITH_CODE((0 == result),
1198 "Cannot find ACPI VDDCI voltage value "
1199 "in Clock Dependency Table",
1200 );
1201
1202 us_mvdd = 0;
1203 if ((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1204 (data->mclk_dpm_key_disabled))
1205 us_mvdd = data->vbios_boot_state.mvdd_bootup_value;
1206 else {
1207 if (!vegam_populate_mvdd_value(hwmgr,
1208 data->dpm_table.mclk_table.dpm_levels[0].value,
1209 &vol_level))
1210 us_mvdd = vol_level.Voltage;
1211 }
1212
1213 if (!vegam_populate_mvdd_value(hwmgr, 0, &vol_level))
1214 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1215 else
1216 table->MemoryACPILevel.MinMvdd = 0;
1217
1218 table->MemoryACPILevel.StutterEnable = false;
1219
1220 table->MemoryACPILevel.EnabledForThrottle = 0;
1221 table->MemoryACPILevel.EnabledForActivity = 0;
1222 table->MemoryACPILevel.UpHyst = 0;
1223 table->MemoryACPILevel.DownHyst = 100;
1224 table->MemoryACPILevel.VoltageDownHyst = 0;
1225 table->MemoryACPILevel.ActivityLevel =
1226 PP_HOST_TO_SMC_US(data->current_profile_setting.mclk_activity);
1227
1228 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1229 CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1230
1231 return result;
1232}
1233
1234static int vegam_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1235 SMU75_Discrete_DpmTable *table)
1236{
1237 int result = -EINVAL;
1238 uint8_t count;
1239 struct pp_atomctrl_clock_dividers_vi dividers;
1240 struct phm_ppt_v1_information *table_info =
1241 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1242 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1243 table_info->mm_dep_table;
1244 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1245 uint32_t vddci;
1246
1247 table->VceLevelCount = (uint8_t)(mm_table->count);
1248 table->VceBootLevel = 0;
1249
1250 for (count = 0; count < table->VceLevelCount; count++) {
1251 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1252 table->VceLevel[count].MinVoltage = 0;
1253 table->VceLevel[count].MinVoltage |=
1254 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1255
1256 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1257 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1258 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1259 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1260 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1261 else
1262 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1263
1264
1265 table->VceLevel[count].MinVoltage |=
1266 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1267 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1268
1269
1270 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1271 table->VceLevel[count].Frequency, ÷rs);
1272 PP_ASSERT_WITH_CODE((0 == result),
1273 "can not find divide id for VCE engine clock",
1274 return result);
1275
1276 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1277
1278 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1279 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1280 }
1281 return result;
1282}
1283
1284static int vegam_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1285 SMU75_Discrete_DpmTable *table)
1286{
1287 int result = -EINVAL;
1288 uint8_t count;
1289 struct pp_atomctrl_clock_dividers_vi dividers;
1290 struct phm_ppt_v1_information *table_info =
1291 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1292 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1293 table_info->mm_dep_table;
1294 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1295 uint32_t vddci;
1296
1297 table->SamuBootLevel = 0;
1298 table->SamuLevelCount = (uint8_t)(mm_table->count);
1299
1300 for (count = 0; count < table->SamuLevelCount; count++) {
1301
1302 table->SamuLevel[count].MinVoltage = 0;
1303 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1304 table->SamuLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1305 VOLTAGE_SCALE) << VDDC_SHIFT;
1306
1307 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1308 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1309 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1310 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1311 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1312 else
1313 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1314
1315 table->SamuLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1316 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1317
1318
1319 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1320 table->SamuLevel[count].Frequency, ÷rs);
1321 PP_ASSERT_WITH_CODE((0 == result),
1322 "can not find divide id for samu clock", return result);
1323
1324 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1325
1326 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1327 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1328 }
1329 return result;
1330}
1331
1332static int vegam_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1333 int32_t eng_clock, int32_t mem_clock,
1334 SMU75_Discrete_MCArbDramTimingTableEntry *arb_regs)
1335{
1336 uint32_t dram_timing;
1337 uint32_t dram_timing2;
1338 uint32_t burst_time;
1339 uint32_t rfsh_rate;
1340 uint32_t misc3;
1341
1342 int result;
1343
1344 result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1345 eng_clock, mem_clock);
1346 PP_ASSERT_WITH_CODE(result == 0,
1347 "Error calling VBIOS to set DRAM_TIMING.",
1348 return result);
1349
1350 dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1351 dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1352 burst_time = cgs_read_register(hwmgr->device, mmMC_ARB_BURST_TIME);
1353 rfsh_rate = cgs_read_register(hwmgr->device, mmMC_ARB_RFSH_RATE);
1354 misc3 = cgs_read_register(hwmgr->device, mmMC_ARB_MISC3);
1355
1356 arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dram_timing);
1357 arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1358 arb_regs->McArbBurstTime = PP_HOST_TO_SMC_UL(burst_time);
1359 arb_regs->McArbRfshRate = PP_HOST_TO_SMC_UL(rfsh_rate);
1360 arb_regs->McArbMisc3 = PP_HOST_TO_SMC_UL(misc3);
1361
1362 return 0;
1363}
1364
1365static int vegam_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1366{
1367 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1368 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1369 struct SMU75_Discrete_MCArbDramTimingTable arb_regs;
1370 uint32_t i, j;
1371 int result = 0;
1372
1373 memset(&arb_regs, 0, sizeof(SMU75_Discrete_MCArbDramTimingTable));
1374
1375 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1376 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1377 result = vegam_populate_memory_timing_parameters(hwmgr,
1378 hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1379 hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1380 &arb_regs.entries[i][j]);
1381 if (result)
1382 return result;
1383 }
1384 }
1385
1386 result = smu7_copy_bytes_to_smc(
1387 hwmgr,
1388 smu_data->smu7_data.arb_table_start,
1389 (uint8_t *)&arb_regs,
1390 sizeof(SMU75_Discrete_MCArbDramTimingTable),
1391 SMC_RAM_END);
1392 return result;
1393}
1394
1395static int vegam_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1396 struct SMU75_Discrete_DpmTable *table)
1397{
1398 int result = -EINVAL;
1399 uint8_t count;
1400 struct pp_atomctrl_clock_dividers_vi dividers;
1401 struct phm_ppt_v1_information *table_info =
1402 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1403 struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1404 table_info->mm_dep_table;
1405 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1406 uint32_t vddci;
1407
1408 table->UvdLevelCount = (uint8_t)(mm_table->count);
1409 table->UvdBootLevel = 0;
1410
1411 for (count = 0; count < table->UvdLevelCount; count++) {
1412 table->UvdLevel[count].MinVoltage = 0;
1413 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1414 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1415 table->UvdLevel[count].MinVoltage |=
1416 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1417
1418 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1419 vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1420 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1421 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1422 vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1423 else
1424 vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1425
1426 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1427 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1428
1429
1430 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1431 table->UvdLevel[count].VclkFrequency, ÷rs);
1432 PP_ASSERT_WITH_CODE((0 == result),
1433 "can not find divide id for Vclk clock", return result);
1434
1435 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1436
1437 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1438 table->UvdLevel[count].DclkFrequency, ÷rs);
1439 PP_ASSERT_WITH_CODE((0 == result),
1440 "can not find divide id for Dclk clock", return result);
1441
1442 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1443
1444 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1445 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1446 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1447 }
1448
1449 return result;
1450}
1451
1452static int vegam_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1453 struct SMU75_Discrete_DpmTable *table)
1454{
1455 int result = 0;
1456 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1457
1458 table->GraphicsBootLevel = 0;
1459 table->MemoryBootLevel = 0;
1460
1461
1462 result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1463 data->vbios_boot_state.sclk_bootup_value,
1464 (uint32_t *)&(table->GraphicsBootLevel));
1465
1466 result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1467 data->vbios_boot_state.mclk_bootup_value,
1468 (uint32_t *)&(table->MemoryBootLevel));
1469
1470 table->BootVddc = data->vbios_boot_state.vddc_bootup_value *
1471 VOLTAGE_SCALE;
1472 table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1473 VOLTAGE_SCALE;
1474 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value *
1475 VOLTAGE_SCALE;
1476
1477 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1478 CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1479 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1480
1481 return 0;
1482}
1483
1484static int vegam_populate_smc_initial_state(struct pp_hwmgr *hwmgr)
1485{
1486 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1487 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1488 struct phm_ppt_v1_information *table_info =
1489 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1490 uint8_t count, level;
1491
1492 count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1493
1494 for (level = 0; level < count; level++) {
1495 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1496 hw_data->vbios_boot_state.sclk_bootup_value) {
1497 smu_data->smc_state_table.GraphicsBootLevel = level;
1498 break;
1499 }
1500 }
1501
1502 count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1503 for (level = 0; level < count; level++) {
1504 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1505 hw_data->vbios_boot_state.mclk_bootup_value) {
1506 smu_data->smc_state_table.MemoryBootLevel = level;
1507 break;
1508 }
1509 }
1510
1511 return 0;
1512}
1513
1514static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
1515{
1516 uint32_t tmp;
1517 tmp = raw_setting * 4096 / 100;
1518 return (uint16_t)tmp;
1519}
1520
1521static int vegam_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
1522{
1523 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1524
1525 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1526 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1527 struct phm_ppt_v1_information *table_info =
1528 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1529 struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
1530 struct pp_advance_fan_control_parameters *fan_table =
1531 &hwmgr->thermal_controller.advanceFanControlParameters;
1532 int i, j, k;
1533 const uint16_t *pdef1;
1534 const uint16_t *pdef2;
1535
1536 table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1537 table->TargetTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
1538
1539 PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
1540 "Target Operating Temp is out of Range!",
1541 );
1542
1543 table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
1544 cac_dtp_table->usTargetOperatingTemp * 256);
1545 table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
1546 cac_dtp_table->usTemperatureLimitHotspot * 256);
1547 table->FanGainEdge = PP_HOST_TO_SMC_US(
1548 scale_fan_gain_settings(fan_table->usFanGainEdge));
1549 table->FanGainHotspot = PP_HOST_TO_SMC_US(
1550 scale_fan_gain_settings(fan_table->usFanGainHotspot));
1551
1552 pdef1 = defaults->BAPMTI_R;
1553 pdef2 = defaults->BAPMTI_RC;
1554
1555 for (i = 0; i < SMU75_DTE_ITERATIONS; i++) {
1556 for (j = 0; j < SMU75_DTE_SOURCES; j++) {
1557 for (k = 0; k < SMU75_DTE_SINKS; k++) {
1558 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
1559 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
1560 pdef1++;
1561 pdef2++;
1562 }
1563 }
1564 }
1565
1566 return 0;
1567}
1568
1569static int vegam_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1570{
1571 uint32_t ro, efuse, volt_without_cks, volt_with_cks, value, max, min;
1572 struct vegam_smumgr *smu_data =
1573 (struct vegam_smumgr *)(hwmgr->smu_backend);
1574
1575 uint8_t i, stretch_amount, stretch_amount2, volt_offset = 0;
1576 struct phm_ppt_v1_information *table_info =
1577 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1578 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1579 table_info->vdd_dep_on_sclk;
1580 uint32_t mask = (1 << ((STRAP_ASIC_RO_MSB - STRAP_ASIC_RO_LSB) + 1)) - 1;
1581
1582 stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1583
1584 atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB,
1585 mask, &efuse);
1586
1587 min = 1200;
1588 max = 2500;
1589
1590 ro = efuse * (max - min) / 255 + min;
1591
1592
1593 for (i = 0; i < sclk_table->count; i++) {
1594 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1595 sclk_table->entries[i].cks_enable << i;
1596 volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) *
1597 136418 - (ro - 70) * 1000000) /
1598 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1599 volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 *
1600 3232 - (ro - 65) * 1000000) /
1601 (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1602
1603 if (volt_without_cks >= volt_with_cks)
1604 volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1605 sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1606
1607 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1608 }
1609
1610 smu_data->smc_state_table.LdoRefSel =
1611 (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ?
1612 table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1613
1614 if (stretch_amount == 1 || stretch_amount == 2 || stretch_amount == 5)
1615 stretch_amount2 = 0;
1616 else if (stretch_amount == 3 || stretch_amount == 4)
1617 stretch_amount2 = 1;
1618 else {
1619 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1620 PHM_PlatformCaps_ClockStretcher);
1621 PP_ASSERT_WITH_CODE(false,
1622 "Stretch Amount in PPTable not supported\n",
1623 return -EINVAL);
1624 }
1625
1626 value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1627 value &= 0xFFFFFFFE;
1628 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1629
1630 return 0;
1631}
1632
1633static bool vegam_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
1634{
1635 uint32_t efuse;
1636
1637 efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1638 ixSMU_EFUSE_0 + (49 * 4));
1639 efuse &= 0x00000001;
1640
1641 if (efuse)
1642 return true;
1643
1644 return false;
1645}
1646
1647static int vegam_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1648{
1649 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1650 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1651
1652 SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1653 int result = 0;
1654 struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1655 AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1656 AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1657 uint32_t tmp, i;
1658
1659 struct phm_ppt_v1_information *table_info =
1660 (struct phm_ppt_v1_information *)hwmgr->pptable;
1661 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1662 table_info->vdd_dep_on_sclk;
1663
1664 if (!hwmgr->avfs_supported)
1665 return 0;
1666
1667 result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1668
1669 if (0 == result) {
1670 table->BTCGB_VDROOP_TABLE[0].a0 =
1671 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1672 table->BTCGB_VDROOP_TABLE[0].a1 =
1673 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1674 table->BTCGB_VDROOP_TABLE[0].a2 =
1675 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1676 table->BTCGB_VDROOP_TABLE[1].a0 =
1677 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1678 table->BTCGB_VDROOP_TABLE[1].a1 =
1679 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1680 table->BTCGB_VDROOP_TABLE[1].a2 =
1681 PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1682 table->AVFSGB_FUSE_TABLE[0].m1 =
1683 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1684 table->AVFSGB_FUSE_TABLE[0].m2 =
1685 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1686 table->AVFSGB_FUSE_TABLE[0].b =
1687 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1688 table->AVFSGB_FUSE_TABLE[0].m1_shift = 24;
1689 table->AVFSGB_FUSE_TABLE[0].m2_shift = 12;
1690 table->AVFSGB_FUSE_TABLE[1].m1 =
1691 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1692 table->AVFSGB_FUSE_TABLE[1].m2 =
1693 PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1694 table->AVFSGB_FUSE_TABLE[1].b =
1695 PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1696 table->AVFSGB_FUSE_TABLE[1].m1_shift = 24;
1697 table->AVFSGB_FUSE_TABLE[1].m2_shift = 12;
1698 table->MaxVoltage = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1699 AVFS_meanNsigma.Aconstant[0] =
1700 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1701 AVFS_meanNsigma.Aconstant[1] =
1702 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1703 AVFS_meanNsigma.Aconstant[2] =
1704 PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1705 AVFS_meanNsigma.DC_tol_sigma =
1706 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1707 AVFS_meanNsigma.Platform_mean =
1708 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1709 AVFS_meanNsigma.PSM_Age_CompFactor =
1710 PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1711 AVFS_meanNsigma.Platform_sigma =
1712 PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1713
1714 for (i = 0; i < sclk_table->count; i++) {
1715 AVFS_meanNsigma.Static_Voltage_Offset[i] =
1716 (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1717 AVFS_SclkOffset.Sclk_Offset[i] =
1718 PP_HOST_TO_SMC_US((uint16_t)
1719 (sclk_table->entries[i].sclk_offset) / 100);
1720 }
1721
1722 result = smu7_read_smc_sram_dword(hwmgr,
1723 SMU7_FIRMWARE_HEADER_LOCATION +
1724 offsetof(SMU75_Firmware_Header, AvfsMeanNSigma),
1725 &tmp, SMC_RAM_END);
1726 smu7_copy_bytes_to_smc(hwmgr,
1727 tmp,
1728 (uint8_t *)&AVFS_meanNsigma,
1729 sizeof(AVFS_meanNsigma_t),
1730 SMC_RAM_END);
1731
1732 result = smu7_read_smc_sram_dword(hwmgr,
1733 SMU7_FIRMWARE_HEADER_LOCATION +
1734 offsetof(SMU75_Firmware_Header, AvfsSclkOffsetTable),
1735 &tmp, SMC_RAM_END);
1736 smu7_copy_bytes_to_smc(hwmgr,
1737 tmp,
1738 (uint8_t *)&AVFS_SclkOffset,
1739 sizeof(AVFS_Sclk_Offset_t),
1740 SMC_RAM_END);
1741
1742 data->avfs_vdroop_override_setting =
1743 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1744 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1745 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1746 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1747 data->apply_avfs_cks_off_voltage =
1748 (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1749 }
1750 return result;
1751}
1752
1753static int vegam_populate_vr_config(struct pp_hwmgr *hwmgr,
1754 struct SMU75_Discrete_DpmTable *table)
1755{
1756 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1757 struct vegam_smumgr *smu_data =
1758 (struct vegam_smumgr *)(hwmgr->smu_backend);
1759 uint16_t config;
1760
1761 config = VR_MERGED_WITH_VDDC;
1762 table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1763
1764
1765 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1766 config = VR_SVI2_PLANE_1;
1767 table->VRConfig |= config;
1768 } else {
1769 PP_ASSERT_WITH_CODE(false,
1770 "VDDC should be on SVI2 control in merged mode!",
1771 );
1772 }
1773
1774 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1775 config = VR_SVI2_PLANE_2;
1776 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1777 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1778 config = VR_SMIO_PATTERN_1;
1779 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1780 } else {
1781 config = VR_STATIC_VOLTAGE;
1782 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1783 }
1784
1785 if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1786 if (config != VR_SVI2_PLANE_2) {
1787 config = VR_SVI2_PLANE_2;
1788 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1789 cgs_write_ind_register(hwmgr->device,
1790 CGS_IND_REG__SMC,
1791 smu_data->smu7_data.soft_regs_start +
1792 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1793 0x1);
1794 } else {
1795 PP_ASSERT_WITH_CODE(false,
1796 "SVI2 Plane 2 is already taken, set MVDD as Static",);
1797 config = VR_STATIC_VOLTAGE;
1798 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1799 }
1800 } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
1801 config = VR_SMIO_PATTERN_2;
1802 table->VRConfig = (config << VRCONF_MVDD_SHIFT);
1803 cgs_write_ind_register(hwmgr->device,
1804 CGS_IND_REG__SMC,
1805 smu_data->smu7_data.soft_regs_start +
1806 offsetof(SMU75_SoftRegisters, AllowMvddSwitch),
1807 0x1);
1808 } else {
1809 config = VR_STATIC_VOLTAGE;
1810 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1811 }
1812
1813 return 0;
1814}
1815
1816static int vegam_populate_svi_load_line(struct pp_hwmgr *hwmgr)
1817{
1818 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1819 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1820
1821 smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
1822 smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
1823 smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
1824 smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
1825
1826 return 0;
1827}
1828
1829static int vegam_populate_tdc_limit(struct pp_hwmgr *hwmgr)
1830{
1831 uint16_t tdc_limit;
1832 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1833 struct phm_ppt_v1_information *table_info =
1834 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1835 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1836
1837 tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
1838 smu_data->power_tune_table.TDC_VDDC_PkgLimit =
1839 CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
1840 smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
1841 defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
1842 smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
1843
1844 return 0;
1845}
1846
1847static int vegam_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
1848{
1849 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1850 const struct vegam_pt_defaults *defaults = smu_data->power_tune_defaults;
1851 uint32_t temp;
1852
1853 if (smu7_read_smc_sram_dword(hwmgr,
1854 fuse_table_offset +
1855 offsetof(SMU75_Discrete_PmFuses, TdcWaterfallCtl),
1856 (uint32_t *)&temp, SMC_RAM_END))
1857 PP_ASSERT_WITH_CODE(false,
1858 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
1859 return -EINVAL);
1860 else {
1861 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
1862 smu_data->power_tune_table.LPMLTemperatureMin =
1863 (uint8_t)((temp >> 16) & 0xff);
1864 smu_data->power_tune_table.LPMLTemperatureMax =
1865 (uint8_t)((temp >> 8) & 0xff);
1866 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
1867 }
1868 return 0;
1869}
1870
1871static int vegam_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
1872{
1873 int i;
1874 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1875
1876
1877 for (i = 0; i < 16; i++)
1878 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
1879
1880 return 0;
1881}
1882
1883static int vegam_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
1884{
1885 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1886
1887
1888 if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
1889 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
1890 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
1891 hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
1892
1893 smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
1894 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
1895 return 0;
1896}
1897
1898static int vegam_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
1899{
1900 int i;
1901 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1902
1903
1904 for (i = 0; i < 16; i++)
1905 smu_data->power_tune_table.GnbLPML[i] = 0;
1906
1907 return 0;
1908}
1909
1910static int vegam_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
1911{
1912 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1913 struct phm_ppt_v1_information *table_info =
1914 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1915 uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
1916 uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
1917 struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
1918
1919 hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
1920 lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
1921
1922 smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
1923 CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
1924 smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
1925 CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
1926
1927 return 0;
1928}
1929
1930static int vegam_populate_pm_fuses(struct pp_hwmgr *hwmgr)
1931{
1932 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
1933 uint32_t pm_fuse_table_offset;
1934
1935 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1936 PHM_PlatformCaps_PowerContainment)) {
1937 if (smu7_read_smc_sram_dword(hwmgr,
1938 SMU7_FIRMWARE_HEADER_LOCATION +
1939 offsetof(SMU75_Firmware_Header, PmFuseTable),
1940 &pm_fuse_table_offset, SMC_RAM_END))
1941 PP_ASSERT_WITH_CODE(false,
1942 "Attempt to get pm_fuse_table_offset Failed!",
1943 return -EINVAL);
1944
1945 if (vegam_populate_svi_load_line(hwmgr))
1946 PP_ASSERT_WITH_CODE(false,
1947 "Attempt to populate SviLoadLine Failed!",
1948 return -EINVAL);
1949
1950 if (vegam_populate_tdc_limit(hwmgr))
1951 PP_ASSERT_WITH_CODE(false,
1952 "Attempt to populate TDCLimit Failed!", return -EINVAL);
1953
1954 if (vegam_populate_dw8(hwmgr, pm_fuse_table_offset))
1955 PP_ASSERT_WITH_CODE(false,
1956 "Attempt to populate TdcWaterfallCtl, "
1957 "LPMLTemperature Min and Max Failed!",
1958 return -EINVAL);
1959
1960 if (0 != vegam_populate_temperature_scaler(hwmgr))
1961 PP_ASSERT_WITH_CODE(false,
1962 "Attempt to populate LPMLTemperatureScaler Failed!",
1963 return -EINVAL);
1964
1965 if (vegam_populate_fuzzy_fan(hwmgr))
1966 PP_ASSERT_WITH_CODE(false,
1967 "Attempt to populate Fuzzy Fan Control parameters Failed!",
1968 return -EINVAL);
1969
1970 if (vegam_populate_gnb_lpml(hwmgr))
1971 PP_ASSERT_WITH_CODE(false,
1972 "Attempt to populate GnbLPML Failed!",
1973 return -EINVAL);
1974
1975 if (vegam_populate_bapm_vddc_base_leakage_sidd(hwmgr))
1976 PP_ASSERT_WITH_CODE(false,
1977 "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
1978 "Sidd Failed!", return -EINVAL);
1979
1980 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
1981 (uint8_t *)&smu_data->power_tune_table,
1982 (sizeof(struct SMU75_Discrete_PmFuses) - PMFUSES_AVFSSIZE),
1983 SMC_RAM_END))
1984 PP_ASSERT_WITH_CODE(false,
1985 "Attempt to download PmFuseTable Failed!",
1986 return -EINVAL);
1987 }
1988 return 0;
1989}
1990
1991static int vegam_enable_reconfig_cus(struct pp_hwmgr *hwmgr)
1992{
1993 struct amdgpu_device *adev = hwmgr->adev;
1994
1995 smum_send_msg_to_smc_with_parameter(hwmgr,
1996 PPSMC_MSG_EnableModeSwitchRLCNotification,
1997 adev->gfx.cu_info.number);
1998
1999 return 0;
2000}
2001
2002static int vegam_init_smc_table(struct pp_hwmgr *hwmgr)
2003{
2004 int result;
2005 struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
2006 struct vegam_smumgr *smu_data = (struct vegam_smumgr *)(hwmgr->smu_backend);
2007
2008 struct phm_ppt_v1_information *table_info =
2009 (struct phm_ppt_v1_information *)(hwmgr->pptable);
2010 struct SMU75_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2011 uint8_t i;
2012 struct pp_atomctrl_gpio_pin_assignment gpio_pin;
2013 struct phm_ppt_v1_gpio_table *gpio_table =
2014 (struct phm_ppt_v1_gpio_table *)table_info->gpio_table;
2015 pp_atomctrl_clock_dividers_vi dividers;
2016
2017 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2018 PHM_PlatformCaps_AutomaticDCTransition);
2019
2020 vegam_initialize_power_tune_defaults(hwmgr);
2021
2022 if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
2023 vegam_populate_smc_voltage_tables(hwmgr, table);
2024
2025 table->SystemFlags = 0;
2026 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2027 PHM_PlatformCaps_AutomaticDCTransition))
2028 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2029
2030 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2031 PHM_PlatformCaps_StepVddc))
2032 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2033
2034 if (hw_data->is_memory_gddr5)
2035 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2036
2037 if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
2038 result = vegam_populate_ulv_state(hwmgr, table);
2039 PP_ASSERT_WITH_CODE(!result,
2040 "Failed to initialize ULV state!", return result);
2041 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
2042 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
2043 }
2044
2045 result = vegam_populate_smc_link_level(hwmgr, table);
2046 PP_ASSERT_WITH_CODE(!result,
2047 "Failed to initialize Link Level!", return result);
2048
2049 result = vegam_populate_all_graphic_levels(hwmgr);
2050 PP_ASSERT_WITH_CODE(!result,
2051 "Failed to initialize Graphics Level!", return result);
2052
2053 result = vegam_populate_all_memory_levels(hwmgr);
2054 PP_ASSERT_WITH_CODE(!result,
2055 "Failed to initialize Memory Level!", return result);
2056
2057 result = vegam_populate_smc_acpi_level(hwmgr, table);
2058 PP_ASSERT_WITH_CODE(!result,
2059 "Failed to initialize ACPI Level!", return result);
2060
2061 result = vegam_populate_smc_vce_level(hwmgr, table);
2062 PP_ASSERT_WITH_CODE(!result,
2063 "Failed to initialize VCE Level!", return result);
2064
2065 result = vegam_populate_smc_samu_level(hwmgr, table);
2066 PP_ASSERT_WITH_CODE(!result,
2067 "Failed to initialize SAMU Level!", return result);
2068
2069
2070
2071
2072
2073 result = vegam_program_memory_timing_parameters(hwmgr);
2074 PP_ASSERT_WITH_CODE(!result,
2075 "Failed to Write ARB settings for the initial state.", return result);
2076
2077 result = vegam_populate_smc_uvd_level(hwmgr, table);
2078 PP_ASSERT_WITH_CODE(!result,
2079 "Failed to initialize UVD Level!", return result);
2080
2081 result = vegam_populate_smc_boot_level(hwmgr, table);
2082 PP_ASSERT_WITH_CODE(!result,
2083 "Failed to initialize Boot Level!", return result);
2084
2085 result = vegam_populate_smc_initial_state(hwmgr);
2086 PP_ASSERT_WITH_CODE(!result,
2087 "Failed to initialize Boot State!", return result);
2088
2089 result = vegam_populate_bapm_parameters_in_dpm_table(hwmgr);
2090 PP_ASSERT_WITH_CODE(!result,
2091 "Failed to populate BAPM Parameters!", return result);
2092
2093 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2094 PHM_PlatformCaps_ClockStretcher)) {
2095 result = vegam_populate_clock_stretcher_data_table(hwmgr);
2096 PP_ASSERT_WITH_CODE(!result,
2097 "Failed to populate Clock Stretcher Data Table!",
2098 return result);
2099 }
2100
2101 result = vegam_populate_avfs_parameters(hwmgr);
2102 PP_ASSERT_WITH_CODE(!result,
2103 "Failed to populate AVFS Parameters!", return result;);
2104
2105 table->CurrSclkPllRange = 0xff;
2106 table->GraphicsVoltageChangeEnable = 1;
2107 table->GraphicsThermThrottleEnable = 1;
2108 table->GraphicsInterval = 1;
2109 table->VoltageInterval = 1;
2110 table->ThermalInterval = 1;
2111 table->TemperatureLimitHigh =
2112 table_info->cac_dtp_table->usTargetOperatingTemp *
2113 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2114 table->TemperatureLimitLow =
2115 (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
2116 SMU7_Q88_FORMAT_CONVERSION_UNIT;
2117 table->MemoryVoltageChangeEnable = 1;
2118 table->MemoryInterval = 1;
2119 table->VoltageResponseTime = 0;
2120 table->PhaseResponseTime = 0;
2121 table->MemoryThermThrottleEnable = 1;
2122
2123 PP_ASSERT_WITH_CODE(hw_data->dpm_table.pcie_speed_table.count >= 1,
2124 "There must be 1 or more PCIE levels defined in PPTable.",
2125 return -EINVAL);
2126 table->PCIeBootLinkLevel =
2127 hw_data->dpm_table.pcie_speed_table.count;
2128 table->PCIeGenInterval = 1;
2129 table->VRConfig = 0;
2130
2131 result = vegam_populate_vr_config(hwmgr, table);
2132 PP_ASSERT_WITH_CODE(!result,
2133 "Failed to populate VRConfig setting!", return result);
2134
2135 table->ThermGpio = 17;
2136 table->SclkStepSize = 0x4000;
2137
2138 if (atomctrl_get_pp_assign_pin(hwmgr,
2139 VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2140 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2141 if (gpio_table)
2142 table->VRHotLevel =
2143 table_info->gpio_table->vrhot_triggered_sclk_dpm_index;
2144 } else {
2145 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2146 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2147 PHM_PlatformCaps_RegulatorHot);
2148 }
2149
2150 if (atomctrl_get_pp_assign_pin(hwmgr,
2151 PP_AC_DC_SWITCH_GPIO_PINID, &gpio_pin)) {
2152 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2153 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2154 PHM_PlatformCaps_AutomaticDCTransition) &&
2155 !smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme))
2156 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2157 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
2158 } else {
2159 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2160 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2161 PHM_PlatformCaps_AutomaticDCTransition);
2162 }
2163
2164
2165 if (atomctrl_get_pp_assign_pin(hwmgr,
2166 THERMAL_INT_OUTPUT_GPIO_PINID, &gpio_pin)) {
2167 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2168
2169
2170
2171
2172
2173
2174 table->ThermOutPolarity =
2175 (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A) &
2176 (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2177 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2178
2179
2180 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2181 PHM_PlatformCaps_RegulatorHot) &&
2182 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2183 PHM_PlatformCaps_CombinePCCWithThermalSignal))
2184 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2185 } else {
2186 table->ThermOutGpio = 17;
2187 table->ThermOutPolarity = 1;
2188 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2189 }
2190
2191
2192 for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2193 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
2194 smu_data->bif_sclk_table[i], ÷rs);
2195 PP_ASSERT_WITH_CODE(!result,
2196 "Can not find DFS divide id for Sclk",
2197 return result);
2198
2199 if (i == 0)
2200 table->Ulv.BifSclkDfs =
2201 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2202 else
2203 table->LinkLevel[i - 1].BifSclkDfs =
2204 PP_HOST_TO_SMC_US((uint16_t)(dividers.pll_post_divider));
2205 }
2206
2207 for (i = 0; i < SMU75_MAX_ENTRIES_SMIO; i++)
2208 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2209
2210 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2211 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2212 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2213 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2214 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2215 CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2216 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2217 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2218 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2219 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2220
2221
2222 result = smu7_copy_bytes_to_smc(hwmgr,
2223 smu_data->smu7_data.dpm_table_start +
2224 offsetof(SMU75_Discrete_DpmTable, SystemFlags),
2225 (uint8_t *)&(table->SystemFlags),
2226 sizeof(SMU75_Discrete_DpmTable) - 3 * sizeof(SMU75_PIDController),
2227 SMC_RAM_END);
2228 PP_ASSERT_WITH_CODE(!result,
2229 "Failed to upload dpm data to SMC memory!", return result);
2230
2231 result = vegam_populate_pm_fuses(hwmgr);
2232 PP_ASSERT_WITH_CODE(!result,
2233 "Failed to populate PM fuses to SMC memory!", return result);
2234
2235 result = vegam_enable_reconfig_cus(hwmgr);
2236 PP_ASSERT_WITH_CODE(!result,
2237 "Failed to enable reconfigurable CUs!", return result);
2238
2239 return 0;
2240}
2241
2242static uint32_t vegam_get_offsetof(uint32_t type, uint32_t member)
2243{
2244 switch (type) {
2245 case SMU_SoftRegisters:
2246 switch (member) {
2247 case HandshakeDisables:
2248 return offsetof(SMU75_SoftRegisters, HandshakeDisables);
2249 case VoltageChangeTimeout:
2250 return offsetof(SMU75_SoftRegisters, VoltageChangeTimeout);
2251 case AverageGraphicsActivity:
2252 return offsetof(SMU75_SoftRegisters, AverageGraphicsActivity);
2253 case PreVBlankGap:
2254 return offsetof(SMU75_SoftRegisters, PreVBlankGap);
2255 case VBlankTimeout:
2256 return offsetof(SMU75_SoftRegisters, VBlankTimeout);
2257 case UcodeLoadStatus:
2258 return offsetof(SMU75_SoftRegisters, UcodeLoadStatus);
2259 case DRAM_LOG_ADDR_H:
2260 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_H);
2261 case DRAM_LOG_ADDR_L:
2262 return offsetof(SMU75_SoftRegisters, DRAM_LOG_ADDR_L);
2263 case DRAM_LOG_PHY_ADDR_H:
2264 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2265 case DRAM_LOG_PHY_ADDR_L:
2266 return offsetof(SMU75_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2267 case DRAM_LOG_BUFF_SIZE:
2268 return offsetof(SMU75_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2269 }
2270 case SMU_Discrete_DpmTable:
2271 switch (member) {
2272 case UvdBootLevel:
2273 return offsetof(SMU75_Discrete_DpmTable, UvdBootLevel);
2274 case VceBootLevel:
2275 return offsetof(SMU75_Discrete_DpmTable, VceBootLevel);
2276 case SamuBootLevel:
2277 return offsetof(SMU75_Discrete_DpmTable, SamuBootLevel);
2278 case LowSclkInterruptThreshold:
2279 return offsetof(SMU75_Discrete_DpmTable, LowSclkInterruptThreshold);
2280 }
2281 }
2282 pr_warn("can't get the offset of type %x member %x\n", type, member);
2283 return 0;
2284}
2285
2286static int vegam_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2287{
2288 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2289
2290 if (data->need_update_smu7_dpm_table &
2291 (DPMTABLE_OD_UPDATE_SCLK +
2292 DPMTABLE_UPDATE_SCLK +
2293 DPMTABLE_UPDATE_MCLK))
2294 return vegam_program_memory_timing_parameters(hwmgr);
2295
2296 return 0;
2297}
2298
2299static int vegam_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2300{
2301 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2302 struct vegam_smumgr *smu_data =
2303 (struct vegam_smumgr *)(hwmgr->smu_backend);
2304 int result = 0;
2305 uint32_t low_sclk_interrupt_threshold = 0;
2306
2307 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2308 PHM_PlatformCaps_SclkThrottleLowNotification)
2309 && (data->low_sclk_interrupt_threshold != 0)) {
2310 low_sclk_interrupt_threshold =
2311 data->low_sclk_interrupt_threshold;
2312
2313 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2314
2315 result = smu7_copy_bytes_to_smc(
2316 hwmgr,
2317 smu_data->smu7_data.dpm_table_start +
2318 offsetof(SMU75_Discrete_DpmTable,
2319 LowSclkInterruptThreshold),
2320 (uint8_t *)&low_sclk_interrupt_threshold,
2321 sizeof(uint32_t),
2322 SMC_RAM_END);
2323 }
2324 PP_ASSERT_WITH_CODE((result == 0),
2325 "Failed to update SCLK threshold!", return result);
2326
2327 result = vegam_program_mem_timing_parameters(hwmgr);
2328 PP_ASSERT_WITH_CODE((result == 0),
2329 "Failed to program memory timing parameters!",
2330 );
2331
2332 return result;
2333}
2334
2335int vegam_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2336{
2337 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2338 int ret;
2339
2340 if (!hwmgr->avfs_supported)
2341 return 0;
2342
2343 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
2344 if (!ret) {
2345 if (data->apply_avfs_cks_off_voltage)
2346 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
2347 }
2348
2349 return ret;
2350}
2351
2352static int vegam_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2353{
2354 PP_ASSERT_WITH_CODE(hwmgr->thermal_controller.fanInfo.bNoFan,
2355 "VBIOS fan info is not correct!",
2356 );
2357 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2358 PHM_PlatformCaps_MicrocodeFanControl);
2359 return 0;
2360}
2361
2362const struct pp_smumgr_func vegam_smu_funcs = {
2363 .smu_init = vegam_smu_init,
2364 .smu_fini = smu7_smu_fini,
2365 .start_smu = vegam_start_smu,
2366 .check_fw_load_finish = smu7_check_fw_load_finish,
2367 .request_smu_load_fw = smu7_reload_firmware,
2368 .request_smu_load_specific_fw = NULL,
2369 .send_msg_to_smc = smu7_send_msg_to_smc,
2370 .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2371 .process_firmware_header = vegam_process_firmware_header,
2372 .is_dpm_running = vegam_is_dpm_running,
2373 .get_mac_definition = vegam_get_mac_definition,
2374 .update_smc_table = vegam_update_smc_table,
2375 .init_smc_table = vegam_init_smc_table,
2376 .get_offsetof = vegam_get_offsetof,
2377 .populate_all_graphic_levels = vegam_populate_all_graphic_levels,
2378 .populate_all_memory_levels = vegam_populate_all_memory_levels,
2379 .update_sclk_threshold = vegam_update_sclk_threshold,
2380 .is_hw_avfs_present = vegam_is_hw_avfs_present,
2381 .thermal_avfs_enable = vegam_thermal_avfs_enable,
2382 .thermal_setup_fan_table = vegam_thermal_setup_fan_table,
2383};
2384
