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14#include <linux/kernel.h>
15#include <linux/component.h>
16#include <linux/platform_device.h>
17#include <linux/clk.h>
18#include <linux/pm_runtime.h>
19#include <linux/mfd/syscon.h>
20#include <linux/of_device.h>
21#include <linux/regmap.h>
22
23#include <drm/drmP.h>
24#include <drm/exynos_drm.h>
25#include "regs-gsc.h"
26#include "exynos_drm_drv.h"
27#include "exynos_drm_iommu.h"
28#include "exynos_drm_ipp.h"
29
30
31
32
33
34
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36
37
38
39#define GSC_MAX_CLOCKS 8
40#define GSC_MAX_SRC 4
41#define GSC_MAX_DST 16
42#define GSC_RESET_TIMEOUT 50
43#define GSC_BUF_STOP 1
44#define GSC_BUF_START 2
45#define GSC_REG_SZ 16
46#define GSC_WIDTH_ITU_709 1280
47#define GSC_SC_UP_MAX_RATIO 65536
48#define GSC_SC_DOWN_RATIO_7_8 74898
49#define GSC_SC_DOWN_RATIO_6_8 87381
50#define GSC_SC_DOWN_RATIO_5_8 104857
51#define GSC_SC_DOWN_RATIO_4_8 131072
52#define GSC_SC_DOWN_RATIO_3_8 174762
53#define GSC_SC_DOWN_RATIO_2_8 262144
54#define GSC_CROP_MAX 8192
55#define GSC_CROP_MIN 32
56#define GSC_SCALE_MAX 4224
57#define GSC_SCALE_MIN 32
58#define GSC_COEF_RATIO 7
59#define GSC_COEF_PHASE 9
60#define GSC_COEF_ATTR 16
61#define GSC_COEF_H_8T 8
62#define GSC_COEF_V_4T 4
63#define GSC_COEF_DEPTH 3
64#define GSC_AUTOSUSPEND_DELAY 2000
65
66#define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
67#define gsc_read(offset) readl(ctx->regs + (offset))
68#define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
69
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78
79
80struct gsc_scaler {
81 bool range;
82 u32 pre_shfactor;
83 u32 pre_hratio;
84 u32 pre_vratio;
85 unsigned long main_hratio;
86 unsigned long main_vratio;
87};
88
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98
99
100struct gsc_context {
101 struct exynos_drm_ipp ipp;
102 struct drm_device *drm_dev;
103 struct device *dev;
104 struct exynos_drm_ipp_task *task;
105 struct exynos_drm_ipp_formats *formats;
106 unsigned int num_formats;
107
108 struct resource *regs_res;
109 void __iomem *regs;
110 const char **clk_names;
111 struct clk *clocks[GSC_MAX_CLOCKS];
112 int num_clocks;
113 struct gsc_scaler sc;
114 int id;
115 int irq;
116 bool rotation;
117};
118
119
120
121
122
123
124
125
126struct gsc_driverdata {
127 const struct drm_exynos_ipp_limit *limits;
128 int num_limits;
129 const char *clk_names[GSC_MAX_CLOCKS];
130 int num_clocks;
131};
132
133
134static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
135 {
136 { 0, 0, 0, 128, 0, 0, 0, 0 },
137 { -1, 2, -6, 127, 7, -2, 1, 0 },
138 { -1, 4, -12, 125, 16, -5, 1, 0 },
139 { -1, 5, -15, 120, 25, -8, 2, 0 },
140 { -1, 6, -18, 114, 35, -10, 3, -1 },
141 { -1, 6, -20, 107, 46, -13, 4, -1 },
142 { -2, 7, -21, 99, 57, -16, 5, -1 },
143 { -1, 6, -20, 89, 68, -18, 5, -1 },
144 { -1, 6, -20, 79, 79, -20, 6, -1 },
145 { -1, 5, -18, 68, 89, -20, 6, -1 },
146 { -1, 5, -16, 57, 99, -21, 7, -2 },
147 { -1, 4, -13, 46, 107, -20, 6, -1 },
148 { -1, 3, -10, 35, 114, -18, 6, -1 },
149 { 0, 2, -8, 25, 120, -15, 5, -1 },
150 { 0, 1, -5, 16, 125, -12, 4, -1 },
151 { 0, 1, -2, 7, 127, -6, 2, -1 }
152 }, {
153 { 3, -8, 14, 111, 13, -8, 3, 0 },
154 { 2, -6, 7, 112, 21, -10, 3, -1 },
155 { 2, -4, 1, 110, 28, -12, 4, -1 },
156 { 1, -2, -3, 106, 36, -13, 4, -1 },
157 { 1, -1, -7, 103, 44, -15, 4, -1 },
158 { 1, 1, -11, 97, 53, -16, 4, -1 },
159 { 0, 2, -13, 91, 61, -16, 4, -1 },
160 { 0, 3, -15, 85, 69, -17, 4, -1 },
161 { 0, 3, -16, 77, 77, -16, 3, 0 },
162 { -1, 4, -17, 69, 85, -15, 3, 0 },
163 { -1, 4, -16, 61, 91, -13, 2, 0 },
164 { -1, 4, -16, 53, 97, -11, 1, 1 },
165 { -1, 4, -15, 44, 103, -7, -1, 1 },
166 { -1, 4, -13, 36, 106, -3, -2, 1 },
167 { -1, 4, -12, 28, 110, 1, -4, 2 },
168 { -1, 3, -10, 21, 112, 7, -6, 2 }
169 }, {
170 { 2, -11, 25, 96, 25, -11, 2, 0 },
171 { 2, -10, 19, 96, 31, -12, 2, 0 },
172 { 2, -9, 14, 94, 37, -12, 2, 0 },
173 { 2, -8, 10, 92, 43, -12, 1, 0 },
174 { 2, -7, 5, 90, 49, -12, 1, 0 },
175 { 2, -5, 1, 86, 55, -12, 0, 1 },
176 { 2, -4, -2, 82, 61, -11, -1, 1 },
177 { 1, -3, -5, 77, 67, -9, -1, 1 },
178 { 1, -2, -7, 72, 72, -7, -2, 1 },
179 { 1, -1, -9, 67, 77, -5, -3, 1 },
180 { 1, -1, -11, 61, 82, -2, -4, 2 },
181 { 1, 0, -12, 55, 86, 1, -5, 2 },
182 { 0, 1, -12, 49, 90, 5, -7, 2 },
183 { 0, 1, -12, 43, 92, 10, -8, 2 },
184 { 0, 2, -12, 37, 94, 14, -9, 2 },
185 { 0, 2, -12, 31, 96, 19, -10, 2 }
186 }, {
187 { -1, -8, 33, 80, 33, -8, -1, 0 },
188 { -1, -8, 28, 80, 37, -7, -2, 1 },
189 { 0, -8, 24, 79, 41, -7, -2, 1 },
190 { 0, -8, 20, 78, 46, -6, -3, 1 },
191 { 0, -8, 16, 76, 50, -4, -3, 1 },
192 { 0, -7, 13, 74, 54, -3, -4, 1 },
193 { 1, -7, 10, 71, 58, -1, -5, 1 },
194 { 1, -6, 6, 68, 62, 1, -5, 1 },
195 { 1, -6, 4, 65, 65, 4, -6, 1 },
196 { 1, -5, 1, 62, 68, 6, -6, 1 },
197 { 1, -5, -1, 58, 71, 10, -7, 1 },
198 { 1, -4, -3, 54, 74, 13, -7, 0 },
199 { 1, -3, -4, 50, 76, 16, -8, 0 },
200 { 1, -3, -6, 46, 78, 20, -8, 0 },
201 { 1, -2, -7, 41, 79, 24, -8, 0 },
202 { 1, -2, -7, 37, 80, 28, -8, -1 }
203 }, {
204 { -3, 0, 35, 64, 35, 0, -3, 0 },
205 { -3, -1, 32, 64, 38, 1, -3, 0 },
206 { -2, -2, 29, 63, 41, 2, -3, 0 },
207 { -2, -3, 27, 63, 43, 4, -4, 0 },
208 { -2, -3, 24, 61, 46, 6, -4, 0 },
209 { -2, -3, 21, 60, 49, 7, -4, 0 },
210 { -1, -4, 19, 59, 51, 9, -4, -1 },
211 { -1, -4, 16, 57, 53, 12, -4, -1 },
212 { -1, -4, 14, 55, 55, 14, -4, -1 },
213 { -1, -4, 12, 53, 57, 16, -4, -1 },
214 { -1, -4, 9, 51, 59, 19, -4, -1 },
215 { 0, -4, 7, 49, 60, 21, -3, -2 },
216 { 0, -4, 6, 46, 61, 24, -3, -2 },
217 { 0, -4, 4, 43, 63, 27, -3, -2 },
218 { 0, -3, 2, 41, 63, 29, -2, -2 },
219 { 0, -3, 1, 38, 64, 32, -1, -3 }
220 }, {
221 { -1, 8, 33, 48, 33, 8, -1, 0 },
222 { -1, 7, 31, 49, 35, 9, -1, -1 },
223 { -1, 6, 30, 49, 36, 10, -1, -1 },
224 { -1, 5, 28, 48, 38, 12, -1, -1 },
225 { -1, 4, 26, 48, 39, 13, 0, -1 },
226 { -1, 3, 24, 47, 41, 15, 0, -1 },
227 { -1, 2, 23, 47, 42, 16, 0, -1 },
228 { -1, 2, 21, 45, 43, 18, 1, -1 },
229 { -1, 1, 19, 45, 45, 19, 1, -1 },
230 { -1, 1, 18, 43, 45, 21, 2, -1 },
231 { -1, 0, 16, 42, 47, 23, 2, -1 },
232 { -1, 0, 15, 41, 47, 24, 3, -1 },
233 { -1, 0, 13, 39, 48, 26, 4, -1 },
234 { -1, -1, 12, 38, 48, 28, 5, -1 },
235 { -1, -1, 10, 36, 49, 30, 6, -1 },
236 { -1, -1, 9, 35, 49, 31, 7, -1 }
237 }, {
238 { 2, 13, 30, 38, 30, 13, 2, 0 },
239 { 2, 12, 29, 38, 30, 14, 3, 0 },
240 { 2, 11, 28, 38, 31, 15, 3, 0 },
241 { 2, 10, 26, 38, 32, 16, 4, 0 },
242 { 1, 10, 26, 37, 33, 17, 4, 0 },
243 { 1, 9, 24, 37, 34, 18, 5, 0 },
244 { 1, 8, 24, 37, 34, 19, 5, 0 },
245 { 1, 7, 22, 36, 35, 20, 6, 1 },
246 { 1, 6, 21, 36, 36, 21, 6, 1 },
247 { 1, 6, 20, 35, 36, 22, 7, 1 },
248 { 0, 5, 19, 34, 37, 24, 8, 1 },
249 { 0, 5, 18, 34, 37, 24, 9, 1 },
250 { 0, 4, 17, 33, 37, 26, 10, 1 },
251 { 0, 4, 16, 32, 38, 26, 10, 2 },
252 { 0, 3, 15, 31, 38, 28, 11, 2 },
253 { 0, 3, 14, 30, 38, 29, 12, 2 }
254 }
255};
256
257
258static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
259 {
260 { 0, 128, 0, 0 },
261 { -4, 127, 5, 0 },
262 { -6, 124, 11, -1 },
263 { -8, 118, 19, -1 },
264 { -8, 111, 27, -2 },
265 { -8, 102, 37, -3 },
266 { -8, 92, 48, -4 },
267 { -7, 81, 59, -5 },
268 { -6, 70, 70, -6 },
269 { -5, 59, 81, -7 },
270 { -4, 48, 92, -8 },
271 { -3, 37, 102, -8 },
272 { -2, 27, 111, -8 },
273 { -1, 19, 118, -8 },
274 { -1, 11, 124, -6 },
275 { 0, 5, 127, -4 }
276 }, {
277 { 8, 112, 8, 0 },
278 { 4, 111, 14, -1 },
279 { 1, 109, 20, -2 },
280 { -2, 105, 27, -2 },
281 { -3, 100, 34, -3 },
282 { -5, 93, 43, -3 },
283 { -5, 86, 51, -4 },
284 { -5, 77, 60, -4 },
285 { -5, 69, 69, -5 },
286 { -4, 60, 77, -5 },
287 { -4, 51, 86, -5 },
288 { -3, 43, 93, -5 },
289 { -3, 34, 100, -3 },
290 { -2, 27, 105, -2 },
291 { -2, 20, 109, 1 },
292 { -1, 14, 111, 4 }
293 }, {
294 { 16, 96, 16, 0 },
295 { 12, 97, 21, -2 },
296 { 8, 96, 26, -2 },
297 { 5, 93, 32, -2 },
298 { 2, 89, 39, -2 },
299 { 0, 84, 46, -2 },
300 { -1, 79, 53, -3 },
301 { -2, 73, 59, -2 },
302 { -2, 66, 66, -2 },
303 { -2, 59, 73, -2 },
304 { -3, 53, 79, -1 },
305 { -2, 46, 84, 0 },
306 { -2, 39, 89, 2 },
307 { -2, 32, 93, 5 },
308 { -2, 26, 96, 8 },
309 { -2, 21, 97, 12 }
310 }, {
311 { 22, 84, 22, 0 },
312 { 18, 85, 26, -1 },
313 { 14, 84, 31, -1 },
314 { 11, 82, 36, -1 },
315 { 8, 79, 42, -1 },
316 { 6, 76, 47, -1 },
317 { 4, 72, 52, 0 },
318 { 2, 68, 58, 0 },
319 { 1, 63, 63, 1 },
320 { 0, 58, 68, 2 },
321 { 0, 52, 72, 4 },
322 { -1, 47, 76, 6 },
323 { -1, 42, 79, 8 },
324 { -1, 36, 82, 11 },
325 { -1, 31, 84, 14 },
326 { -1, 26, 85, 18 }
327 }, {
328 { 26, 76, 26, 0 },
329 { 22, 76, 30, 0 },
330 { 19, 75, 34, 0 },
331 { 16, 73, 38, 1 },
332 { 13, 71, 43, 1 },
333 { 10, 69, 47, 2 },
334 { 8, 66, 51, 3 },
335 { 6, 63, 55, 4 },
336 { 5, 59, 59, 5 },
337 { 4, 55, 63, 6 },
338 { 3, 51, 66, 8 },
339 { 2, 47, 69, 10 },
340 { 1, 43, 71, 13 },
341 { 1, 38, 73, 16 },
342 { 0, 34, 75, 19 },
343 { 0, 30, 76, 22 }
344 }, {
345 { 29, 70, 29, 0 },
346 { 26, 68, 32, 2 },
347 { 23, 67, 36, 2 },
348 { 20, 66, 39, 3 },
349 { 17, 65, 43, 3 },
350 { 15, 63, 46, 4 },
351 { 12, 61, 50, 5 },
352 { 10, 58, 53, 7 },
353 { 8, 56, 56, 8 },
354 { 7, 53, 58, 10 },
355 { 5, 50, 61, 12 },
356 { 4, 46, 63, 15 },
357 { 3, 43, 65, 17 },
358 { 3, 39, 66, 20 },
359 { 2, 36, 67, 23 },
360 { 2, 32, 68, 26 }
361 }, {
362 { 32, 64, 32, 0 },
363 { 28, 63, 34, 3 },
364 { 25, 62, 37, 4 },
365 { 22, 62, 40, 4 },
366 { 19, 61, 43, 5 },
367 { 17, 59, 46, 6 },
368 { 15, 58, 48, 7 },
369 { 13, 55, 51, 9 },
370 { 11, 53, 53, 11 },
371 { 9, 51, 55, 13 },
372 { 7, 48, 58, 15 },
373 { 6, 46, 59, 17 },
374 { 5, 43, 61, 19 },
375 { 4, 40, 62, 22 },
376 { 4, 37, 62, 25 },
377 { 3, 34, 63, 28 }
378 }
379};
380
381static int gsc_sw_reset(struct gsc_context *ctx)
382{
383 u32 cfg;
384 int count = GSC_RESET_TIMEOUT;
385
386
387 cfg = (GSC_SW_RESET_SRESET);
388 gsc_write(cfg, GSC_SW_RESET);
389
390
391 while (count--) {
392 cfg = gsc_read(GSC_SW_RESET);
393 if (!cfg)
394 break;
395 usleep_range(1000, 2000);
396 }
397
398 if (cfg) {
399 DRM_ERROR("failed to reset gsc h/w.\n");
400 return -EBUSY;
401 }
402
403
404 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
405 cfg |= (GSC_IN_BASE_ADDR_MASK |
406 GSC_IN_BASE_ADDR_PINGPONG(0));
407 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
408 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
409 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
410
411 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
412 cfg |= (GSC_OUT_BASE_ADDR_MASK |
413 GSC_OUT_BASE_ADDR_PINGPONG(0));
414 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
415 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
416 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
417
418 return 0;
419}
420
421static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
422 bool overflow, bool done)
423{
424 u32 cfg;
425
426 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
427 enable, overflow, done);
428
429 cfg = gsc_read(GSC_IRQ);
430 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
431
432 if (enable)
433 cfg |= GSC_IRQ_ENABLE;
434 else
435 cfg &= ~GSC_IRQ_ENABLE;
436
437 if (overflow)
438 cfg &= ~GSC_IRQ_OR_MASK;
439 else
440 cfg |= GSC_IRQ_OR_MASK;
441
442 if (done)
443 cfg &= ~GSC_IRQ_FRMDONE_MASK;
444 else
445 cfg |= GSC_IRQ_FRMDONE_MASK;
446
447 gsc_write(cfg, GSC_IRQ);
448}
449
450
451static void gsc_src_set_fmt(struct gsc_context *ctx, u32 fmt)
452{
453 u32 cfg;
454
455 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
456
457 cfg = gsc_read(GSC_IN_CON);
458 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
459 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
460 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
461 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
462
463 switch (fmt) {
464 case DRM_FORMAT_RGB565:
465 cfg |= GSC_IN_RGB565;
466 break;
467 case DRM_FORMAT_XRGB8888:
468 case DRM_FORMAT_ARGB8888:
469 cfg |= GSC_IN_XRGB8888;
470 break;
471 case DRM_FORMAT_BGRX8888:
472 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
473 break;
474 case DRM_FORMAT_YUYV:
475 cfg |= (GSC_IN_YUV422_1P |
476 GSC_IN_YUV422_1P_ORDER_LSB_Y |
477 GSC_IN_CHROMA_ORDER_CBCR);
478 break;
479 case DRM_FORMAT_YVYU:
480 cfg |= (GSC_IN_YUV422_1P |
481 GSC_IN_YUV422_1P_ORDER_LSB_Y |
482 GSC_IN_CHROMA_ORDER_CRCB);
483 break;
484 case DRM_FORMAT_UYVY:
485 cfg |= (GSC_IN_YUV422_1P |
486 GSC_IN_YUV422_1P_OEDER_LSB_C |
487 GSC_IN_CHROMA_ORDER_CBCR);
488 break;
489 case DRM_FORMAT_VYUY:
490 cfg |= (GSC_IN_YUV422_1P |
491 GSC_IN_YUV422_1P_OEDER_LSB_C |
492 GSC_IN_CHROMA_ORDER_CRCB);
493 break;
494 case DRM_FORMAT_NV21:
495 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
496 break;
497 case DRM_FORMAT_NV61:
498 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
499 break;
500 case DRM_FORMAT_YUV422:
501 cfg |= GSC_IN_YUV422_3P;
502 break;
503 case DRM_FORMAT_YUV420:
504 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
505 break;
506 case DRM_FORMAT_YVU420:
507 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
508 break;
509 case DRM_FORMAT_NV12:
510 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
511 break;
512 case DRM_FORMAT_NV16:
513 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
514 break;
515 }
516
517 gsc_write(cfg, GSC_IN_CON);
518}
519
520static void gsc_src_set_transf(struct gsc_context *ctx, unsigned int rotation)
521{
522 unsigned int degree = rotation & DRM_MODE_ROTATE_MASK;
523 u32 cfg;
524
525 cfg = gsc_read(GSC_IN_CON);
526 cfg &= ~GSC_IN_ROT_MASK;
527
528 switch (degree) {
529 case DRM_MODE_ROTATE_0:
530 if (rotation & DRM_MODE_REFLECT_X)
531 cfg |= GSC_IN_ROT_XFLIP;
532 if (rotation & DRM_MODE_REFLECT_Y)
533 cfg |= GSC_IN_ROT_YFLIP;
534 break;
535 case DRM_MODE_ROTATE_90:
536 cfg |= GSC_IN_ROT_90;
537 if (rotation & DRM_MODE_REFLECT_X)
538 cfg |= GSC_IN_ROT_XFLIP;
539 if (rotation & DRM_MODE_REFLECT_Y)
540 cfg |= GSC_IN_ROT_YFLIP;
541 break;
542 case DRM_MODE_ROTATE_180:
543 cfg |= GSC_IN_ROT_180;
544 if (rotation & DRM_MODE_REFLECT_X)
545 cfg &= ~GSC_IN_ROT_XFLIP;
546 if (rotation & DRM_MODE_REFLECT_Y)
547 cfg &= ~GSC_IN_ROT_YFLIP;
548 break;
549 case DRM_MODE_ROTATE_270:
550 cfg |= GSC_IN_ROT_270;
551 if (rotation & DRM_MODE_REFLECT_X)
552 cfg &= ~GSC_IN_ROT_XFLIP;
553 if (rotation & DRM_MODE_REFLECT_Y)
554 cfg &= ~GSC_IN_ROT_YFLIP;
555 break;
556 }
557
558 gsc_write(cfg, GSC_IN_CON);
559
560 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
561}
562
563static void gsc_src_set_size(struct gsc_context *ctx,
564 struct exynos_drm_ipp_buffer *buf)
565{
566 struct gsc_scaler *sc = &ctx->sc;
567 u32 cfg;
568
569
570 cfg = (GSC_SRCIMG_OFFSET_X(buf->rect.x) |
571 GSC_SRCIMG_OFFSET_Y(buf->rect.y));
572 gsc_write(cfg, GSC_SRCIMG_OFFSET);
573
574
575 cfg = (GSC_CROPPED_WIDTH(buf->rect.w) |
576 GSC_CROPPED_HEIGHT(buf->rect.h));
577 gsc_write(cfg, GSC_CROPPED_SIZE);
578
579
580 cfg = gsc_read(GSC_SRCIMG_SIZE);
581 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
582 GSC_SRCIMG_WIDTH_MASK);
583
584 cfg |= (GSC_SRCIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
585 GSC_SRCIMG_HEIGHT(buf->buf.height));
586
587 gsc_write(cfg, GSC_SRCIMG_SIZE);
588
589 cfg = gsc_read(GSC_IN_CON);
590 cfg &= ~GSC_IN_RGB_TYPE_MASK;
591
592 if (buf->rect.w >= GSC_WIDTH_ITU_709)
593 if (sc->range)
594 cfg |= GSC_IN_RGB_HD_WIDE;
595 else
596 cfg |= GSC_IN_RGB_HD_NARROW;
597 else
598 if (sc->range)
599 cfg |= GSC_IN_RGB_SD_WIDE;
600 else
601 cfg |= GSC_IN_RGB_SD_NARROW;
602
603 gsc_write(cfg, GSC_IN_CON);
604}
605
606static void gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
607 bool enqueue)
608{
609 bool masked = !enqueue;
610 u32 cfg;
611 u32 mask = 0x00000001 << buf_id;
612
613
614 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
615
616
617 cfg &= ~mask;
618 cfg |= masked << buf_id;
619 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
620 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
621 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
622}
623
624static void gsc_src_set_addr(struct gsc_context *ctx, u32 buf_id,
625 struct exynos_drm_ipp_buffer *buf)
626{
627
628 gsc_write(buf->dma_addr[0], GSC_IN_BASE_ADDR_Y(buf_id));
629 gsc_write(buf->dma_addr[1], GSC_IN_BASE_ADDR_CB(buf_id));
630 gsc_write(buf->dma_addr[2], GSC_IN_BASE_ADDR_CR(buf_id));
631
632 gsc_src_set_buf_seq(ctx, buf_id, true);
633}
634
635static void gsc_dst_set_fmt(struct gsc_context *ctx, u32 fmt)
636{
637 u32 cfg;
638
639 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
640
641 cfg = gsc_read(GSC_OUT_CON);
642 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
643 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
644 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
645 GSC_OUT_GLOBAL_ALPHA_MASK);
646
647 switch (fmt) {
648 case DRM_FORMAT_RGB565:
649 cfg |= GSC_OUT_RGB565;
650 break;
651 case DRM_FORMAT_ARGB8888:
652 case DRM_FORMAT_XRGB8888:
653 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_GLOBAL_ALPHA(0xff));
654 break;
655 case DRM_FORMAT_BGRX8888:
656 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
657 break;
658 case DRM_FORMAT_YUYV:
659 cfg |= (GSC_OUT_YUV422_1P |
660 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
661 GSC_OUT_CHROMA_ORDER_CBCR);
662 break;
663 case DRM_FORMAT_YVYU:
664 cfg |= (GSC_OUT_YUV422_1P |
665 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
666 GSC_OUT_CHROMA_ORDER_CRCB);
667 break;
668 case DRM_FORMAT_UYVY:
669 cfg |= (GSC_OUT_YUV422_1P |
670 GSC_OUT_YUV422_1P_OEDER_LSB_C |
671 GSC_OUT_CHROMA_ORDER_CBCR);
672 break;
673 case DRM_FORMAT_VYUY:
674 cfg |= (GSC_OUT_YUV422_1P |
675 GSC_OUT_YUV422_1P_OEDER_LSB_C |
676 GSC_OUT_CHROMA_ORDER_CRCB);
677 break;
678 case DRM_FORMAT_NV21:
679 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
680 break;
681 case DRM_FORMAT_NV61:
682 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
683 break;
684 case DRM_FORMAT_YUV422:
685 cfg |= GSC_OUT_YUV422_3P;
686 break;
687 case DRM_FORMAT_YUV420:
688 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
689 break;
690 case DRM_FORMAT_YVU420:
691 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
692 break;
693 case DRM_FORMAT_NV12:
694 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
695 break;
696 case DRM_FORMAT_NV16:
697 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
698 break;
699 }
700
701 gsc_write(cfg, GSC_OUT_CON);
702}
703
704static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
705{
706 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
707
708 if (src >= dst * 8) {
709 DRM_ERROR("failed to make ratio and shift.\n");
710 return -EINVAL;
711 } else if (src >= dst * 4)
712 *ratio = 4;
713 else if (src >= dst * 2)
714 *ratio = 2;
715 else
716 *ratio = 1;
717
718 return 0;
719}
720
721static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
722{
723 if (hratio == 4 && vratio == 4)
724 *shfactor = 4;
725 else if ((hratio == 4 && vratio == 2) ||
726 (hratio == 2 && vratio == 4))
727 *shfactor = 3;
728 else if ((hratio == 4 && vratio == 1) ||
729 (hratio == 1 && vratio == 4) ||
730 (hratio == 2 && vratio == 2))
731 *shfactor = 2;
732 else if (hratio == 1 && vratio == 1)
733 *shfactor = 0;
734 else
735 *shfactor = 1;
736}
737
738static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
739 struct drm_exynos_ipp_task_rect *src,
740 struct drm_exynos_ipp_task_rect *dst)
741{
742 u32 cfg;
743 u32 src_w, src_h, dst_w, dst_h;
744 int ret = 0;
745
746 src_w = src->w;
747 src_h = src->h;
748
749 if (ctx->rotation) {
750 dst_w = dst->h;
751 dst_h = dst->w;
752 } else {
753 dst_w = dst->w;
754 dst_h = dst->h;
755 }
756
757 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
758 if (ret) {
759 dev_err(ctx->dev, "failed to get ratio horizontal.\n");
760 return ret;
761 }
762
763 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
764 if (ret) {
765 dev_err(ctx->dev, "failed to get ratio vertical.\n");
766 return ret;
767 }
768
769 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
770 sc->pre_hratio, sc->pre_vratio);
771
772 sc->main_hratio = (src_w << 16) / dst_w;
773 sc->main_vratio = (src_h << 16) / dst_h;
774
775 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
776 sc->main_hratio, sc->main_vratio);
777
778 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
779 &sc->pre_shfactor);
780
781 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
782
783 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
784 GSC_PRESC_H_RATIO(sc->pre_hratio) |
785 GSC_PRESC_V_RATIO(sc->pre_vratio));
786 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
787
788 return ret;
789}
790
791static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
792{
793 int i, j, k, sc_ratio;
794
795 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
796 sc_ratio = 0;
797 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
798 sc_ratio = 1;
799 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
800 sc_ratio = 2;
801 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
802 sc_ratio = 3;
803 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
804 sc_ratio = 4;
805 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
806 sc_ratio = 5;
807 else
808 sc_ratio = 6;
809
810 for (i = 0; i < GSC_COEF_PHASE; i++)
811 for (j = 0; j < GSC_COEF_H_8T; j++)
812 for (k = 0; k < GSC_COEF_DEPTH; k++)
813 gsc_write(h_coef_8t[sc_ratio][i][j],
814 GSC_HCOEF(i, j, k));
815}
816
817static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
818{
819 int i, j, k, sc_ratio;
820
821 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
822 sc_ratio = 0;
823 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
824 sc_ratio = 1;
825 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
826 sc_ratio = 2;
827 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
828 sc_ratio = 3;
829 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
830 sc_ratio = 4;
831 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
832 sc_ratio = 5;
833 else
834 sc_ratio = 6;
835
836 for (i = 0; i < GSC_COEF_PHASE; i++)
837 for (j = 0; j < GSC_COEF_V_4T; j++)
838 for (k = 0; k < GSC_COEF_DEPTH; k++)
839 gsc_write(v_coef_4t[sc_ratio][i][j],
840 GSC_VCOEF(i, j, k));
841}
842
843static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
844{
845 u32 cfg;
846
847 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
848 sc->main_hratio, sc->main_vratio);
849
850 gsc_set_h_coef(ctx, sc->main_hratio);
851 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
852 gsc_write(cfg, GSC_MAIN_H_RATIO);
853
854 gsc_set_v_coef(ctx, sc->main_vratio);
855 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
856 gsc_write(cfg, GSC_MAIN_V_RATIO);
857}
858
859static void gsc_dst_set_size(struct gsc_context *ctx,
860 struct exynos_drm_ipp_buffer *buf)
861{
862 struct gsc_scaler *sc = &ctx->sc;
863 u32 cfg;
864
865
866 cfg = (GSC_DSTIMG_OFFSET_X(buf->rect.x) |
867 GSC_DSTIMG_OFFSET_Y(buf->rect.y));
868 gsc_write(cfg, GSC_DSTIMG_OFFSET);
869
870
871 if (ctx->rotation)
872 cfg = (GSC_SCALED_WIDTH(buf->rect.h) |
873 GSC_SCALED_HEIGHT(buf->rect.w));
874 else
875 cfg = (GSC_SCALED_WIDTH(buf->rect.w) |
876 GSC_SCALED_HEIGHT(buf->rect.h));
877 gsc_write(cfg, GSC_SCALED_SIZE);
878
879
880 cfg = gsc_read(GSC_DSTIMG_SIZE);
881 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | GSC_DSTIMG_WIDTH_MASK);
882 cfg |= GSC_DSTIMG_WIDTH(buf->buf.pitch[0] / buf->format->cpp[0]) |
883 GSC_DSTIMG_HEIGHT(buf->buf.height);
884 gsc_write(cfg, GSC_DSTIMG_SIZE);
885
886 cfg = gsc_read(GSC_OUT_CON);
887 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
888
889 if (buf->rect.w >= GSC_WIDTH_ITU_709)
890 if (sc->range)
891 cfg |= GSC_OUT_RGB_HD_WIDE;
892 else
893 cfg |= GSC_OUT_RGB_HD_NARROW;
894 else
895 if (sc->range)
896 cfg |= GSC_OUT_RGB_SD_WIDE;
897 else
898 cfg |= GSC_OUT_RGB_SD_NARROW;
899
900 gsc_write(cfg, GSC_OUT_CON);
901}
902
903static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
904{
905 u32 cfg, i, buf_num = GSC_REG_SZ;
906 u32 mask = 0x00000001;
907
908 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
909
910 for (i = 0; i < GSC_REG_SZ; i++)
911 if (cfg & (mask << i))
912 buf_num--;
913
914 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
915
916 return buf_num;
917}
918
919static void gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
920 bool enqueue)
921{
922 bool masked = !enqueue;
923 u32 cfg;
924 u32 mask = 0x00000001 << buf_id;
925
926
927 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
928
929
930 cfg &= ~mask;
931 cfg |= masked << buf_id;
932 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
933 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
934 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
935
936
937 if (enqueue && gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
938 gsc_handle_irq(ctx, true, false, true);
939
940
941 if (!enqueue && gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
942 gsc_handle_irq(ctx, false, false, true);
943}
944
945static void gsc_dst_set_addr(struct gsc_context *ctx,
946 u32 buf_id, struct exynos_drm_ipp_buffer *buf)
947{
948
949 gsc_write(buf->dma_addr[0], GSC_OUT_BASE_ADDR_Y(buf_id));
950 gsc_write(buf->dma_addr[1], GSC_OUT_BASE_ADDR_CB(buf_id));
951 gsc_write(buf->dma_addr[2], GSC_OUT_BASE_ADDR_CR(buf_id));
952
953 gsc_dst_set_buf_seq(ctx, buf_id, true);
954}
955
956static int gsc_get_src_buf_index(struct gsc_context *ctx)
957{
958 u32 cfg, curr_index, i;
959 u32 buf_id = GSC_MAX_SRC;
960
961 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
962
963 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
964 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
965
966 for (i = curr_index; i < GSC_MAX_SRC; i++) {
967 if (!((cfg >> i) & 0x1)) {
968 buf_id = i;
969 break;
970 }
971 }
972
973 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
974 curr_index, buf_id);
975
976 if (buf_id == GSC_MAX_SRC) {
977 DRM_ERROR("failed to get in buffer index.\n");
978 return -EINVAL;
979 }
980
981 gsc_src_set_buf_seq(ctx, buf_id, false);
982
983 return buf_id;
984}
985
986static int gsc_get_dst_buf_index(struct gsc_context *ctx)
987{
988 u32 cfg, curr_index, i;
989 u32 buf_id = GSC_MAX_DST;
990
991 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
992
993 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
994 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
995
996 for (i = curr_index; i < GSC_MAX_DST; i++) {
997 if (!((cfg >> i) & 0x1)) {
998 buf_id = i;
999 break;
1000 }
1001 }
1002
1003 if (buf_id == GSC_MAX_DST) {
1004 DRM_ERROR("failed to get out buffer index.\n");
1005 return -EINVAL;
1006 }
1007
1008 gsc_dst_set_buf_seq(ctx, buf_id, false);
1009
1010 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1011 curr_index, buf_id);
1012
1013 return buf_id;
1014}
1015
1016static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1017{
1018 struct gsc_context *ctx = dev_id;
1019 u32 status;
1020 int err = 0;
1021
1022 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1023
1024 status = gsc_read(GSC_IRQ);
1025 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1026 dev_err(ctx->dev, "occurred overflow at %d, status 0x%x.\n",
1027 ctx->id, status);
1028 err = -EINVAL;
1029 }
1030
1031 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1032 int src_buf_id, dst_buf_id;
1033
1034 dev_dbg(ctx->dev, "occurred frame done at %d, status 0x%x.\n",
1035 ctx->id, status);
1036
1037 src_buf_id = gsc_get_src_buf_index(ctx);
1038 dst_buf_id = gsc_get_dst_buf_index(ctx);
1039
1040 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n", src_buf_id,
1041 dst_buf_id);
1042
1043 if (src_buf_id < 0 || dst_buf_id < 0)
1044 err = -EINVAL;
1045 }
1046
1047 if (ctx->task) {
1048 struct exynos_drm_ipp_task *task = ctx->task;
1049
1050 ctx->task = NULL;
1051 pm_runtime_mark_last_busy(ctx->dev);
1052 pm_runtime_put_autosuspend(ctx->dev);
1053 exynos_drm_ipp_task_done(task, err);
1054 }
1055
1056 return IRQ_HANDLED;
1057}
1058
1059static int gsc_reset(struct gsc_context *ctx)
1060{
1061 struct gsc_scaler *sc = &ctx->sc;
1062 int ret;
1063
1064
1065 ret = gsc_sw_reset(ctx);
1066 if (ret < 0) {
1067 dev_err(ctx->dev, "failed to reset hardware.\n");
1068 return ret;
1069 }
1070
1071
1072 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1073 sc->range = true;
1074
1075 return 0;
1076}
1077
1078static void gsc_start(struct gsc_context *ctx)
1079{
1080 u32 cfg;
1081
1082 gsc_handle_irq(ctx, true, false, true);
1083
1084
1085 cfg = gsc_read(GSC_ENABLE);
1086 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1087 GSC_ENABLE_CLK_GATE_MODE_MASK);
1088 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1089 gsc_write(cfg, GSC_ENABLE);
1090
1091
1092 cfg = gsc_read(GSC_IN_CON);
1093 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1094 cfg |= GSC_IN_PATH_MEMORY;
1095 gsc_write(cfg, GSC_IN_CON);
1096
1097
1098 cfg = gsc_read(GSC_OUT_CON);
1099 cfg |= GSC_OUT_PATH_MEMORY;
1100 gsc_write(cfg, GSC_OUT_CON);
1101
1102 gsc_set_scaler(ctx, &ctx->sc);
1103
1104 cfg = gsc_read(GSC_ENABLE);
1105 cfg |= GSC_ENABLE_ON;
1106 gsc_write(cfg, GSC_ENABLE);
1107}
1108
1109static int gsc_commit(struct exynos_drm_ipp *ipp,
1110 struct exynos_drm_ipp_task *task)
1111{
1112 struct gsc_context *ctx = container_of(ipp, struct gsc_context, ipp);
1113 int ret;
1114
1115 pm_runtime_get_sync(ctx->dev);
1116 ctx->task = task;
1117
1118 ret = gsc_reset(ctx);
1119 if (ret) {
1120 pm_runtime_put_autosuspend(ctx->dev);
1121 ctx->task = NULL;
1122 return ret;
1123 }
1124
1125 gsc_src_set_fmt(ctx, task->src.buf.fourcc);
1126 gsc_src_set_transf(ctx, task->transform.rotation);
1127 gsc_src_set_size(ctx, &task->src);
1128 gsc_src_set_addr(ctx, 0, &task->src);
1129 gsc_dst_set_fmt(ctx, task->dst.buf.fourcc);
1130 gsc_dst_set_size(ctx, &task->dst);
1131 gsc_dst_set_addr(ctx, 0, &task->dst);
1132 gsc_set_prescaler(ctx, &ctx->sc, &task->src.rect, &task->dst.rect);
1133 gsc_start(ctx);
1134
1135 return 0;
1136}
1137
1138static void gsc_abort(struct exynos_drm_ipp *ipp,
1139 struct exynos_drm_ipp_task *task)
1140{
1141 struct gsc_context *ctx =
1142 container_of(ipp, struct gsc_context, ipp);
1143
1144 gsc_reset(ctx);
1145 if (ctx->task) {
1146 struct exynos_drm_ipp_task *task = ctx->task;
1147
1148 ctx->task = NULL;
1149 pm_runtime_mark_last_busy(ctx->dev);
1150 pm_runtime_put_autosuspend(ctx->dev);
1151 exynos_drm_ipp_task_done(task, -EIO);
1152 }
1153}
1154
1155static struct exynos_drm_ipp_funcs ipp_funcs = {
1156 .commit = gsc_commit,
1157 .abort = gsc_abort,
1158};
1159
1160static int gsc_bind(struct device *dev, struct device *master, void *data)
1161{
1162 struct gsc_context *ctx = dev_get_drvdata(dev);
1163 struct drm_device *drm_dev = data;
1164 struct exynos_drm_ipp *ipp = &ctx->ipp;
1165
1166 ctx->drm_dev = drm_dev;
1167 drm_iommu_attach_device(drm_dev, dev);
1168
1169 exynos_drm_ipp_register(drm_dev, ipp, &ipp_funcs,
1170 DRM_EXYNOS_IPP_CAP_CROP | DRM_EXYNOS_IPP_CAP_ROTATE |
1171 DRM_EXYNOS_IPP_CAP_SCALE | DRM_EXYNOS_IPP_CAP_CONVERT,
1172 ctx->formats, ctx->num_formats, "gsc");
1173
1174 dev_info(dev, "The exynos gscaler has been probed successfully\n");
1175
1176 return 0;
1177}
1178
1179static void gsc_unbind(struct device *dev, struct device *master,
1180 void *data)
1181{
1182 struct gsc_context *ctx = dev_get_drvdata(dev);
1183 struct drm_device *drm_dev = data;
1184 struct exynos_drm_ipp *ipp = &ctx->ipp;
1185
1186 exynos_drm_ipp_unregister(drm_dev, ipp);
1187 drm_iommu_detach_device(drm_dev, dev);
1188}
1189
1190static const struct component_ops gsc_component_ops = {
1191 .bind = gsc_bind,
1192 .unbind = gsc_unbind,
1193};
1194
1195static const unsigned int gsc_formats[] = {
1196 DRM_FORMAT_ARGB8888,
1197 DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB565, DRM_FORMAT_BGRX8888,
1198 DRM_FORMAT_NV12, DRM_FORMAT_NV16, DRM_FORMAT_NV21, DRM_FORMAT_NV61,
1199 DRM_FORMAT_UYVY, DRM_FORMAT_VYUY, DRM_FORMAT_YUYV, DRM_FORMAT_YVYU,
1200 DRM_FORMAT_YUV420, DRM_FORMAT_YVU420, DRM_FORMAT_YUV422,
1201};
1202
1203static int gsc_probe(struct platform_device *pdev)
1204{
1205 struct device *dev = &pdev->dev;
1206 struct gsc_driverdata *driver_data;
1207 struct exynos_drm_ipp_formats *formats;
1208 struct gsc_context *ctx;
1209 struct resource *res;
1210 int ret, i;
1211
1212 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1213 if (!ctx)
1214 return -ENOMEM;
1215
1216 formats = devm_kcalloc(dev,
1217 ARRAY_SIZE(gsc_formats), sizeof(*formats),
1218 GFP_KERNEL);
1219 if (!formats)
1220 return -ENOMEM;
1221
1222 driver_data = (struct gsc_driverdata *)of_device_get_match_data(dev);
1223 ctx->dev = dev;
1224 ctx->num_clocks = driver_data->num_clocks;
1225 ctx->clk_names = driver_data->clk_names;
1226
1227 for (i = 0; i < ARRAY_SIZE(gsc_formats); i++) {
1228 formats[i].fourcc = gsc_formats[i];
1229 formats[i].type = DRM_EXYNOS_IPP_FORMAT_SOURCE |
1230 DRM_EXYNOS_IPP_FORMAT_DESTINATION;
1231 formats[i].limits = driver_data->limits;
1232 formats[i].num_limits = driver_data->num_limits;
1233 }
1234 ctx->formats = formats;
1235 ctx->num_formats = ARRAY_SIZE(gsc_formats);
1236
1237
1238 for (i = 0; i < ctx->num_clocks; i++) {
1239 ctx->clocks[i] = devm_clk_get(dev, ctx->clk_names[i]);
1240 if (IS_ERR(ctx->clocks[i])) {
1241 dev_err(dev, "failed to get clock: %s\n",
1242 ctx->clk_names[i]);
1243 return PTR_ERR(ctx->clocks[i]);
1244 }
1245 }
1246
1247
1248 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1249 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1250 if (IS_ERR(ctx->regs))
1251 return PTR_ERR(ctx->regs);
1252
1253
1254 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1255 if (!res) {
1256 dev_err(dev, "failed to request irq resource.\n");
1257 return -ENOENT;
1258 }
1259
1260 ctx->irq = res->start;
1261 ret = devm_request_irq(dev, ctx->irq, gsc_irq_handler, 0,
1262 dev_name(dev), ctx);
1263 if (ret < 0) {
1264 dev_err(dev, "failed to request irq.\n");
1265 return ret;
1266 }
1267
1268
1269 ctx->id = pdev->id;
1270
1271 platform_set_drvdata(pdev, ctx);
1272
1273 pm_runtime_use_autosuspend(dev);
1274 pm_runtime_set_autosuspend_delay(dev, GSC_AUTOSUSPEND_DELAY);
1275 pm_runtime_enable(dev);
1276
1277 ret = component_add(dev, &gsc_component_ops);
1278 if (ret)
1279 goto err_pm_dis;
1280
1281 dev_info(dev, "drm gsc registered successfully.\n");
1282
1283 return 0;
1284
1285err_pm_dis:
1286 pm_runtime_dont_use_autosuspend(dev);
1287 pm_runtime_disable(dev);
1288 return ret;
1289}
1290
1291static int gsc_remove(struct platform_device *pdev)
1292{
1293 struct device *dev = &pdev->dev;
1294
1295 pm_runtime_dont_use_autosuspend(dev);
1296 pm_runtime_disable(dev);
1297
1298 return 0;
1299}
1300
1301static int __maybe_unused gsc_runtime_suspend(struct device *dev)
1302{
1303 struct gsc_context *ctx = get_gsc_context(dev);
1304 int i;
1305
1306 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1307
1308 for (i = ctx->num_clocks - 1; i >= 0; i--)
1309 clk_disable_unprepare(ctx->clocks[i]);
1310
1311 return 0;
1312}
1313
1314static int __maybe_unused gsc_runtime_resume(struct device *dev)
1315{
1316 struct gsc_context *ctx = get_gsc_context(dev);
1317 int i, ret;
1318
1319 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1320
1321 for (i = 0; i < ctx->num_clocks; i++) {
1322 ret = clk_prepare_enable(ctx->clocks[i]);
1323 if (ret) {
1324 while (--i > 0)
1325 clk_disable_unprepare(ctx->clocks[i]);
1326 return ret;
1327 }
1328 }
1329 return 0;
1330}
1331
1332static const struct dev_pm_ops gsc_pm_ops = {
1333 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1334 pm_runtime_force_resume)
1335 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1336};
1337
1338static const struct drm_exynos_ipp_limit gsc_5250_limits[] = {
1339 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1340 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1341 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2048 }, .v = { 16, 2048 }) },
1342 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1343 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1344};
1345
1346static const struct drm_exynos_ipp_limit gsc_5420_limits[] = {
1347 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 4800, 8 }, .v = { 16, 3344, 8 }) },
1348 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 2 }, .v = { 8, 3344, 2 }) },
1349 { IPP_SIZE_LIMIT(ROTATED, .h = { 16, 2016 }, .v = { 8, 2016 }) },
1350 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1351 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1352};
1353
1354static const struct drm_exynos_ipp_limit gsc_5433_limits[] = {
1355 { IPP_SIZE_LIMIT(BUFFER, .h = { 32, 8191, 16 }, .v = { 16, 8191, 2 }) },
1356 { IPP_SIZE_LIMIT(AREA, .h = { 16, 4800, 1 }, .v = { 8, 3344, 1 }) },
1357 { IPP_SIZE_LIMIT(ROTATED, .h = { 32, 2047 }, .v = { 8, 8191 }) },
1358 { IPP_SCALE_LIMIT(.h = { (1 << 16) / 16, (1 << 16) * 8 },
1359 .v = { (1 << 16) / 16, (1 << 16) * 8 }) },
1360};
1361
1362static struct gsc_driverdata gsc_exynos5250_drvdata = {
1363 .clk_names = {"gscl"},
1364 .num_clocks = 1,
1365 .limits = gsc_5250_limits,
1366 .num_limits = ARRAY_SIZE(gsc_5250_limits),
1367};
1368
1369static struct gsc_driverdata gsc_exynos5420_drvdata = {
1370 .clk_names = {"gscl"},
1371 .num_clocks = 1,
1372 .limits = gsc_5420_limits,
1373 .num_limits = ARRAY_SIZE(gsc_5420_limits),
1374};
1375
1376static struct gsc_driverdata gsc_exynos5433_drvdata = {
1377 .clk_names = {"pclk", "aclk", "aclk_xiu", "aclk_gsclbend"},
1378 .num_clocks = 4,
1379 .limits = gsc_5433_limits,
1380 .num_limits = ARRAY_SIZE(gsc_5433_limits),
1381};
1382
1383static const struct of_device_id exynos_drm_gsc_of_match[] = {
1384 {
1385 .compatible = "samsung,exynos5-gsc",
1386 .data = &gsc_exynos5250_drvdata,
1387 }, {
1388 .compatible = "samsung,exynos5250-gsc",
1389 .data = &gsc_exynos5250_drvdata,
1390 }, {
1391 .compatible = "samsung,exynos5420-gsc",
1392 .data = &gsc_exynos5420_drvdata,
1393 }, {
1394 .compatible = "samsung,exynos5433-gsc",
1395 .data = &gsc_exynos5433_drvdata,
1396 }, {
1397 },
1398};
1399MODULE_DEVICE_TABLE(of, exynos_drm_gsc_of_match);
1400
1401struct platform_driver gsc_driver = {
1402 .probe = gsc_probe,
1403 .remove = gsc_remove,
1404 .driver = {
1405 .name = "exynos-drm-gsc",
1406 .owner = THIS_MODULE,
1407 .pm = &gsc_pm_ops,
1408 .of_match_table = of_match_ptr(exynos_drm_gsc_of_match),
1409 },
1410};
1411
