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36#ifndef _GVT_SCHEDULER_H_
37#define _GVT_SCHEDULER_H_
38
39struct intel_gvt_workload_scheduler {
40 struct intel_vgpu *current_vgpu;
41 struct intel_vgpu *next_vgpu;
42 struct intel_vgpu_workload *current_workload[I915_NUM_ENGINES];
43 bool need_reschedule;
44
45 spinlock_t mmio_context_lock;
46
47 struct intel_vgpu *engine_owner[I915_NUM_ENGINES];
48
49 wait_queue_head_t workload_complete_wq;
50 struct task_struct *thread[I915_NUM_ENGINES];
51 wait_queue_head_t waitq[I915_NUM_ENGINES];
52
53 void *sched_data;
54 struct intel_gvt_sched_policy_ops *sched_ops;
55};
56
57#define INDIRECT_CTX_ADDR_MASK 0xffffffc0
58#define INDIRECT_CTX_SIZE_MASK 0x3f
59struct shadow_indirect_ctx {
60 struct drm_i915_gem_object *obj;
61 unsigned long guest_gma;
62 unsigned long shadow_gma;
63 void *shadow_va;
64 uint32_t size;
65};
66
67#define PER_CTX_ADDR_MASK 0xfffff000
68struct shadow_per_ctx {
69 unsigned long guest_gma;
70 unsigned long shadow_gma;
71 unsigned valid;
72};
73
74struct intel_shadow_wa_ctx {
75 struct shadow_indirect_ctx indirect_ctx;
76 struct shadow_per_ctx per_ctx;
77
78};
79
80struct intel_vgpu_workload {
81 struct intel_vgpu *vgpu;
82 int ring_id;
83 struct i915_request *req;
84
85 bool dispatched;
86 bool shadowed;
87 int status;
88
89 struct intel_vgpu_mm *shadow_mm;
90
91
92 int (*prepare)(struct intel_vgpu_workload *);
93 int (*complete)(struct intel_vgpu_workload *);
94 struct list_head list;
95
96 DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
97 void *shadow_ring_buffer_va;
98
99
100 struct execlist_ctx_descriptor_format ctx_desc;
101 struct execlist_ring_context *ring_context;
102 unsigned long rb_head, rb_tail, rb_ctl, rb_start, rb_len;
103 bool restore_inhibit;
104 struct intel_vgpu_elsp_dwords elsp_dwords;
105 bool emulate_schedule_in;
106 atomic_t shadow_ctx_active;
107 wait_queue_head_t shadow_ctx_status_wq;
108 u64 ring_context_gpa;
109
110
111 struct list_head shadow_bb;
112 struct intel_shadow_wa_ctx wa_ctx;
113
114
115 u32 oactxctrl;
116 u32 flex_mmio[7];
117};
118
119struct intel_vgpu_shadow_bb {
120 struct list_head list;
121 struct drm_i915_gem_object *obj;
122 struct i915_vma *vma;
123 void *va;
124 u32 *bb_start_cmd_va;
125 unsigned int clflush;
126 bool accessing;
127 unsigned long bb_offset;
128 bool ppgtt;
129};
130
131#define workload_q_head(vgpu, ring_id) \
132 (&(vgpu->submission.workload_q_head[ring_id]))
133
134void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload);
135
136int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt);
137
138void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt);
139
140void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu);
141
142int intel_vgpu_setup_submission(struct intel_vgpu *vgpu);
143
144void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
145 unsigned long engine_mask);
146
147void intel_vgpu_clean_submission(struct intel_vgpu *vgpu);
148
149int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
150 unsigned long engine_mask,
151 unsigned int interface);
152
153extern const struct intel_vgpu_submission_ops
154intel_vgpu_execlist_submission_ops;
155
156struct intel_vgpu_workload *
157intel_vgpu_create_workload(struct intel_vgpu *vgpu, int ring_id,
158 struct execlist_ctx_descriptor_format *desc);
159
160void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload);
161
162#endif
163