1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#define DSS_SUBSYS_NAME "VENC"
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/mutex.h>
28#include <linux/completion.h>
29#include <linux/delay.h>
30#include <linux/string.h>
31#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
34#include <linux/pm_runtime.h>
35#include <linux/of.h>
36#include <linux/of_graph.h>
37#include <linux/component.h>
38#include <linux/sys_soc.h>
39
40#include "omapdss.h"
41#include "dss.h"
42
43
44#define VENC_REV_ID 0x00
45#define VENC_STATUS 0x04
46#define VENC_F_CONTROL 0x08
47#define VENC_VIDOUT_CTRL 0x10
48#define VENC_SYNC_CTRL 0x14
49#define VENC_LLEN 0x1C
50#define VENC_FLENS 0x20
51#define VENC_HFLTR_CTRL 0x24
52#define VENC_CC_CARR_WSS_CARR 0x28
53#define VENC_C_PHASE 0x2C
54#define VENC_GAIN_U 0x30
55#define VENC_GAIN_V 0x34
56#define VENC_GAIN_Y 0x38
57#define VENC_BLACK_LEVEL 0x3C
58#define VENC_BLANK_LEVEL 0x40
59#define VENC_X_COLOR 0x44
60#define VENC_M_CONTROL 0x48
61#define VENC_BSTAMP_WSS_DATA 0x4C
62#define VENC_S_CARR 0x50
63#define VENC_LINE21 0x54
64#define VENC_LN_SEL 0x58
65#define VENC_L21__WC_CTL 0x5C
66#define VENC_HTRIGGER_VTRIGGER 0x60
67#define VENC_SAVID__EAVID 0x64
68#define VENC_FLEN__FAL 0x68
69#define VENC_LAL__PHASE_RESET 0x6C
70#define VENC_HS_INT_START_STOP_X 0x70
71#define VENC_HS_EXT_START_STOP_X 0x74
72#define VENC_VS_INT_START_X 0x78
73#define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
74#define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
75#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
76#define VENC_VS_EXT_STOP_Y 0x88
77#define VENC_AVID_START_STOP_X 0x90
78#define VENC_AVID_START_STOP_Y 0x94
79#define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
80#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
81#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
82#define VENC_TVDETGP_INT_START_STOP_X 0xB0
83#define VENC_TVDETGP_INT_START_STOP_Y 0xB4
84#define VENC_GEN_CTRL 0xB8
85#define VENC_OUTPUT_CONTROL 0xC4
86#define VENC_OUTPUT_TEST 0xC8
87#define VENC_DAC_B__DAC_C 0xC8
88
89struct venc_config {
90 u32 f_control;
91 u32 vidout_ctrl;
92 u32 sync_ctrl;
93 u32 llen;
94 u32 flens;
95 u32 hfltr_ctrl;
96 u32 cc_carr_wss_carr;
97 u32 c_phase;
98 u32 gain_u;
99 u32 gain_v;
100 u32 gain_y;
101 u32 black_level;
102 u32 blank_level;
103 u32 x_color;
104 u32 m_control;
105 u32 bstamp_wss_data;
106 u32 s_carr;
107 u32 line21;
108 u32 ln_sel;
109 u32 l21__wc_ctl;
110 u32 htrigger_vtrigger;
111 u32 savid__eavid;
112 u32 flen__fal;
113 u32 lal__phase_reset;
114 u32 hs_int_start_stop_x;
115 u32 hs_ext_start_stop_x;
116 u32 vs_int_start_x;
117 u32 vs_int_stop_x__vs_int_start_y;
118 u32 vs_int_stop_y__vs_ext_start_x;
119 u32 vs_ext_stop_x__vs_ext_start_y;
120 u32 vs_ext_stop_y;
121 u32 avid_start_stop_x;
122 u32 avid_start_stop_y;
123 u32 fid_int_start_x__fid_int_start_y;
124 u32 fid_int_offset_y__fid_ext_start_x;
125 u32 fid_ext_start_y__fid_ext_offset_y;
126 u32 tvdetgp_int_start_stop_x;
127 u32 tvdetgp_int_start_stop_y;
128 u32 gen_ctrl;
129};
130
131
132static const struct venc_config venc_config_pal_trm = {
133 .f_control = 0,
134 .vidout_ctrl = 1,
135 .sync_ctrl = 0x40,
136 .llen = 0x35F,
137 .flens = 0x270,
138 .hfltr_ctrl = 0,
139 .cc_carr_wss_carr = 0x2F7225ED,
140 .c_phase = 0,
141 .gain_u = 0x111,
142 .gain_v = 0x181,
143 .gain_y = 0x140,
144 .black_level = 0x3B,
145 .blank_level = 0x3B,
146 .x_color = 0x7,
147 .m_control = 0x2,
148 .bstamp_wss_data = 0x3F,
149 .s_carr = 0x2A098ACB,
150 .line21 = 0,
151 .ln_sel = 0x01290015,
152 .l21__wc_ctl = 0x0000F603,
153 .htrigger_vtrigger = 0,
154
155 .savid__eavid = 0x06A70108,
156 .flen__fal = 0x00180270,
157 .lal__phase_reset = 0x00040135,
158 .hs_int_start_stop_x = 0x00880358,
159 .hs_ext_start_stop_x = 0x000F035F,
160 .vs_int_start_x = 0x01A70000,
161 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
162 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
163 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
164 .vs_ext_stop_y = 0x00000025,
165 .avid_start_stop_x = 0x03530083,
166 .avid_start_stop_y = 0x026C002E,
167 .fid_int_start_x__fid_int_start_y = 0x0001008A,
168 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
169 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
170
171 .tvdetgp_int_start_stop_x = 0x00140001,
172 .tvdetgp_int_start_stop_y = 0x00010001,
173 .gen_ctrl = 0x00FF0000,
174};
175
176
177static const struct venc_config venc_config_ntsc_trm = {
178 .f_control = 0,
179 .vidout_ctrl = 1,
180 .sync_ctrl = 0x8040,
181 .llen = 0x359,
182 .flens = 0x20C,
183 .hfltr_ctrl = 0,
184 .cc_carr_wss_carr = 0x043F2631,
185 .c_phase = 0,
186 .gain_u = 0x102,
187 .gain_v = 0x16C,
188 .gain_y = 0x12F,
189 .black_level = 0x43,
190 .blank_level = 0x38,
191 .x_color = 0x7,
192 .m_control = 0x1,
193 .bstamp_wss_data = 0x38,
194 .s_carr = 0x21F07C1F,
195 .line21 = 0,
196 .ln_sel = 0x01310011,
197 .l21__wc_ctl = 0x0000F003,
198 .htrigger_vtrigger = 0,
199
200 .savid__eavid = 0x069300F4,
201 .flen__fal = 0x0016020C,
202 .lal__phase_reset = 0x00060107,
203 .hs_int_start_stop_x = 0x008E0350,
204 .hs_ext_start_stop_x = 0x000F0359,
205 .vs_int_start_x = 0x01A00000,
206 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
207 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
208 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
209 .vs_ext_stop_y = 0x00000006,
210 .avid_start_stop_x = 0x03480078,
211 .avid_start_stop_y = 0x02060024,
212 .fid_int_start_x__fid_int_start_y = 0x0001008A,
213 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
214 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
215
216 .tvdetgp_int_start_stop_x = 0x00140001,
217 .tvdetgp_int_start_stop_y = 0x00010001,
218 .gen_ctrl = 0x00F90000,
219};
220
221static const struct venc_config venc_config_pal_bdghi = {
222 .f_control = 0,
223 .vidout_ctrl = 0,
224 .sync_ctrl = 0,
225 .hfltr_ctrl = 0,
226 .x_color = 0,
227 .line21 = 0,
228 .ln_sel = 21,
229 .htrigger_vtrigger = 0,
230 .tvdetgp_int_start_stop_x = 0x00140001,
231 .tvdetgp_int_start_stop_y = 0x00010001,
232 .gen_ctrl = 0x00FB0000,
233
234 .llen = 864-1,
235 .flens = 625-1,
236 .cc_carr_wss_carr = 0x2F7625ED,
237 .c_phase = 0xDF,
238 .gain_u = 0x111,
239 .gain_v = 0x181,
240 .gain_y = 0x140,
241 .black_level = 0x3e,
242 .blank_level = 0x3e,
243 .m_control = 0<<2 | 1<<1,
244 .bstamp_wss_data = 0x42,
245 .s_carr = 0x2a098acb,
246 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
247 .savid__eavid = 0x06A70108,
248 .flen__fal = 23<<16 | 624<<0,
249 .lal__phase_reset = 2<<17 | 310<<0,
250 .hs_int_start_stop_x = 0x00920358,
251 .hs_ext_start_stop_x = 0x000F035F,
252 .vs_int_start_x = 0x1a7<<16,
253 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
254 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
255 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
256 .vs_ext_stop_y = 0x05,
257 .avid_start_stop_x = 0x03530082,
258 .avid_start_stop_y = 0x0270002E,
259 .fid_int_start_x__fid_int_start_y = 0x0005008A,
260 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
261 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
262};
263
264enum venc_videomode {
265 VENC_MODE_UNKNOWN,
266 VENC_MODE_PAL,
267 VENC_MODE_NTSC,
268};
269
270static const struct videomode omap_dss_pal_vm = {
271 .hactive = 720,
272 .vactive = 574,
273 .pixelclock = 13500000,
274 .hsync_len = 64,
275 .hfront_porch = 12,
276 .hback_porch = 68,
277 .vsync_len = 5,
278 .vfront_porch = 5,
279 .vback_porch = 41,
280
281 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
282 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
283 DISPLAY_FLAGS_PIXDATA_POSEDGE |
284 DISPLAY_FLAGS_SYNC_NEGEDGE,
285};
286
287static const struct videomode omap_dss_ntsc_vm = {
288 .hactive = 720,
289 .vactive = 482,
290 .pixelclock = 13500000,
291 .hsync_len = 64,
292 .hfront_porch = 16,
293 .hback_porch = 58,
294 .vsync_len = 6,
295 .vfront_porch = 6,
296 .vback_porch = 31,
297
298 .flags = DISPLAY_FLAGS_INTERLACED | DISPLAY_FLAGS_HSYNC_LOW |
299 DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH |
300 DISPLAY_FLAGS_PIXDATA_POSEDGE |
301 DISPLAY_FLAGS_SYNC_NEGEDGE,
302};
303
304static enum venc_videomode venc_get_videomode(const struct videomode *vm)
305{
306 if (!(vm->flags & DISPLAY_FLAGS_INTERLACED))
307 return VENC_MODE_UNKNOWN;
308
309 if (vm->pixelclock == omap_dss_pal_vm.pixelclock &&
310 vm->hactive == omap_dss_pal_vm.hactive &&
311 vm->vactive == omap_dss_pal_vm.vactive)
312 return VENC_MODE_PAL;
313
314 if (vm->pixelclock == omap_dss_ntsc_vm.pixelclock &&
315 vm->hactive == omap_dss_ntsc_vm.hactive &&
316 vm->vactive == omap_dss_ntsc_vm.vactive)
317 return VENC_MODE_NTSC;
318
319 return VENC_MODE_UNKNOWN;
320}
321
322struct venc_device {
323 struct platform_device *pdev;
324 void __iomem *base;
325 struct mutex venc_lock;
326 u32 wss_data;
327 struct regulator *vdda_dac_reg;
328 struct dss_device *dss;
329
330 struct dss_debugfs_entry *debugfs;
331
332 struct clk *tv_dac_clk;
333
334 struct videomode vm;
335 enum omap_dss_venc_type type;
336 bool invert_polarity;
337 bool requires_tv_dac_clk;
338
339 struct omap_dss_device output;
340};
341
342#define dssdev_to_venc(dssdev) container_of(dssdev, struct venc_device, output)
343
344static inline void venc_write_reg(struct venc_device *venc, int idx, u32 val)
345{
346 __raw_writel(val, venc->base + idx);
347}
348
349static inline u32 venc_read_reg(struct venc_device *venc, int idx)
350{
351 u32 l = __raw_readl(venc->base + idx);
352 return l;
353}
354
355static void venc_write_config(struct venc_device *venc,
356 const struct venc_config *config)
357{
358 DSSDBG("write venc conf\n");
359
360 venc_write_reg(venc, VENC_LLEN, config->llen);
361 venc_write_reg(venc, VENC_FLENS, config->flens);
362 venc_write_reg(venc, VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
363 venc_write_reg(venc, VENC_C_PHASE, config->c_phase);
364 venc_write_reg(venc, VENC_GAIN_U, config->gain_u);
365 venc_write_reg(venc, VENC_GAIN_V, config->gain_v);
366 venc_write_reg(venc, VENC_GAIN_Y, config->gain_y);
367 venc_write_reg(venc, VENC_BLACK_LEVEL, config->black_level);
368 venc_write_reg(venc, VENC_BLANK_LEVEL, config->blank_level);
369 venc_write_reg(venc, VENC_M_CONTROL, config->m_control);
370 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
371 venc->wss_data);
372 venc_write_reg(venc, VENC_S_CARR, config->s_carr);
373 venc_write_reg(venc, VENC_L21__WC_CTL, config->l21__wc_ctl);
374 venc_write_reg(venc, VENC_SAVID__EAVID, config->savid__eavid);
375 venc_write_reg(venc, VENC_FLEN__FAL, config->flen__fal);
376 venc_write_reg(venc, VENC_LAL__PHASE_RESET, config->lal__phase_reset);
377 venc_write_reg(venc, VENC_HS_INT_START_STOP_X,
378 config->hs_int_start_stop_x);
379 venc_write_reg(venc, VENC_HS_EXT_START_STOP_X,
380 config->hs_ext_start_stop_x);
381 venc_write_reg(venc, VENC_VS_INT_START_X, config->vs_int_start_x);
382 venc_write_reg(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y,
383 config->vs_int_stop_x__vs_int_start_y);
384 venc_write_reg(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X,
385 config->vs_int_stop_y__vs_ext_start_x);
386 venc_write_reg(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
387 config->vs_ext_stop_x__vs_ext_start_y);
388 venc_write_reg(venc, VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
389 venc_write_reg(venc, VENC_AVID_START_STOP_X, config->avid_start_stop_x);
390 venc_write_reg(venc, VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
391 venc_write_reg(venc, VENC_FID_INT_START_X__FID_INT_START_Y,
392 config->fid_int_start_x__fid_int_start_y);
393 venc_write_reg(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
394 config->fid_int_offset_y__fid_ext_start_x);
395 venc_write_reg(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
396 config->fid_ext_start_y__fid_ext_offset_y);
397
398 venc_write_reg(venc, VENC_DAC_B__DAC_C,
399 venc_read_reg(venc, VENC_DAC_B__DAC_C));
400 venc_write_reg(venc, VENC_VIDOUT_CTRL, config->vidout_ctrl);
401 venc_write_reg(venc, VENC_HFLTR_CTRL, config->hfltr_ctrl);
402 venc_write_reg(venc, VENC_X_COLOR, config->x_color);
403 venc_write_reg(venc, VENC_LINE21, config->line21);
404 venc_write_reg(venc, VENC_LN_SEL, config->ln_sel);
405 venc_write_reg(venc, VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
406 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_X,
407 config->tvdetgp_int_start_stop_x);
408 venc_write_reg(venc, VENC_TVDETGP_INT_START_STOP_Y,
409 config->tvdetgp_int_start_stop_y);
410 venc_write_reg(venc, VENC_GEN_CTRL, config->gen_ctrl);
411 venc_write_reg(venc, VENC_F_CONTROL, config->f_control);
412 venc_write_reg(venc, VENC_SYNC_CTRL, config->sync_ctrl);
413}
414
415static void venc_reset(struct venc_device *venc)
416{
417 int t = 1000;
418
419 venc_write_reg(venc, VENC_F_CONTROL, 1<<8);
420 while (venc_read_reg(venc, VENC_F_CONTROL) & (1<<8)) {
421 if (--t == 0) {
422 DSSERR("Failed to reset venc\n");
423 return;
424 }
425 }
426
427#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
428
429
430 msleep(20);
431#endif
432}
433
434static int venc_runtime_get(struct venc_device *venc)
435{
436 int r;
437
438 DSSDBG("venc_runtime_get\n");
439
440 r = pm_runtime_get_sync(&venc->pdev->dev);
441 WARN_ON(r < 0);
442 return r < 0 ? r : 0;
443}
444
445static void venc_runtime_put(struct venc_device *venc)
446{
447 int r;
448
449 DSSDBG("venc_runtime_put\n");
450
451 r = pm_runtime_put_sync(&venc->pdev->dev);
452 WARN_ON(r < 0 && r != -ENOSYS);
453}
454
455static const struct venc_config *venc_timings_to_config(struct videomode *vm)
456{
457 switch (venc_get_videomode(vm)) {
458 default:
459 WARN_ON_ONCE(1);
460 case VENC_MODE_PAL:
461 return &venc_config_pal_trm;
462 case VENC_MODE_NTSC:
463 return &venc_config_ntsc_trm;
464 }
465}
466
467static int venc_power_on(struct venc_device *venc)
468{
469 u32 l;
470 int r;
471
472 r = venc_runtime_get(venc);
473 if (r)
474 goto err0;
475
476 venc_reset(venc);
477 venc_write_config(venc, venc_timings_to_config(&venc->vm));
478
479 dss_set_venc_output(venc->dss, venc->type);
480 dss_set_dac_pwrdn_bgz(venc->dss, 1);
481
482 l = 0;
483
484 if (venc->type == OMAP_DSS_VENC_TYPE_COMPOSITE)
485 l |= 1 << 1;
486 else
487 l |= (1 << 0) | (1 << 2);
488
489 if (venc->invert_polarity == false)
490 l |= 1 << 3;
491
492 venc_write_reg(venc, VENC_OUTPUT_CONTROL, l);
493
494 dss_mgr_set_timings(&venc->output, &venc->vm);
495
496 r = regulator_enable(venc->vdda_dac_reg);
497 if (r)
498 goto err1;
499
500 r = dss_mgr_enable(&venc->output);
501 if (r)
502 goto err2;
503
504 return 0;
505
506err2:
507 regulator_disable(venc->vdda_dac_reg);
508err1:
509 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
510 dss_set_dac_pwrdn_bgz(venc->dss, 0);
511
512 venc_runtime_put(venc);
513err0:
514 return r;
515}
516
517static void venc_power_off(struct venc_device *venc)
518{
519 venc_write_reg(venc, VENC_OUTPUT_CONTROL, 0);
520 dss_set_dac_pwrdn_bgz(venc->dss, 0);
521
522 dss_mgr_disable(&venc->output);
523
524 regulator_disable(venc->vdda_dac_reg);
525
526 venc_runtime_put(venc);
527}
528
529static int venc_display_enable(struct omap_dss_device *dssdev)
530{
531 struct venc_device *venc = dssdev_to_venc(dssdev);
532 int r;
533
534 DSSDBG("venc_display_enable\n");
535
536 mutex_lock(&venc->venc_lock);
537
538 if (!dssdev->dispc_channel_connected) {
539 DSSERR("Failed to enable display: no output/manager\n");
540 r = -ENODEV;
541 goto err0;
542 }
543
544 r = venc_power_on(venc);
545 if (r)
546 goto err0;
547
548 venc->wss_data = 0;
549
550 mutex_unlock(&venc->venc_lock);
551
552 return 0;
553err0:
554 mutex_unlock(&venc->venc_lock);
555 return r;
556}
557
558static void venc_display_disable(struct omap_dss_device *dssdev)
559{
560 struct venc_device *venc = dssdev_to_venc(dssdev);
561
562 DSSDBG("venc_display_disable\n");
563
564 mutex_lock(&venc->venc_lock);
565
566 venc_power_off(venc);
567
568 mutex_unlock(&venc->venc_lock);
569}
570
571static void venc_set_timings(struct omap_dss_device *dssdev,
572 struct videomode *vm)
573{
574 struct venc_device *venc = dssdev_to_venc(dssdev);
575 struct videomode actual_vm;
576
577 DSSDBG("venc_set_timings\n");
578
579 mutex_lock(&venc->venc_lock);
580
581 switch (venc_get_videomode(vm)) {
582 default:
583 WARN_ON_ONCE(1);
584 case VENC_MODE_PAL:
585 actual_vm = omap_dss_pal_vm;
586 break;
587 case VENC_MODE_NTSC:
588 actual_vm = omap_dss_ntsc_vm;
589 break;
590 }
591
592
593 if (memcmp(&venc->vm, &actual_vm, sizeof(actual_vm)))
594 venc->wss_data = 0;
595
596 venc->vm = actual_vm;
597
598 dispc_set_tv_pclk(venc->dss->dispc, 13500000);
599
600 mutex_unlock(&venc->venc_lock);
601}
602
603static int venc_check_timings(struct omap_dss_device *dssdev,
604 struct videomode *vm)
605{
606 DSSDBG("venc_check_timings\n");
607
608 switch (venc_get_videomode(vm)) {
609 case VENC_MODE_PAL:
610 case VENC_MODE_NTSC:
611 return 0;
612 default:
613 return -EINVAL;
614 }
615}
616
617static void venc_get_timings(struct omap_dss_device *dssdev,
618 struct videomode *vm)
619{
620 struct venc_device *venc = dssdev_to_venc(dssdev);
621
622 mutex_lock(&venc->venc_lock);
623
624 *vm = venc->vm;
625
626 mutex_unlock(&venc->venc_lock);
627}
628
629static u32 venc_get_wss(struct omap_dss_device *dssdev)
630{
631 struct venc_device *venc = dssdev_to_venc(dssdev);
632
633
634 return (venc->wss_data >> 8) ^ 0xfffff;
635}
636
637static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
638{
639 struct venc_device *venc = dssdev_to_venc(dssdev);
640 const struct venc_config *config;
641 int r;
642
643 DSSDBG("venc_set_wss\n");
644
645 mutex_lock(&venc->venc_lock);
646
647 config = venc_timings_to_config(&venc->vm);
648
649
650 venc->wss_data = (wss ^ 0xfffff) << 8;
651
652 r = venc_runtime_get(venc);
653 if (r)
654 goto err;
655
656 venc_write_reg(venc, VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
657 venc->wss_data);
658
659 venc_runtime_put(venc);
660
661err:
662 mutex_unlock(&venc->venc_lock);
663
664 return r;
665}
666
667static int venc_init_regulator(struct venc_device *venc)
668{
669 struct regulator *vdda_dac;
670
671 if (venc->vdda_dac_reg != NULL)
672 return 0;
673
674 vdda_dac = devm_regulator_get(&venc->pdev->dev, "vdda");
675 if (IS_ERR(vdda_dac)) {
676 if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
677 DSSERR("can't get VDDA_DAC regulator\n");
678 return PTR_ERR(vdda_dac);
679 }
680
681 venc->vdda_dac_reg = vdda_dac;
682
683 return 0;
684}
685
686static int venc_dump_regs(struct seq_file *s, void *p)
687{
688 struct venc_device *venc = s->private;
689
690#define DUMPREG(venc, r) \
691 seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(venc, r))
692
693 if (venc_runtime_get(venc))
694 return 0;
695
696 DUMPREG(venc, VENC_F_CONTROL);
697 DUMPREG(venc, VENC_VIDOUT_CTRL);
698 DUMPREG(venc, VENC_SYNC_CTRL);
699 DUMPREG(venc, VENC_LLEN);
700 DUMPREG(venc, VENC_FLENS);
701 DUMPREG(venc, VENC_HFLTR_CTRL);
702 DUMPREG(venc, VENC_CC_CARR_WSS_CARR);
703 DUMPREG(venc, VENC_C_PHASE);
704 DUMPREG(venc, VENC_GAIN_U);
705 DUMPREG(venc, VENC_GAIN_V);
706 DUMPREG(venc, VENC_GAIN_Y);
707 DUMPREG(venc, VENC_BLACK_LEVEL);
708 DUMPREG(venc, VENC_BLANK_LEVEL);
709 DUMPREG(venc, VENC_X_COLOR);
710 DUMPREG(venc, VENC_M_CONTROL);
711 DUMPREG(venc, VENC_BSTAMP_WSS_DATA);
712 DUMPREG(venc, VENC_S_CARR);
713 DUMPREG(venc, VENC_LINE21);
714 DUMPREG(venc, VENC_LN_SEL);
715 DUMPREG(venc, VENC_L21__WC_CTL);
716 DUMPREG(venc, VENC_HTRIGGER_VTRIGGER);
717 DUMPREG(venc, VENC_SAVID__EAVID);
718 DUMPREG(venc, VENC_FLEN__FAL);
719 DUMPREG(venc, VENC_LAL__PHASE_RESET);
720 DUMPREG(venc, VENC_HS_INT_START_STOP_X);
721 DUMPREG(venc, VENC_HS_EXT_START_STOP_X);
722 DUMPREG(venc, VENC_VS_INT_START_X);
723 DUMPREG(venc, VENC_VS_INT_STOP_X__VS_INT_START_Y);
724 DUMPREG(venc, VENC_VS_INT_STOP_Y__VS_EXT_START_X);
725 DUMPREG(venc, VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
726 DUMPREG(venc, VENC_VS_EXT_STOP_Y);
727 DUMPREG(venc, VENC_AVID_START_STOP_X);
728 DUMPREG(venc, VENC_AVID_START_STOP_Y);
729 DUMPREG(venc, VENC_FID_INT_START_X__FID_INT_START_Y);
730 DUMPREG(venc, VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
731 DUMPREG(venc, VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
732 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_X);
733 DUMPREG(venc, VENC_TVDETGP_INT_START_STOP_Y);
734 DUMPREG(venc, VENC_GEN_CTRL);
735 DUMPREG(venc, VENC_OUTPUT_CONTROL);
736 DUMPREG(venc, VENC_OUTPUT_TEST);
737
738 venc_runtime_put(venc);
739
740#undef DUMPREG
741 return 0;
742}
743
744static int venc_get_clocks(struct venc_device *venc)
745{
746 struct clk *clk;
747
748 if (venc->requires_tv_dac_clk) {
749 clk = devm_clk_get(&venc->pdev->dev, "tv_dac_clk");
750 if (IS_ERR(clk)) {
751 DSSERR("can't get tv_dac_clk\n");
752 return PTR_ERR(clk);
753 }
754 } else {
755 clk = NULL;
756 }
757
758 venc->tv_dac_clk = clk;
759
760 return 0;
761}
762
763static int venc_connect(struct omap_dss_device *dssdev,
764 struct omap_dss_device *dst)
765{
766 struct venc_device *venc = dssdev_to_venc(dssdev);
767 int r;
768
769 r = venc_init_regulator(venc);
770 if (r)
771 return r;
772
773 r = dss_mgr_connect(&venc->output, dssdev);
774 if (r)
775 return r;
776
777 r = omapdss_output_set_device(dssdev, dst);
778 if (r) {
779 DSSERR("failed to connect output to new device: %s\n",
780 dst->name);
781 dss_mgr_disconnect(&venc->output, dssdev);
782 return r;
783 }
784
785 return 0;
786}
787
788static void venc_disconnect(struct omap_dss_device *dssdev,
789 struct omap_dss_device *dst)
790{
791 struct venc_device *venc = dssdev_to_venc(dssdev);
792
793 WARN_ON(dst != dssdev->dst);
794
795 if (dst != dssdev->dst)
796 return;
797
798 omapdss_output_unset_device(dssdev);
799
800 dss_mgr_disconnect(&venc->output, dssdev);
801}
802
803static const struct omapdss_atv_ops venc_ops = {
804 .connect = venc_connect,
805 .disconnect = venc_disconnect,
806
807 .enable = venc_display_enable,
808 .disable = venc_display_disable,
809
810 .check_timings = venc_check_timings,
811 .set_timings = venc_set_timings,
812 .get_timings = venc_get_timings,
813
814 .set_wss = venc_set_wss,
815 .get_wss = venc_get_wss,
816};
817
818static void venc_init_output(struct venc_device *venc)
819{
820 struct omap_dss_device *out = &venc->output;
821
822 out->dev = &venc->pdev->dev;
823 out->id = OMAP_DSS_OUTPUT_VENC;
824 out->output_type = OMAP_DISPLAY_TYPE_VENC;
825 out->name = "venc.0";
826 out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
827 out->ops.atv = &venc_ops;
828 out->owner = THIS_MODULE;
829
830 omapdss_register_output(out);
831}
832
833static void venc_uninit_output(struct venc_device *venc)
834{
835 omapdss_unregister_output(&venc->output);
836}
837
838static int venc_probe_of(struct venc_device *venc)
839{
840 struct device_node *node = venc->pdev->dev.of_node;
841 struct device_node *ep;
842 u32 channels;
843 int r;
844
845 ep = of_graph_get_endpoint_by_regs(node, 0, 0);
846 if (!ep)
847 return 0;
848
849 venc->invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
850
851 r = of_property_read_u32(ep, "ti,channels", &channels);
852 if (r) {
853 dev_err(&venc->pdev->dev,
854 "failed to read property 'ti,channels': %d\n", r);
855 goto err;
856 }
857
858 switch (channels) {
859 case 1:
860 venc->type = OMAP_DSS_VENC_TYPE_COMPOSITE;
861 break;
862 case 2:
863 venc->type = OMAP_DSS_VENC_TYPE_SVIDEO;
864 break;
865 default:
866 dev_err(&venc->pdev->dev, "bad channel propert '%d'\n",
867 channels);
868 r = -EINVAL;
869 goto err;
870 }
871
872 of_node_put(ep);
873
874 return 0;
875
876err:
877 of_node_put(ep);
878 return r;
879}
880
881
882static const struct soc_device_attribute venc_soc_devices[] = {
883 { .machine = "OMAP3[45]*" },
884 { .machine = "AM35*" },
885 { }
886};
887
888static int venc_bind(struct device *dev, struct device *master, void *data)
889{
890 struct platform_device *pdev = to_platform_device(dev);
891 struct dss_device *dss = dss_get_device(master);
892 struct venc_device *venc;
893 u8 rev_id;
894 struct resource *venc_mem;
895 int r;
896
897 venc = kzalloc(sizeof(*venc), GFP_KERNEL);
898 if (!venc)
899 return -ENOMEM;
900
901 venc->pdev = pdev;
902 venc->dss = dss;
903 dev_set_drvdata(dev, venc);
904
905
906 if (soc_device_match(venc_soc_devices))
907 venc->requires_tv_dac_clk = true;
908
909 mutex_init(&venc->venc_lock);
910
911 venc->wss_data = 0;
912
913 venc_mem = platform_get_resource(venc->pdev, IORESOURCE_MEM, 0);
914 venc->base = devm_ioremap_resource(&pdev->dev, venc_mem);
915 if (IS_ERR(venc->base)) {
916 r = PTR_ERR(venc->base);
917 goto err_free;
918 }
919
920 r = venc_get_clocks(venc);
921 if (r)
922 goto err_free;
923
924 pm_runtime_enable(&pdev->dev);
925
926 r = venc_runtime_get(venc);
927 if (r)
928 goto err_runtime_get;
929
930 rev_id = (u8)(venc_read_reg(venc, VENC_REV_ID) & 0xff);
931 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
932
933 venc_runtime_put(venc);
934
935 r = venc_probe_of(venc);
936 if (r) {
937 DSSERR("Invalid DT data\n");
938 goto err_probe_of;
939 }
940
941 venc->debugfs = dss_debugfs_create_file(dss, "venc", venc_dump_regs,
942 venc);
943
944 venc_init_output(venc);
945
946 return 0;
947
948err_probe_of:
949err_runtime_get:
950 pm_runtime_disable(&pdev->dev);
951err_free:
952 kfree(venc);
953 return r;
954}
955
956static void venc_unbind(struct device *dev, struct device *master, void *data)
957{
958 struct venc_device *venc = dev_get_drvdata(dev);
959
960 dss_debugfs_remove_file(venc->debugfs);
961
962 venc_uninit_output(venc);
963
964 pm_runtime_disable(dev);
965
966 kfree(venc);
967}
968
969static const struct component_ops venc_component_ops = {
970 .bind = venc_bind,
971 .unbind = venc_unbind,
972};
973
974static int venc_probe(struct platform_device *pdev)
975{
976 return component_add(&pdev->dev, &venc_component_ops);
977}
978
979static int venc_remove(struct platform_device *pdev)
980{
981 component_del(&pdev->dev, &venc_component_ops);
982 return 0;
983}
984
985static int venc_runtime_suspend(struct device *dev)
986{
987 struct venc_device *venc = dev_get_drvdata(dev);
988
989 if (venc->tv_dac_clk)
990 clk_disable_unprepare(venc->tv_dac_clk);
991
992 dispc_runtime_put(venc->dss->dispc);
993
994 return 0;
995}
996
997static int venc_runtime_resume(struct device *dev)
998{
999 struct venc_device *venc = dev_get_drvdata(dev);
1000 int r;
1001
1002 r = dispc_runtime_get(venc->dss->dispc);
1003 if (r < 0)
1004 return r;
1005
1006 if (venc->tv_dac_clk)
1007 clk_prepare_enable(venc->tv_dac_clk);
1008
1009 return 0;
1010}
1011
1012static const struct dev_pm_ops venc_pm_ops = {
1013 .runtime_suspend = venc_runtime_suspend,
1014 .runtime_resume = venc_runtime_resume,
1015};
1016
1017static const struct of_device_id venc_of_match[] = {
1018 { .compatible = "ti,omap2-venc", },
1019 { .compatible = "ti,omap3-venc", },
1020 { .compatible = "ti,omap4-venc", },
1021 {},
1022};
1023
1024struct platform_driver omap_venchw_driver = {
1025 .probe = venc_probe,
1026 .remove = venc_remove,
1027 .driver = {
1028 .name = "omapdss_venc",
1029 .pm = &venc_pm_ops,
1030 .of_match_table = venc_of_match,
1031 .suppress_bind_attrs = true,
1032 },
1033};
1034
