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9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/input.h>
15#include <linux/interrupt.h>
16#include <linux/jiffies.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22#include <linux/sched.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25
26#include <linux/platform_data/at91_adc.h>
27
28#include <linux/iio/iio.h>
29#include <linux/iio/buffer.h>
30#include <linux/iio/trigger.h>
31#include <linux/iio/trigger_consumer.h>
32#include <linux/iio/triggered_buffer.h>
33#include <linux/pinctrl/consumer.h>
34
35
36#define AT91_ADC_CR 0x00
37#define AT91_ADC_SWRST (1 << 0)
38#define AT91_ADC_START (1 << 1)
39
40#define AT91_ADC_MR 0x04
41#define AT91_ADC_TSAMOD (3 << 0)
42#define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0)
43#define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0)
44#define AT91_ADC_TRGEN (1 << 0)
45#define AT91_ADC_TRGSEL (7 << 1)
46#define AT91_ADC_TRGSEL_TC0 (0 << 1)
47#define AT91_ADC_TRGSEL_TC1 (1 << 1)
48#define AT91_ADC_TRGSEL_TC2 (2 << 1)
49#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
50#define AT91_ADC_LOWRES (1 << 4)
51#define AT91_ADC_SLEEP (1 << 5)
52#define AT91_ADC_PENDET (1 << 6)
53#define AT91_ADC_PRESCAL_9260 (0x3f << 8)
54#define AT91_ADC_PRESCAL_9G45 (0xff << 8)
55#define AT91_ADC_PRESCAL_(x) ((x) << 8)
56#define AT91_ADC_STARTUP_9260 (0x1f << 16)
57#define AT91_ADC_STARTUP_9G45 (0x7f << 16)
58#define AT91_ADC_STARTUP_9X5 (0xf << 16)
59#define AT91_ADC_STARTUP_(x) ((x) << 16)
60#define AT91_ADC_SHTIM (0xf << 24)
61#define AT91_ADC_SHTIM_(x) ((x) << 24)
62#define AT91_ADC_PENDBC (0x0f << 28)
63#define AT91_ADC_PENDBC_(x) ((x) << 28)
64
65#define AT91_ADC_TSR 0x0C
66#define AT91_ADC_TSR_SHTIM (0xf << 24)
67#define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68
69#define AT91_ADC_CHER 0x10
70#define AT91_ADC_CHDR 0x14
71#define AT91_ADC_CHSR 0x18
72#define AT91_ADC_CH(n) (1 << (n))
73
74#define AT91_ADC_SR 0x1C
75#define AT91_ADC_EOC(n) (1 << (n))
76#define AT91_ADC_OVRE(n) (1 << ((n) + 8))
77#define AT91_ADC_DRDY (1 << 16)
78#define AT91_ADC_GOVRE (1 << 17)
79#define AT91_ADC_ENDRX (1 << 18)
80#define AT91_ADC_RXFUFF (1 << 19)
81
82#define AT91_ADC_SR_9X5 0x30
83#define AT91_ADC_SR_DRDY_9X5 (1 << 24)
84
85#define AT91_ADC_LCDR 0x20
86#define AT91_ADC_LDATA (0x3ff)
87
88#define AT91_ADC_IER 0x24
89#define AT91_ADC_IDR 0x28
90#define AT91_ADC_IMR 0x2C
91#define AT91RL_ADC_IER_PEN (1 << 20)
92#define AT91RL_ADC_IER_NOPEN (1 << 21)
93#define AT91_ADC_IER_PEN (1 << 29)
94#define AT91_ADC_IER_NOPEN (1 << 30)
95#define AT91_ADC_IER_XRDY (1 << 20)
96#define AT91_ADC_IER_YRDY (1 << 21)
97#define AT91_ADC_IER_PRDY (1 << 22)
98#define AT91_ADC_ISR_PENS (1 << 31)
99
100#define AT91_ADC_CHR(n) (0x30 + ((n) * 4))
101#define AT91_ADC_DATA (0x3ff)
102
103#define AT91_ADC_CDR0_9X5 (0x50)
104
105#define AT91_ADC_ACR 0x94
106#define AT91_ADC_ACR_PENDETSENS (0x3 << 0)
107
108#define AT91_ADC_TSMR 0xB0
109#define AT91_ADC_TSMR_TSMODE (3 << 0)
110#define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
111#define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
112#define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
113#define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
114#define AT91_ADC_TSMR_TSAV (3 << 4)
115#define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
116#define AT91_ADC_TSMR_SCTIM (0x0f << 16)
117#define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
118#define AT91_ADC_TSMR_PENDBC (0x0f << 28)
119#define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
120#define AT91_ADC_TSMR_NOTSDMA (1 << 22)
121#define AT91_ADC_TSMR_PENDET_DIS (0 << 24)
122#define AT91_ADC_TSMR_PENDET_ENA (1 << 24)
123
124#define AT91_ADC_TSXPOSR 0xB4
125#define AT91_ADC_TSYPOSR 0xB8
126#define AT91_ADC_TSPRESSR 0xBC
127
128#define AT91_ADC_TRGR_9260 AT91_ADC_MR
129#define AT91_ADC_TRGR_9G45 0x08
130#define AT91_ADC_TRGR_9X5 0xC0
131
132
133#define AT91_ADC_TRGR_TRGPER (0xffff << 16)
134#define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
135#define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
136#define AT91_ADC_TRGR_NONE (0 << 0)
137#define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
138
139#define AT91_ADC_CHAN(st, ch) \
140 (st->registers->channel_base + (ch * 4))
141#define at91_adc_readl(st, reg) \
142 (readl_relaxed(st->reg_base + reg))
143#define at91_adc_writel(st, reg, val) \
144 (writel_relaxed(val, st->reg_base + reg))
145
146#define DRIVER_NAME "at91_adc"
147#define MAX_POS_BITS 12
148
149#define TOUCH_SAMPLE_PERIOD_US 2000
150#define TOUCH_PEN_DETECT_DEBOUNCE_US 200
151
152#define MAX_RLPOS_BITS 10
153#define TOUCH_SAMPLE_PERIOD_US_RL 10000
154#define TOUCH_SHTIM 0xa
155#define TOUCH_SCTIM_US 10
156
157
158
159
160
161
162
163
164
165
166
167struct at91_adc_reg_desc {
168 u8 channel_base;
169 u32 drdy_mask;
170 u8 status_register;
171 u8 trigger_register;
172 u32 mr_prescal_mask;
173 u32 mr_startup_mask;
174};
175
176struct at91_adc_caps {
177 bool has_ts;
178 bool has_tsmr;
179
180
181
182
183 u8 ts_filter_average;
184
185 u8 ts_pen_detect_sensitivity;
186
187
188 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
189
190 u8 num_channels;
191 struct at91_adc_reg_desc registers;
192};
193
194struct at91_adc_state {
195 struct clk *adc_clk;
196 u16 *buffer;
197 unsigned long channels_mask;
198 struct clk *clk;
199 bool done;
200 int irq;
201 u16 last_value;
202 int chnb;
203 struct mutex lock;
204 u8 num_channels;
205 void __iomem *reg_base;
206 struct at91_adc_reg_desc *registers;
207 u32 startup_time;
208 u8 sample_hold_time;
209 bool sleep_mode;
210 struct iio_trigger **trig;
211 struct at91_adc_trigger *trigger_list;
212 u32 trigger_number;
213 bool use_external;
214 u32 vref_mv;
215 u32 res;
216 bool low_res;
217 wait_queue_head_t wq_data_avail;
218 struct at91_adc_caps *caps;
219
220
221
222
223
224
225
226
227
228
229
230
231
232#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
233#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
234 enum atmel_adc_ts_type touchscreen_type;
235 struct input_dev *ts_input;
236
237 u16 ts_sample_period_val;
238 u32 ts_pressure_threshold;
239 u16 ts_pendbc;
240
241 bool ts_bufferedmeasure;
242 u32 ts_prev_absx;
243 u32 ts_prev_absy;
244};
245
246static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
247{
248 struct iio_poll_func *pf = p;
249 struct iio_dev *idev = pf->indio_dev;
250 struct at91_adc_state *st = iio_priv(idev);
251 int i, j = 0;
252
253 for (i = 0; i < idev->masklength; i++) {
254 if (!test_bit(i, idev->active_scan_mask))
255 continue;
256 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
257 j++;
258 }
259
260 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
261
262 iio_trigger_notify_done(idev->trig);
263
264
265 at91_adc_readl(st, AT91_ADC_LCDR);
266
267 enable_irq(st->irq);
268
269 return IRQ_HANDLED;
270}
271
272
273static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
274{
275 struct at91_adc_state *st = iio_priv(idev);
276
277 if (iio_buffer_enabled(idev)) {
278 disable_irq_nosync(irq);
279 iio_trigger_poll(idev->trig);
280 } else {
281 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
282 st->done = true;
283 wake_up_interruptible(&st->wq_data_avail);
284 }
285}
286
287static int at91_ts_sample(struct at91_adc_state *st)
288{
289 unsigned int xscale, yscale, reg, z1, z2;
290 unsigned int x, y, pres, xpos, ypos;
291 unsigned int rxp = 1;
292 unsigned int factor = 1000;
293 struct iio_dev *idev = iio_priv_to_dev(st);
294
295 unsigned int xyz_mask_bits = st->res;
296 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
297
298
299
300 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
301 xpos = reg & xyz_mask;
302 x = (xpos << MAX_POS_BITS) - xpos;
303 xscale = (reg >> 16) & xyz_mask;
304 if (xscale == 0) {
305 dev_err(&idev->dev, "Error: xscale == 0!\n");
306 return -1;
307 }
308 x /= xscale;
309
310
311 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
312 ypos = reg & xyz_mask;
313 y = (ypos << MAX_POS_BITS) - ypos;
314 yscale = (reg >> 16) & xyz_mask;
315 if (yscale == 0) {
316 dev_err(&idev->dev, "Error: yscale == 0!\n");
317 return -1;
318 }
319 y /= yscale;
320
321
322 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
323 z1 = reg & xyz_mask;
324 z2 = (reg >> 16) & xyz_mask;
325
326 if (z1 != 0)
327 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
328 / factor;
329 else
330 pres = st->ts_pressure_threshold;
331
332 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
333 xpos, xscale, ypos, yscale, z1, z2, pres);
334
335 if (pres < st->ts_pressure_threshold) {
336 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
337 x, y, pres / factor);
338 input_report_abs(st->ts_input, ABS_X, x);
339 input_report_abs(st->ts_input, ABS_Y, y);
340 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
341 input_report_key(st->ts_input, BTN_TOUCH, 1);
342 input_sync(st->ts_input);
343 } else {
344 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
345 }
346
347 return 0;
348}
349
350static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
351{
352 struct iio_dev *idev = private;
353 struct at91_adc_state *st = iio_priv(idev);
354 u32 status = at91_adc_readl(st, st->registers->status_register);
355 unsigned int reg;
356
357 status &= at91_adc_readl(st, AT91_ADC_IMR);
358 if (status & GENMASK(st->num_channels - 1, 0))
359 handle_adc_eoc_trigger(irq, idev);
360
361 if (status & AT91RL_ADC_IER_PEN) {
362
363 reg = at91_adc_readl(st, AT91_ADC_MR);
364 reg &= ~AT91_ADC_PENDBC;
365 at91_adc_writel(st, AT91_ADC_MR, reg);
366
367 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
368 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
369 | AT91_ADC_EOC(3));
370
371 at91_adc_writel(st, st->registers->trigger_register,
372 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
373 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
374 } else if (status & AT91RL_ADC_IER_NOPEN) {
375 reg = at91_adc_readl(st, AT91_ADC_MR);
376 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
377 at91_adc_writel(st, AT91_ADC_MR, reg);
378 at91_adc_writel(st, st->registers->trigger_register,
379 AT91_ADC_TRGR_NONE);
380
381 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
382 | AT91_ADC_EOC(3));
383 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
384 st->ts_bufferedmeasure = false;
385 input_report_key(st->ts_input, BTN_TOUCH, 0);
386 input_sync(st->ts_input);
387 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
388
389 if (st->ts_bufferedmeasure) {
390
391
392
393
394
395 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
396 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
397 input_report_key(st->ts_input, BTN_TOUCH, 1);
398 input_sync(st->ts_input);
399 } else
400 st->ts_bufferedmeasure = true;
401
402
403 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
404 << MAX_RLPOS_BITS;
405 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
406
407 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
408 << MAX_RLPOS_BITS;
409 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
410 }
411
412 return IRQ_HANDLED;
413}
414
415static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
416{
417 struct iio_dev *idev = private;
418 struct at91_adc_state *st = iio_priv(idev);
419 u32 status = at91_adc_readl(st, st->registers->status_register);
420 const uint32_t ts_data_irq_mask =
421 AT91_ADC_IER_XRDY |
422 AT91_ADC_IER_YRDY |
423 AT91_ADC_IER_PRDY;
424
425 if (status & GENMASK(st->num_channels - 1, 0))
426 handle_adc_eoc_trigger(irq, idev);
427
428 if (status & AT91_ADC_IER_PEN) {
429 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
430 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
431 ts_data_irq_mask);
432
433 at91_adc_writel(st, st->registers->trigger_register,
434 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
435 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
436 } else if (status & AT91_ADC_IER_NOPEN) {
437 at91_adc_writel(st, st->registers->trigger_register, 0);
438 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
439 ts_data_irq_mask);
440 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
441
442 input_report_key(st->ts_input, BTN_TOUCH, 0);
443 input_sync(st->ts_input);
444 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
445
446
447 if (status & AT91_ADC_ISR_PENS) {
448
449 at91_ts_sample(st);
450 } else {
451
452
453
454 at91_adc_readl(st, AT91_ADC_TSXPOSR);
455 at91_adc_readl(st, AT91_ADC_TSYPOSR);
456 at91_adc_readl(st, AT91_ADC_TSPRESSR);
457 }
458 }
459
460 return IRQ_HANDLED;
461}
462
463static int at91_adc_channel_init(struct iio_dev *idev)
464{
465 struct at91_adc_state *st = iio_priv(idev);
466 struct iio_chan_spec *chan_array, *timestamp;
467 int bit, idx = 0;
468 unsigned long rsvd_mask = 0;
469
470
471 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
472 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
473 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
474 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
475
476
477 st->channels_mask &= ~rsvd_mask;
478
479 idev->num_channels = bitmap_weight(&st->channels_mask,
480 st->num_channels) + 1;
481
482 chan_array = devm_kzalloc(&idev->dev,
483 ((idev->num_channels + 1) *
484 sizeof(struct iio_chan_spec)),
485 GFP_KERNEL);
486
487 if (!chan_array)
488 return -ENOMEM;
489
490 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
491 struct iio_chan_spec *chan = chan_array + idx;
492
493 chan->type = IIO_VOLTAGE;
494 chan->indexed = 1;
495 chan->channel = bit;
496 chan->scan_index = idx;
497 chan->scan_type.sign = 'u';
498 chan->scan_type.realbits = st->res;
499 chan->scan_type.storagebits = 16;
500 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
501 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
502 idx++;
503 }
504 timestamp = chan_array + idx;
505
506 timestamp->type = IIO_TIMESTAMP;
507 timestamp->channel = -1;
508 timestamp->scan_index = idx;
509 timestamp->scan_type.sign = 's';
510 timestamp->scan_type.realbits = 64;
511 timestamp->scan_type.storagebits = 64;
512
513 idev->channels = chan_array;
514 return idev->num_channels;
515}
516
517static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
518 struct at91_adc_trigger *triggers,
519 const char *trigger_name)
520{
521 struct at91_adc_state *st = iio_priv(idev);
522 int i;
523
524 for (i = 0; i < st->trigger_number; i++) {
525 char *name = kasprintf(GFP_KERNEL,
526 "%s-dev%d-%s",
527 idev->name,
528 idev->id,
529 triggers[i].name);
530 if (!name)
531 return -ENOMEM;
532
533 if (strcmp(trigger_name, name) == 0) {
534 kfree(name);
535 if (triggers[i].value == 0)
536 return -EINVAL;
537 return triggers[i].value;
538 }
539
540 kfree(name);
541 }
542
543 return -EINVAL;
544}
545
546static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
547{
548 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
549 struct at91_adc_state *st = iio_priv(idev);
550 struct at91_adc_reg_desc *reg = st->registers;
551 u32 status = at91_adc_readl(st, reg->trigger_register);
552 int value;
553 u8 bit;
554
555 value = at91_adc_get_trigger_value_by_name(idev,
556 st->trigger_list,
557 idev->trig->name);
558 if (value < 0)
559 return value;
560
561 if (state) {
562 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
563 if (st->buffer == NULL)
564 return -ENOMEM;
565
566 at91_adc_writel(st, reg->trigger_register,
567 status | value);
568
569 for_each_set_bit(bit, idev->active_scan_mask,
570 st->num_channels) {
571 struct iio_chan_spec const *chan = idev->channels + bit;
572 at91_adc_writel(st, AT91_ADC_CHER,
573 AT91_ADC_CH(chan->channel));
574 }
575
576 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
577
578 } else {
579 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
580
581 at91_adc_writel(st, reg->trigger_register,
582 status & ~value);
583
584 for_each_set_bit(bit, idev->active_scan_mask,
585 st->num_channels) {
586 struct iio_chan_spec const *chan = idev->channels + bit;
587 at91_adc_writel(st, AT91_ADC_CHDR,
588 AT91_ADC_CH(chan->channel));
589 }
590 kfree(st->buffer);
591 }
592
593 return 0;
594}
595
596static const struct iio_trigger_ops at91_adc_trigger_ops = {
597 .set_trigger_state = &at91_adc_configure_trigger,
598};
599
600static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
601 struct at91_adc_trigger *trigger)
602{
603 struct iio_trigger *trig;
604 int ret;
605
606 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
607 idev->id, trigger->name);
608 if (trig == NULL)
609 return NULL;
610
611 trig->dev.parent = idev->dev.parent;
612 iio_trigger_set_drvdata(trig, idev);
613 trig->ops = &at91_adc_trigger_ops;
614
615 ret = iio_trigger_register(trig);
616 if (ret)
617 return NULL;
618
619 return trig;
620}
621
622static int at91_adc_trigger_init(struct iio_dev *idev)
623{
624 struct at91_adc_state *st = iio_priv(idev);
625 int i, ret;
626
627 st->trig = devm_kcalloc(&idev->dev,
628 st->trigger_number, sizeof(*st->trig),
629 GFP_KERNEL);
630
631 if (st->trig == NULL) {
632 ret = -ENOMEM;
633 goto error_ret;
634 }
635
636 for (i = 0; i < st->trigger_number; i++) {
637 if (st->trigger_list[i].is_external && !(st->use_external))
638 continue;
639
640 st->trig[i] = at91_adc_allocate_trigger(idev,
641 st->trigger_list + i);
642 if (st->trig[i] == NULL) {
643 dev_err(&idev->dev,
644 "Could not allocate trigger %d\n", i);
645 ret = -ENOMEM;
646 goto error_trigger;
647 }
648 }
649
650 return 0;
651
652error_trigger:
653 for (i--; i >= 0; i--) {
654 iio_trigger_unregister(st->trig[i]);
655 iio_trigger_free(st->trig[i]);
656 }
657error_ret:
658 return ret;
659}
660
661static void at91_adc_trigger_remove(struct iio_dev *idev)
662{
663 struct at91_adc_state *st = iio_priv(idev);
664 int i;
665
666 for (i = 0; i < st->trigger_number; i++) {
667 iio_trigger_unregister(st->trig[i]);
668 iio_trigger_free(st->trig[i]);
669 }
670}
671
672static int at91_adc_buffer_init(struct iio_dev *idev)
673{
674 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
675 &at91_adc_trigger_handler, NULL);
676}
677
678static void at91_adc_buffer_remove(struct iio_dev *idev)
679{
680 iio_triggered_buffer_cleanup(idev);
681}
682
683static int at91_adc_read_raw(struct iio_dev *idev,
684 struct iio_chan_spec const *chan,
685 int *val, int *val2, long mask)
686{
687 struct at91_adc_state *st = iio_priv(idev);
688 int ret;
689
690 switch (mask) {
691 case IIO_CHAN_INFO_RAW:
692 mutex_lock(&st->lock);
693
694 st->chnb = chan->channel;
695 at91_adc_writel(st, AT91_ADC_CHER,
696 AT91_ADC_CH(chan->channel));
697 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
698 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
699
700 ret = wait_event_interruptible_timeout(st->wq_data_avail,
701 st->done,
702 msecs_to_jiffies(1000));
703 if (ret == 0)
704 ret = -ETIMEDOUT;
705 if (ret < 0) {
706 mutex_unlock(&st->lock);
707 return ret;
708 }
709
710 *val = st->last_value;
711
712 at91_adc_writel(st, AT91_ADC_CHDR,
713 AT91_ADC_CH(chan->channel));
714 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
715
716 st->last_value = 0;
717 st->done = false;
718 mutex_unlock(&st->lock);
719 return IIO_VAL_INT;
720
721 case IIO_CHAN_INFO_SCALE:
722 *val = st->vref_mv;
723 *val2 = chan->scan_type.realbits;
724 return IIO_VAL_FRACTIONAL_LOG2;
725 default:
726 break;
727 }
728 return -EINVAL;
729}
730
731static int at91_adc_of_get_resolution(struct at91_adc_state *st,
732 struct platform_device *pdev)
733{
734 struct iio_dev *idev = iio_priv_to_dev(st);
735 struct device_node *np = pdev->dev.of_node;
736 int count, i, ret = 0;
737 char *res_name, *s;
738 u32 *resolutions;
739
740 count = of_property_count_strings(np, "atmel,adc-res-names");
741 if (count < 2) {
742 dev_err(&idev->dev, "You must specified at least two resolution names for "
743 "adc-res-names property in the DT\n");
744 return count;
745 }
746
747 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
748 if (!resolutions)
749 return -ENOMEM;
750
751 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
752 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
753 ret = -ENODEV;
754 goto ret;
755 }
756
757 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
758 res_name = "highres";
759
760 for (i = 0; i < count; i++) {
761 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
762 continue;
763
764 if (strcmp(res_name, s))
765 continue;
766
767 st->res = resolutions[i];
768 if (!strcmp(res_name, "lowres"))
769 st->low_res = true;
770 else
771 st->low_res = false;
772
773 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
774 goto ret;
775 }
776
777 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
778
779ret:
780 kfree(resolutions);
781 return ret;
782}
783
784static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
785{
786
787
788
789
790
791
792 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
793}
794
795static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
796{
797
798
799
800
801 static const int startup_lookup[] = {
802 0, 8, 16, 24,
803 64, 80, 96, 112,
804 512, 576, 640, 704,
805 768, 832, 896, 960
806 };
807 int i, size = ARRAY_SIZE(startup_lookup);
808 unsigned int ticks;
809
810 ticks = startup_time * adc_clk_khz / 1000;
811 for (i = 0; i < size; i++)
812 if (ticks < startup_lookup[i])
813 break;
814
815 ticks = i;
816 if (ticks == size)
817
818 ticks = size - 1;
819
820 return ticks;
821}
822
823static const struct of_device_id at91_adc_dt_ids[];
824
825static int at91_adc_probe_dt_ts(struct device_node *node,
826 struct at91_adc_state *st, struct device *dev)
827{
828 int ret;
829 u32 prop;
830
831 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
832 if (ret) {
833 dev_info(dev, "ADC Touch screen is disabled.\n");
834 return 0;
835 }
836
837 switch (prop) {
838 case 4:
839 case 5:
840 st->touchscreen_type = prop;
841 break;
842 default:
843 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
844 return -EINVAL;
845 }
846
847 if (!st->caps->has_tsmr)
848 return 0;
849 prop = 0;
850 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
851 st->ts_pressure_threshold = prop;
852 if (st->ts_pressure_threshold) {
853 return 0;
854 } else {
855 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
856 return -EINVAL;
857 }
858}
859
860static int at91_adc_probe_dt(struct at91_adc_state *st,
861 struct platform_device *pdev)
862{
863 struct iio_dev *idev = iio_priv_to_dev(st);
864 struct device_node *node = pdev->dev.of_node;
865 struct device_node *trig_node;
866 int i = 0, ret;
867 u32 prop;
868
869 if (!node)
870 return -EINVAL;
871
872 st->caps = (struct at91_adc_caps *)
873 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
874
875 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
876
877 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
878 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
879 ret = -EINVAL;
880 goto error_ret;
881 }
882 st->channels_mask = prop;
883
884 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
885
886 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
887 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
888 ret = -EINVAL;
889 goto error_ret;
890 }
891 st->startup_time = prop;
892
893 prop = 0;
894 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
895 st->sample_hold_time = prop;
896
897 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
898 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
899 ret = -EINVAL;
900 goto error_ret;
901 }
902 st->vref_mv = prop;
903
904 ret = at91_adc_of_get_resolution(st, pdev);
905 if (ret)
906 goto error_ret;
907
908 st->registers = &st->caps->registers;
909 st->num_channels = st->caps->num_channels;
910 st->trigger_number = of_get_child_count(node);
911 st->trigger_list = devm_kcalloc(&idev->dev,
912 st->trigger_number,
913 sizeof(struct at91_adc_trigger),
914 GFP_KERNEL);
915 if (!st->trigger_list) {
916 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
917 ret = -ENOMEM;
918 goto error_ret;
919 }
920
921 for_each_child_of_node(node, trig_node) {
922 struct at91_adc_trigger *trig = st->trigger_list + i;
923 const char *name;
924
925 if (of_property_read_string(trig_node, "trigger-name", &name)) {
926 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
927 ret = -EINVAL;
928 goto error_ret;
929 }
930 trig->name = name;
931
932 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
933 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
934 ret = -EINVAL;
935 goto error_ret;
936 }
937 trig->value = prop;
938 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
939 i++;
940 }
941
942
943 if (st->caps->has_ts)
944 return at91_adc_probe_dt_ts(node, st, &idev->dev);
945 else
946 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
947
948 return 0;
949
950error_ret:
951 return ret;
952}
953
954static int at91_adc_probe_pdata(struct at91_adc_state *st,
955 struct platform_device *pdev)
956{
957 struct at91_adc_data *pdata = pdev->dev.platform_data;
958
959 if (!pdata)
960 return -EINVAL;
961
962 st->caps = (struct at91_adc_caps *)
963 platform_get_device_id(pdev)->driver_data;
964
965 st->use_external = pdata->use_external_triggers;
966 st->vref_mv = pdata->vref;
967 st->channels_mask = pdata->channels_used;
968 st->num_channels = st->caps->num_channels;
969 st->startup_time = pdata->startup_time;
970 st->trigger_number = pdata->trigger_number;
971 st->trigger_list = pdata->trigger_list;
972 st->registers = &st->caps->registers;
973 st->touchscreen_type = pdata->touchscreen_type;
974
975 return 0;
976}
977
978static const struct iio_info at91_adc_info = {
979 .read_raw = &at91_adc_read_raw,
980};
981
982
983static int atmel_ts_open(struct input_dev *dev)
984{
985 struct at91_adc_state *st = input_get_drvdata(dev);
986
987 if (st->caps->has_tsmr)
988 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
989 else
990 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
991 return 0;
992}
993
994static void atmel_ts_close(struct input_dev *dev)
995{
996 struct at91_adc_state *st = input_get_drvdata(dev);
997
998 if (st->caps->has_tsmr)
999 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1000 else
1001 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1002}
1003
1004static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1005{
1006 struct iio_dev *idev = iio_priv_to_dev(st);
1007 u32 reg = 0;
1008 u32 tssctim = 0;
1009 int i = 0;
1010
1011
1012
1013
1014
1015 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1016 1000, 1);
1017
1018 while (st->ts_pendbc >> ++i)
1019 ;
1020 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1021 st->ts_pendbc = i;
1022 else
1023 st->ts_pendbc = i - 1;
1024
1025 if (!st->caps->has_tsmr) {
1026 reg = at91_adc_readl(st, AT91_ADC_MR);
1027 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1028
1029 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1030 at91_adc_writel(st, AT91_ADC_MR, reg);
1031
1032 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1033 at91_adc_writel(st, AT91_ADC_TSR, reg);
1034
1035 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1036 adc_clk_khz / 1000) - 1, 1);
1037
1038 return 0;
1039 }
1040
1041
1042
1043
1044
1045 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1046 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1047 adc_clk_khz, tssctim);
1048
1049 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1050 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1051 else
1052 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1053
1054 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1055 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1056 & AT91_ADC_TSMR_TSAV;
1057 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1058 reg |= AT91_ADC_TSMR_NOTSDMA;
1059 reg |= AT91_ADC_TSMR_PENDET_ENA;
1060 reg |= 0x03 << 8;
1061
1062 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1063
1064
1065
1066
1067
1068
1069 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1070 & AT91_ADC_ACR_PENDETSENS);
1071
1072
1073 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1074 adc_clk_khz / 1000) - 1, 1);
1075
1076 return 0;
1077}
1078
1079static int at91_ts_register(struct at91_adc_state *st,
1080 struct platform_device *pdev)
1081{
1082 struct input_dev *input;
1083 struct iio_dev *idev = iio_priv_to_dev(st);
1084 int ret;
1085
1086 input = input_allocate_device();
1087 if (!input) {
1088 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1089 return -ENOMEM;
1090 }
1091
1092 input->name = DRIVER_NAME;
1093 input->id.bustype = BUS_HOST;
1094 input->dev.parent = &pdev->dev;
1095 input->open = atmel_ts_open;
1096 input->close = atmel_ts_close;
1097
1098 __set_bit(EV_ABS, input->evbit);
1099 __set_bit(EV_KEY, input->evbit);
1100 __set_bit(BTN_TOUCH, input->keybit);
1101 if (st->caps->has_tsmr) {
1102 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1103 0, 0);
1104 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1105 0, 0);
1106 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1107 } else {
1108 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1109 dev_err(&pdev->dev,
1110 "This touchscreen controller only support 4 wires\n");
1111 ret = -EINVAL;
1112 goto err;
1113 }
1114
1115 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1116 0, 0);
1117 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1118 0, 0);
1119 }
1120
1121 st->ts_input = input;
1122 input_set_drvdata(input, st);
1123
1124 ret = input_register_device(input);
1125 if (ret)
1126 goto err;
1127
1128 return ret;
1129
1130err:
1131 input_free_device(st->ts_input);
1132 return ret;
1133}
1134
1135static void at91_ts_unregister(struct at91_adc_state *st)
1136{
1137 input_unregister_device(st->ts_input);
1138}
1139
1140static int at91_adc_probe(struct platform_device *pdev)
1141{
1142 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1143 int ret;
1144 struct iio_dev *idev;
1145 struct at91_adc_state *st;
1146 struct resource *res;
1147 u32 reg;
1148
1149 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1150 if (!idev)
1151 return -ENOMEM;
1152
1153 st = iio_priv(idev);
1154
1155 if (pdev->dev.of_node)
1156 ret = at91_adc_probe_dt(st, pdev);
1157 else
1158 ret = at91_adc_probe_pdata(st, pdev);
1159
1160 if (ret) {
1161 dev_err(&pdev->dev, "No platform data available.\n");
1162 return -EINVAL;
1163 }
1164
1165 platform_set_drvdata(pdev, idev);
1166
1167 idev->dev.parent = &pdev->dev;
1168 idev->name = dev_name(&pdev->dev);
1169 idev->modes = INDIO_DIRECT_MODE;
1170 idev->info = &at91_adc_info;
1171
1172 st->irq = platform_get_irq(pdev, 0);
1173 if (st->irq < 0) {
1174 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1175 return -ENODEV;
1176 }
1177
1178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1179
1180 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1181 if (IS_ERR(st->reg_base))
1182 return PTR_ERR(st->reg_base);
1183
1184
1185
1186
1187
1188 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1189 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1190
1191 if (st->caps->has_tsmr)
1192 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1193 pdev->dev.driver->name, idev);
1194 else
1195 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1196 pdev->dev.driver->name, idev);
1197 if (ret) {
1198 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1199 return ret;
1200 }
1201
1202 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1203 if (IS_ERR(st->clk)) {
1204 dev_err(&pdev->dev, "Failed to get the clock.\n");
1205 ret = PTR_ERR(st->clk);
1206 goto error_free_irq;
1207 }
1208
1209 ret = clk_prepare_enable(st->clk);
1210 if (ret) {
1211 dev_err(&pdev->dev,
1212 "Could not prepare or enable the clock.\n");
1213 goto error_free_irq;
1214 }
1215
1216 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1217 if (IS_ERR(st->adc_clk)) {
1218 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1219 ret = PTR_ERR(st->adc_clk);
1220 goto error_disable_clk;
1221 }
1222
1223 ret = clk_prepare_enable(st->adc_clk);
1224 if (ret) {
1225 dev_err(&pdev->dev,
1226 "Could not prepare or enable the ADC clock.\n");
1227 goto error_disable_clk;
1228 }
1229
1230
1231
1232
1233
1234
1235 mstrclk = clk_get_rate(st->clk);
1236 adc_clk = clk_get_rate(st->adc_clk);
1237 adc_clk_khz = adc_clk / 1000;
1238
1239 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1240 mstrclk, adc_clk);
1241
1242 prsc = (mstrclk / (2 * adc_clk)) - 1;
1243
1244 if (!st->startup_time) {
1245 dev_err(&pdev->dev, "No startup time available.\n");
1246 ret = -EINVAL;
1247 goto error_disable_adc_clk;
1248 }
1249 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1250
1251
1252
1253
1254
1255
1256 if (st->sample_hold_time > 0)
1257 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1258 - 1, 1);
1259 else
1260 shtim = 0;
1261
1262 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1263 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1264 if (st->low_res)
1265 reg |= AT91_ADC_LOWRES;
1266 if (st->sleep_mode)
1267 reg |= AT91_ADC_SLEEP;
1268 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1269 at91_adc_writel(st, AT91_ADC_MR, reg);
1270
1271
1272 ret = at91_adc_channel_init(idev);
1273 if (ret < 0) {
1274 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1275 goto error_disable_adc_clk;
1276 }
1277
1278 init_waitqueue_head(&st->wq_data_avail);
1279 mutex_init(&st->lock);
1280
1281
1282
1283
1284
1285
1286 if (!st->touchscreen_type) {
1287 ret = at91_adc_buffer_init(idev);
1288 if (ret < 0) {
1289 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1290 goto error_disable_adc_clk;
1291 }
1292
1293 ret = at91_adc_trigger_init(idev);
1294 if (ret < 0) {
1295 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1296 at91_adc_buffer_remove(idev);
1297 goto error_disable_adc_clk;
1298 }
1299 } else {
1300 ret = at91_ts_register(st, pdev);
1301 if (ret)
1302 goto error_disable_adc_clk;
1303
1304 at91_ts_hw_init(st, adc_clk_khz);
1305 }
1306
1307 ret = iio_device_register(idev);
1308 if (ret < 0) {
1309 dev_err(&pdev->dev, "Couldn't register the device.\n");
1310 goto error_iio_device_register;
1311 }
1312
1313 return 0;
1314
1315error_iio_device_register:
1316 if (!st->touchscreen_type) {
1317 at91_adc_trigger_remove(idev);
1318 at91_adc_buffer_remove(idev);
1319 } else {
1320 at91_ts_unregister(st);
1321 }
1322error_disable_adc_clk:
1323 clk_disable_unprepare(st->adc_clk);
1324error_disable_clk:
1325 clk_disable_unprepare(st->clk);
1326error_free_irq:
1327 free_irq(st->irq, idev);
1328 return ret;
1329}
1330
1331static int at91_adc_remove(struct platform_device *pdev)
1332{
1333 struct iio_dev *idev = platform_get_drvdata(pdev);
1334 struct at91_adc_state *st = iio_priv(idev);
1335
1336 iio_device_unregister(idev);
1337 if (!st->touchscreen_type) {
1338 at91_adc_trigger_remove(idev);
1339 at91_adc_buffer_remove(idev);
1340 } else {
1341 at91_ts_unregister(st);
1342 }
1343 clk_disable_unprepare(st->adc_clk);
1344 clk_disable_unprepare(st->clk);
1345 free_irq(st->irq, idev);
1346
1347 return 0;
1348}
1349
1350#ifdef CONFIG_PM_SLEEP
1351static int at91_adc_suspend(struct device *dev)
1352{
1353 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1354 struct at91_adc_state *st = iio_priv(idev);
1355
1356 pinctrl_pm_select_sleep_state(dev);
1357 clk_disable_unprepare(st->clk);
1358
1359 return 0;
1360}
1361
1362static int at91_adc_resume(struct device *dev)
1363{
1364 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1365 struct at91_adc_state *st = iio_priv(idev);
1366
1367 clk_prepare_enable(st->clk);
1368 pinctrl_pm_select_default_state(dev);
1369
1370 return 0;
1371}
1372#endif
1373
1374static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1375
1376static struct at91_adc_caps at91sam9260_caps = {
1377 .calc_startup_ticks = calc_startup_ticks_9260,
1378 .num_channels = 4,
1379 .registers = {
1380 .channel_base = AT91_ADC_CHR(0),
1381 .drdy_mask = AT91_ADC_DRDY,
1382 .status_register = AT91_ADC_SR,
1383 .trigger_register = AT91_ADC_TRGR_9260,
1384 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1385 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1386 },
1387};
1388
1389static struct at91_adc_caps at91sam9rl_caps = {
1390 .has_ts = true,
1391 .calc_startup_ticks = calc_startup_ticks_9260,
1392 .num_channels = 6,
1393 .registers = {
1394 .channel_base = AT91_ADC_CHR(0),
1395 .drdy_mask = AT91_ADC_DRDY,
1396 .status_register = AT91_ADC_SR,
1397 .trigger_register = AT91_ADC_TRGR_9G45,
1398 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1399 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1400 },
1401};
1402
1403static struct at91_adc_caps at91sam9g45_caps = {
1404 .has_ts = true,
1405 .calc_startup_ticks = calc_startup_ticks_9260,
1406 .num_channels = 8,
1407 .registers = {
1408 .channel_base = AT91_ADC_CHR(0),
1409 .drdy_mask = AT91_ADC_DRDY,
1410 .status_register = AT91_ADC_SR,
1411 .trigger_register = AT91_ADC_TRGR_9G45,
1412 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1413 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1414 },
1415};
1416
1417static struct at91_adc_caps at91sam9x5_caps = {
1418 .has_ts = true,
1419 .has_tsmr = true,
1420 .ts_filter_average = 3,
1421 .ts_pen_detect_sensitivity = 2,
1422 .calc_startup_ticks = calc_startup_ticks_9x5,
1423 .num_channels = 12,
1424 .registers = {
1425 .channel_base = AT91_ADC_CDR0_9X5,
1426 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1427 .status_register = AT91_ADC_SR_9X5,
1428 .trigger_register = AT91_ADC_TRGR_9X5,
1429
1430 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1431 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1432 },
1433};
1434
1435static const struct of_device_id at91_adc_dt_ids[] = {
1436 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1437 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1438 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1439 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1440 {},
1441};
1442MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1443
1444static const struct platform_device_id at91_adc_ids[] = {
1445 {
1446 .name = "at91sam9260-adc",
1447 .driver_data = (unsigned long)&at91sam9260_caps,
1448 }, {
1449 .name = "at91sam9rl-adc",
1450 .driver_data = (unsigned long)&at91sam9rl_caps,
1451 }, {
1452 .name = "at91sam9g45-adc",
1453 .driver_data = (unsigned long)&at91sam9g45_caps,
1454 }, {
1455 .name = "at91sam9x5-adc",
1456 .driver_data = (unsigned long)&at91sam9x5_caps,
1457 }, {
1458
1459 }
1460};
1461MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1462
1463static struct platform_driver at91_adc_driver = {
1464 .probe = at91_adc_probe,
1465 .remove = at91_adc_remove,
1466 .id_table = at91_adc_ids,
1467 .driver = {
1468 .name = DRIVER_NAME,
1469 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1470 .pm = &at91_adc_pm_ops,
1471 },
1472};
1473
1474module_platform_driver(at91_adc_driver);
1475
1476MODULE_LICENSE("GPL");
1477MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1478MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1479
