LXR linux/drivers/infiniband/hw/hns/hns_roce

   1/*
   2 * Copyright (c) 2016 Hisilicon Limited.
   3 *
   4 * This software is available to you under a choice of one of two
   5 * licenses.  You may choose to be licensed under the terms of the GNU
   6 * General Public License (GPL) Version 2, available from the file
   7 * COPYING in the main directory of this source tree, or the
   8 * OpenIB.org BSD license below:
   9 *
  10 *     Redistribution and use in source and binary forms, with or
  11 *     without modification, are permitted provided that the following
  12 *     conditions are met:
  13 *
  14 *      - Redistributions of source code must retain the above
  15 *        copyright notice, this list of conditions and the following
  16 *        disclaimer.
  17 *
  18 *      - Redistributions in binary form must reproduce the above
  19 *        copyright notice, this list of conditions and the following
  20 *        disclaimer in the documentation and/or other materials
  21 *        provided with the distribution.
  22 *
  23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30 * SOFTWARE.
  31 */
  32
  33#ifndef _HNS_ROCE_CMD_H
  34#define _HNS_ROCE_CMD_H
  35
  36#define HNS_ROCE_MAILBOX_SIZE           4096
  37#define HNS_ROCE_CMD_TIMEOUT_MSECS      10000
  38
  39enum {
  40        /* QPC BT commands */
  41        HNS_ROCE_CMD_WRITE_QPC_BT0      = 0x0,
  42        HNS_ROCE_CMD_WRITE_QPC_BT1      = 0x1,
  43        HNS_ROCE_CMD_WRITE_QPC_BT2      = 0x2,
  44        HNS_ROCE_CMD_READ_QPC_BT0       = 0x4,
  45        HNS_ROCE_CMD_READ_QPC_BT1       = 0x5,
  46        HNS_ROCE_CMD_READ_QPC_BT2       = 0x6,
  47        HNS_ROCE_CMD_DESTROY_QPC_BT0    = 0x8,
  48        HNS_ROCE_CMD_DESTROY_QPC_BT1    = 0x9,
  49        HNS_ROCE_CMD_DESTROY_QPC_BT2    = 0xa,
  50
  51        /* QPC operation */
  52        HNS_ROCE_CMD_MODIFY_QPC         = 0x41,
  53        HNS_ROCE_CMD_QUERY_QPC          = 0x42,
  54
  55        HNS_ROCE_CMD_MODIFY_CQC         = 0x52,
  56        /* CQC BT commands */
  57        HNS_ROCE_CMD_WRITE_CQC_BT0      = 0x10,
  58        HNS_ROCE_CMD_WRITE_CQC_BT1      = 0x11,
  59        HNS_ROCE_CMD_WRITE_CQC_BT2      = 0x12,
  60        HNS_ROCE_CMD_READ_CQC_BT0       = 0x14,
  61        HNS_ROCE_CMD_READ_CQC_BT1       = 0x15,
  62        HNS_ROCE_CMD_READ_CQC_BT2       = 0x1b,
  63        HNS_ROCE_CMD_DESTROY_CQC_BT0    = 0x18,
  64        HNS_ROCE_CMD_DESTROY_CQC_BT1    = 0x19,
  65        HNS_ROCE_CMD_DESTROY_CQC_BT2    = 0x1a,
  66
  67        /* MPT BT commands */
  68        HNS_ROCE_CMD_WRITE_MPT_BT0      = 0x20,
  69        HNS_ROCE_CMD_WRITE_MPT_BT1      = 0x21,
  70        HNS_ROCE_CMD_WRITE_MPT_BT2      = 0x22,
  71        HNS_ROCE_CMD_READ_MPT_BT0       = 0x24,
  72        HNS_ROCE_CMD_READ_MPT_BT1       = 0x25,
  73        HNS_ROCE_CMD_READ_MPT_BT2       = 0x26,
  74        HNS_ROCE_CMD_DESTROY_MPT_BT0    = 0x28,
  75        HNS_ROCE_CMD_DESTROY_MPT_BT1    = 0x29,
  76        HNS_ROCE_CMD_DESTROY_MPT_BT2    = 0x2a,
  77
  78        /* MPT commands */
  79        HNS_ROCE_CMD_QUERY_MPT          = 0x62,
  80
  81        /* SRQC BT commands */
  82        HNS_ROCE_CMD_WRITE_SRQC_BT0     = 0x30,
  83        HNS_ROCE_CMD_WRITE_SRQC_BT1     = 0x31,
  84        HNS_ROCE_CMD_WRITE_SRQC_BT2     = 0x32,
  85        HNS_ROCE_CMD_READ_SRQC_BT0      = 0x34,
  86        HNS_ROCE_CMD_READ_SRQC_BT1      = 0x35,
  87        HNS_ROCE_CMD_READ_SRQC_BT2      = 0x36,
  88        HNS_ROCE_CMD_DESTROY_SRQC_BT0   = 0x38,
  89        HNS_ROCE_CMD_DESTROY_SRQC_BT1   = 0x39,
  90        HNS_ROCE_CMD_DESTROY_SRQC_BT2   = 0x3a,
  91
  92        /* EQC commands */
  93        HNS_ROCE_CMD_CREATE_AEQC        = 0x80,
  94        HNS_ROCE_CMD_MODIFY_AEQC        = 0x81,
  95        HNS_ROCE_CMD_QUERY_AEQC         = 0x82,
  96        HNS_ROCE_CMD_DESTROY_AEQC       = 0x83,
  97        HNS_ROCE_CMD_CREATE_CEQC        = 0x90,
  98        HNS_ROCE_CMD_MODIFY_CEQC        = 0x91,
  99        HNS_ROCE_CMD_QUERY_CEQC         = 0x92,
 100        HNS_ROCE_CMD_DESTROY_CEQC       = 0x93,
 101};
 102
 103enum {
 104        /* TPT commands */
 105        HNS_ROCE_CMD_SW2HW_MPT          = 0xd,
 106        HNS_ROCE_CMD_HW2SW_MPT          = 0xf,
 107
 108        /* CQ commands */
 109        HNS_ROCE_CMD_SW2HW_CQ           = 0x16,
 110        HNS_ROCE_CMD_HW2SW_CQ           = 0x17,
 111
 112        /* QP/EE commands */
 113        HNS_ROCE_CMD_RST2INIT_QP        = 0x19,
 114        HNS_ROCE_CMD_INIT2RTR_QP        = 0x1a,
 115        HNS_ROCE_CMD_RTR2RTS_QP         = 0x1b,
 116        HNS_ROCE_CMD_RTS2RTS_QP         = 0x1c,
 117        HNS_ROCE_CMD_2ERR_QP            = 0x1e,
 118        HNS_ROCE_CMD_RTS2SQD_QP         = 0x1f,
 119        HNS_ROCE_CMD_SQD2SQD_QP         = 0x38,
 120        HNS_ROCE_CMD_SQD2RTS_QP         = 0x20,
 121        HNS_ROCE_CMD_2RST_QP            = 0x21,
 122        HNS_ROCE_CMD_QUERY_QP           = 0x22,
 123};
 124
 125int hns_roce_cmd_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u64 out_param,
 126                      unsigned long in_modifier, u8 op_modifier, u16 op,
 127                      unsigned long timeout);
 128
 129struct hns_roce_cmd_mailbox
 130        *hns_roce_alloc_cmd_mailbox(struct hns_roce_dev *hr_dev);
 131void hns_roce_free_cmd_mailbox(struct hns_roce_dev *hr_dev,
 132                               struct hns_roce_cmd_mailbox *mailbox);
 133
 134#endif /* _HNS_ROCE_CMD_H */
 135