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13#ifndef __DIB3000MB_PRIV_H_INCLUDED__
14#define __DIB3000MB_PRIV_H_INCLUDED__
15
16
17#define rd(reg) dib3000_read_reg(state,reg)
18
19#define wr(reg,val) if (dib3000_write_reg(state,reg,val)) \
20 { pr_err("while sending 0x%04x to 0x%04x.", val, reg); return -EREMOTEIO; }
21
22#define wr_foreach(a,v) { int i; \
23 if (sizeof(a) != sizeof(v)) \
24 pr_err("sizeof: %zu %zu is different", sizeof(a), sizeof(v));\
25 for (i=0; i < sizeof(a)/sizeof(u16); i++) \
26 wr(a[i],v[i]); \
27 }
28
29#define set_or(reg,val) wr(reg,rd(reg) | val)
30
31#define set_and(reg,val) wr(reg,rd(reg) & val)
32
33
34
35#define dprintk(level, fmt, arg...) do { \
36 if (debug & level) \
37 printk(KERN_DEBUG pr_fmt("%s: " fmt), \
38 __func__, ##arg); \
39} while (0)
40
41
42#define DIB3000_ACTIVATE_PID_FILTERING (0x2000)
43
44
45#define DIB3000_ALPHA_0 ( 0)
46#define DIB3000_ALPHA_1 ( 1)
47#define DIB3000_ALPHA_2 ( 2)
48#define DIB3000_ALPHA_4 ( 4)
49
50#define DIB3000_CONSTELLATION_QPSK ( 0)
51#define DIB3000_CONSTELLATION_16QAM ( 1)
52#define DIB3000_CONSTELLATION_64QAM ( 2)
53
54#define DIB3000_GUARD_TIME_1_32 ( 0)
55#define DIB3000_GUARD_TIME_1_16 ( 1)
56#define DIB3000_GUARD_TIME_1_8 ( 2)
57#define DIB3000_GUARD_TIME_1_4 ( 3)
58
59#define DIB3000_TRANSMISSION_MODE_2K ( 0)
60#define DIB3000_TRANSMISSION_MODE_8K ( 1)
61
62#define DIB3000_SELECT_LP ( 0)
63#define DIB3000_SELECT_HP ( 1)
64
65#define DIB3000_FEC_1_2 ( 1)
66#define DIB3000_FEC_2_3 ( 2)
67#define DIB3000_FEC_3_4 ( 3)
68#define DIB3000_FEC_5_6 ( 5)
69#define DIB3000_FEC_7_8 ( 7)
70
71#define DIB3000_HRCH_OFF ( 0)
72#define DIB3000_HRCH_ON ( 1)
73
74#define DIB3000_DDS_INVERSION_OFF ( 0)
75#define DIB3000_DDS_INVERSION_ON ( 1)
76
77#define DIB3000_TUNER_WRITE_ENABLE(a) (0xffff & (a << 8))
78#define DIB3000_TUNER_WRITE_DISABLE(a) (0xffff & ((a << 8) | (1 << 7)))
79
80#define DIB3000_REG_MANUFACTOR_ID ( 1025)
81#define DIB3000_I2C_ID_DIBCOM (0x01b3)
82
83#define DIB3000_REG_DEVICE_ID ( 1026)
84#define DIB3000MB_DEVICE_ID (0x3000)
85#define DIB3000MC_DEVICE_ID (0x3001)
86#define DIB3000P_DEVICE_ID (0x3002)
87
88
89struct dib3000_state {
90 struct i2c_adapter* i2c;
91
92
93 struct dib3000_config config;
94
95 struct dvb_frontend frontend;
96 int timing_offset;
97 int timing_offset_comp_done;
98
99 u32 last_tuned_bw;
100 u32 last_tuned_freq;
101};
102
103
104
105
106#define DIB3000MB_REG_RESTART ( 0)
107
108#define DIB3000MB_RESTART_OFF ( 0)
109#define DIB3000MB_RESTART_AUTO_SEARCH (1 << 1)
110#define DIB3000MB_RESTART_CTRL (1 << 2)
111#define DIB3000MB_RESTART_AGC (1 << 3)
112
113
114#define DIB3000MB_REG_FFT ( 1)
115
116
117#define DIB3000MB_REG_GUARD_TIME ( 2)
118
119
120#define DIB3000MB_REG_QAM ( 3)
121
122
123#define DIB3000MB_REG_VIT_ALPHA ( 4)
124
125
126#define DIB3000MB_REG_DDS_INV ( 5)
127
128
129#define DIB3000MB_REG_DDS_FREQ_MSB ( 6)
130#define DIB3000MB_REG_DDS_FREQ_LSB ( 7)
131#define DIB3000MB_DDS_FREQ_MSB ( 178)
132#define DIB3000MB_DDS_FREQ_LSB ( 8990)
133
134
135static u16 dib3000mb_reg_timing_freq[] = { 8,9 };
136static u16 dib3000mb_timing_freq[][2] = {
137 { 126 , 48873 },
138 { 147 , 57019 },
139 { 168 , 65164 },
140};
141
142
143
144
145static u16 dib3000mb_reg_impulse_noise[] = { 10,11,12,15,36 };
146
147enum dib3000mb_impulse_noise_type {
148 DIB3000MB_IMPNOISE_OFF,
149 DIB3000MB_IMPNOISE_MOBILE,
150 DIB3000MB_IMPNOISE_FIXED,
151 DIB3000MB_IMPNOISE_DEFAULT
152};
153
154static u16 dib3000mb_impulse_noise_values[][5] = {
155 { 0x0000, 0x0004, 0x0014, 0x01ff, 0x0399 },
156 { 0x0001, 0x0004, 0x0014, 0x01ff, 0x037b },
157 { 0x0001, 0x0004, 0x0020, 0x01bd, 0x0399 },
158 { 0x0000, 0x0002, 0x000a, 0x01ff, 0x0399 },
159};
160
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166
167
168static u16 dib3000mb_reg_agc_gain[] = {
169 19,20,21,22,23,24,25,26,27,28,29,30,31,32
170};
171
172static u16 dib3000mb_default_agc_gain[] =
173 { 0x0001, 52429, 623, 128, 166, 195, 61,
174 0x0001, 53766, 38011, 0, 90, 33, 23 };
175
176
177
178static u16 dib3000mb_reg_phase_noise[] = { 33,34,35,37,38 };
179
180static u16 dib3000mb_default_noise_phase[] = { 2, 544, 0, 5, 4 };
181
182
183static u16 dib3000mb_reg_lock_duration[] = { 39,40 };
184static u16 dib3000mb_default_lock_duration[] = { 135, 135 };
185
186
187static u16 dib3000mb_reg_agc_bandwidth[] = { 43,44,45,46,47,48,49,50 };
188
189static u16 dib3000mb_agc_bandwidth_low[] =
190 { 2088, 10, 2088, 10, 3448, 5, 3448, 5 };
191static u16 dib3000mb_agc_bandwidth_high[] =
192 { 2349, 5, 2349, 5, 2586, 2, 2586, 2 };
193
194
195
196
197#define DIB3000MB_REG_LOCK0_MASK ( 51)
198#define DIB3000MB_LOCK0_DEFAULT ( 4)
199
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203
204
205#define DIB3000MB_REG_LOCK1_MASK ( 52)
206#define DIB3000MB_LOCK1_SEARCH_4 (0x0004)
207#define DIB3000MB_LOCK1_SEARCH_2048 (0x0800)
208#define DIB3000MB_LOCK1_DEFAULT (0x0001)
209
210
211
212#define DIB3000MB_REG_LOCK2_MASK ( 53)
213#define DIB3000MB_LOCK2_DEFAULT (0x0080)
214
215
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217
218
219
220#define DIB3000MB_REG_SEQ ( 54)
221
222
223static u16 dib3000mb_reg_bandwidth[] = { 55,56,57,58,59,60,61,62,63,64,65,66,67 };
224static u16 dib3000mb_bandwidth_6mhz[] =
225 { 0, 33, 53312, 112, 46635, 563, 36565, 0, 1000, 0, 1010, 1, 45264 };
226
227static u16 dib3000mb_bandwidth_7mhz[] =
228 { 0, 28, 64421, 96, 39973, 483, 3255, 0, 1000, 0, 1010, 1, 45264 };
229
230static u16 dib3000mb_bandwidth_8mhz[] =
231 { 0, 25, 23600, 84, 34976, 422, 43808, 0, 1000, 0, 1010, 1, 45264 };
232
233#define DIB3000MB_REG_UNK_68 ( 68)
234#define DIB3000MB_UNK_68 ( 0)
235
236#define DIB3000MB_REG_UNK_69 ( 69)
237#define DIB3000MB_UNK_69 ( 0)
238
239#define DIB3000MB_REG_UNK_71 ( 71)
240#define DIB3000MB_UNK_71 ( 0)
241
242#define DIB3000MB_REG_UNK_77 ( 77)
243#define DIB3000MB_UNK_77 ( 6)
244
245#define DIB3000MB_REG_UNK_78 ( 78)
246#define DIB3000MB_UNK_78 (0x0080)
247
248
249#define DIB3000MB_REG_ISI ( 79)
250#define DIB3000MB_ISI_ACTIVATE ( 0)
251#define DIB3000MB_ISI_INHIBIT ( 1)
252
253
254#define DIB3000MB_REG_SYNC_IMPROVEMENT ( 84)
255#define DIB3000MB_SYNC_IMPROVE_2K_1_8 ( 3)
256#define DIB3000MB_SYNC_IMPROVE_DEFAULT ( 0)
257
258
259#define DIB3000MB_REG_PHASE_NOISE ( 87)
260#define DIB3000MB_PHASE_NOISE_DEFAULT ( 0)
261
262#define DIB3000MB_REG_UNK_92 ( 92)
263#define DIB3000MB_UNK_92 (0x0080)
264
265#define DIB3000MB_REG_UNK_96 ( 96)
266#define DIB3000MB_UNK_96 (0x0010)
267
268#define DIB3000MB_REG_UNK_97 ( 97)
269#define DIB3000MB_UNK_97 (0x0009)
270
271
272#define DIB3000MB_REG_MOBILE_MODE ( 101)
273#define DIB3000MB_MOBILE_MODE_ON ( 1)
274#define DIB3000MB_MOBILE_MODE_OFF ( 0)
275
276#define DIB3000MB_REG_UNK_106 ( 106)
277#define DIB3000MB_UNK_106 (0x0080)
278
279#define DIB3000MB_REG_UNK_107 ( 107)
280#define DIB3000MB_UNK_107 (0x0080)
281
282#define DIB3000MB_REG_UNK_108 ( 108)
283#define DIB3000MB_UNK_108 (0x0080)
284
285
286#define DIB3000MB_REG_UNK_121 ( 121)
287#define DIB3000MB_UNK_121_2K ( 7)
288#define DIB3000MB_UNK_121_DEFAULT ( 5)
289
290#define DIB3000MB_REG_UNK_122 ( 122)
291#define DIB3000MB_UNK_122 ( 2867)
292
293
294#define DIB3000MB_REG_MOBILE_MODE_QAM ( 126)
295#define DIB3000MB_MOBILE_MODE_QAM_64 ( 3)
296#define DIB3000MB_MOBILE_MODE_QAM_QPSK_16 ( 1)
297#define DIB3000MB_MOBILE_MODE_QAM_OFF ( 0)
298
299
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302
303#define DIB3000MB_REG_DATA_IN_DIVERSITY ( 127)
304#define DIB3000MB_DATA_DIVERSITY_IN_OFF ( 0)
305#define DIB3000MB_DATA_DIVERSITY_IN_ON ( 2)
306
307
308#define DIB3000MB_REG_VIT_HRCH ( 128)
309
310
311#define DIB3000MB_REG_VIT_CODE_RATE ( 129)
312
313
314#define DIB3000MB_REG_VIT_HP ( 130)
315
316
317#define DIB3000MB_REG_BERLEN ( 135)
318#define DIB3000MB_BERLEN_LONG ( 0)
319#define DIB3000MB_BERLEN_DEFAULT ( 1)
320#define DIB3000MB_BERLEN_MEDIUM ( 2)
321#define DIB3000MB_BERLEN_SHORT ( 3)
322
323
324
325
326
327#define DIB3000MB_REG_FIFO_142 ( 142)
328#define DIB3000MB_FIFO_142 ( 0)
329
330
331#define DIB3000MB_REG_MPEG2_OUT_MODE ( 143)
332#define DIB3000MB_MPEG2_OUT_MODE_204 ( 0)
333#define DIB3000MB_MPEG2_OUT_MODE_188 ( 1)
334
335#define DIB3000MB_REG_PID_PARSE ( 144)
336#define DIB3000MB_PID_PARSE_INHIBIT ( 0)
337#define DIB3000MB_PID_PARSE_ACTIVATE ( 1)
338
339#define DIB3000MB_REG_FIFO ( 145)
340#define DIB3000MB_FIFO_INHIBIT ( 1)
341#define DIB3000MB_FIFO_ACTIVATE ( 0)
342
343#define DIB3000MB_REG_FIFO_146 ( 146)
344#define DIB3000MB_FIFO_146 ( 3)
345
346#define DIB3000MB_REG_FIFO_147 ( 147)
347#define DIB3000MB_FIFO_147 (0x0100)
348
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351
352
353
354
355
356#define DIB3000MB_REG_FIRST_PID ( 153)
357#define DIB3000MB_NUM_PIDS ( 16)
358
359
360
361
362
363
364#define DIB3000MB_REG_OUTPUT_MODE ( 169)
365#define DIB3000MB_OUTPUT_MODE_GATED_CLK ( 0)
366#define DIB3000MB_OUTPUT_MODE_CONT_CLK ( 1)
367#define DIB3000MB_OUTPUT_MODE_SERIAL ( 2)
368#define DIB3000MB_OUTPUT_MODE_DATA_DIVERSITY ( 5)
369#define DIB3000MB_OUTPUT_MODE_SLAVE ( 6)
370
371
372#define DIB3000MB_REG_IRQ_EVENT_MASK ( 170)
373#define DIB3000MB_IRQ_EVENT_MASK ( 0)
374
375
376static u16 dib3000mb_reg_filter_coeffs[] = {
377 171, 172, 173, 174, 175, 176, 177, 178,
378 179, 180, 181, 182, 183, 184, 185, 186,
379 188, 189, 190, 191, 192, 194
380};
381
382static u16 dib3000mb_filter_coeffs[] = {
383 226, 160, 29,
384 979, 998, 19,
385 22, 1019, 1006,
386 1022, 12, 6,
387 1017, 1017, 3,
388 6, 1019,
389 1021, 2, 3,
390 1, 0,
391};
392
393
394
395
396
397#define DIB3000MB_REG_MOBILE_ALGO ( 195)
398#define DIB3000MB_MOBILE_ALGO_ON ( 0)
399#define DIB3000MB_MOBILE_ALGO_OFF ( 1)
400
401
402#define DIB3000MB_REG_MULTI_DEMOD_MSB ( 206)
403#define DIB3000MB_REG_MULTI_DEMOD_LSB ( 207)
404
405
406#define DIB3000MB_MULTI_DEMOD_MSB ( 32767)
407#define DIB3000MB_MULTI_DEMOD_LSB ( 4095)
408
409
410#define DIB3000MB_REG_RESET_DEVICE ( 1024)
411#define DIB3000MB_RESET_DEVICE (0x812c)
412#define DIB3000MB_RESET_DEVICE_RST ( 0)
413
414
415#define DIB3000MB_REG_CLOCK ( 1027)
416#define DIB3000MB_CLOCK_DEFAULT (0x9000)
417#define DIB3000MB_CLOCK_DIVERSITY (0x92b0)
418
419
420#define DIB3000MB_REG_POWER_CONTROL ( 1028)
421#define DIB3000MB_POWER_DOWN ( 1)
422#define DIB3000MB_POWER_UP ( 0)
423
424
425#define DIB3000MB_REG_ELECT_OUT_MODE ( 1029)
426#define DIB3000MB_ELECT_OUT_MODE_OFF ( 0)
427#define DIB3000MB_ELECT_OUT_MODE_ON ( 1)
428
429
430#define DIB3000MB_REG_TUNER ( 1089)
431
432
433
434
435#define DIB3000MB_REG_AGC_LOCK ( 324)
436
437
438#define DIB3000MB_REG_AGC_POWER ( 325)
439
440
441#define DIB3000MB_REG_AGC1_VALUE ( 326)
442
443
444#define DIB3000MB_REG_AGC2_VALUE ( 327)
445
446
447#define DIB3000MB_REG_RF_POWER ( 328)
448
449
450#define DIB3000MB_REG_DDS_VALUE_MSB ( 339)
451#define DIB3000MB_REG_DDS_VALUE_LSB ( 340)
452
453
454#define DIB3000MB_REG_TIMING_OFFSET_MSB ( 341)
455#define DIB3000MB_REG_TIMING_OFFSET_LSB ( 342)
456
457
458#define DIB3000MB_REG_FFT_WINDOW_POS ( 353)
459
460
461#define DIB3000MB_REG_CARRIER_LOCK ( 355)
462
463
464#define DIB3000MB_REG_NOISE_POWER_MSB ( 372)
465#define DIB3000MB_REG_NOISE_POWER_LSB ( 373)
466
467#define DIB3000MB_REG_MOBILE_NOISE_MSB ( 374)
468#define DIB3000MB_REG_MOBILE_NOISE_LSB ( 375)
469
470
471
472
473
474#define DIB3000MB_REG_SIGNAL_POWER ( 380)
475
476
477#define DIB3000MB_REG_MER_MSB ( 381)
478#define DIB3000MB_REG_MER_LSB ( 382)
479
480
481
482
483
484
485
486
487#define DIB3000MB_REG_TPS_LOCK ( 394)
488
489
490#define DIB3000MB_REG_TPS_QAM ( 398)
491
492
493#define DIB3000MB_REG_TPS_HRCH ( 399)
494
495
496#define DIB3000MB_REG_TPS_VIT_ALPHA ( 400)
497
498
499#define DIB3000MB_REG_TPS_CODE_RATE_HP ( 401)
500
501
502#define DIB3000MB_REG_TPS_CODE_RATE_LP ( 402)
503
504
505#define DIB3000MB_REG_TPS_GUARD_TIME ( 403)
506
507
508#define DIB3000MB_REG_TPS_FFT ( 404)
509
510
511#define DIB3000MB_REG_TPS_CELL_ID ( 406)
512
513
514#define DIB3000MB_REG_TPS_1 ( 408)
515#define DIB3000MB_REG_TPS_2 ( 409)
516#define DIB3000MB_REG_TPS_3 ( 410)
517#define DIB3000MB_REG_TPS_4 ( 411)
518#define DIB3000MB_REG_TPS_5 ( 412)
519
520
521#define DIB3000MB_REG_BER_MSB ( 414)
522#define DIB3000MB_REG_BER_LSB ( 415)
523
524
525#define DIB3000MB_REG_PACKET_ERROR_RATE ( 417)
526
527
528#define DIB3000MB_REG_UNC ( 420)
529
530
531#define DIB3000MB_REG_VIT_LCK ( 421)
532
533
534#define DIB3000MB_REG_VIT_INDICATOR ( 422)
535
536
537#define DIB3000MB_REG_TS_SYNC_LOCK ( 423)
538
539
540#define DIB3000MB_REG_TS_RS_LOCK ( 424)
541
542
543#define DIB3000MB_REG_LOCK0_VALUE ( 425)
544
545
546#define DIB3000MB_REG_LOCK1_VALUE ( 426)
547
548
549#define DIB3000MB_REG_LOCK2_VALUE ( 427)
550
551
552#define DIB3000MB_REG_AS_IRQ_PENDING ( 434)
553
554#endif
555