LXR linux/drivers/media/platform/omap3isp/ispcsiphy.c

   1/*
   2 * ispcsiphy.c
   3 *
   4 * TI OMAP3 ISP - CSI PHY module
   5 *
   6 * Copyright (C) 2010 Nokia Corporation
   7 * Copyright (C) 2009 Texas Instruments, Inc.
   8 *
   9 * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  10 *           Sakari Ailus <sakari.ailus@iki.fi>
  11 *
  12 * This program is free software; you can redistribute it and/or modify
  13 * it under the terms of the GNU General Public License version 2 as
  14 * published by the Free Software Foundation.
  15 */
  16
  17#include <linux/delay.h>
  18#include <linux/device.h>
  19#include <linux/regmap.h>
  20#include <linux/regulator/consumer.h>
  21
  22#include "isp.h"
  23#include "ispreg.h"
  24#include "ispcsiphy.h"
  25
  26static void csiphy_routing_cfg_3630(struct isp_csiphy *phy,
  27                                    enum isp_interface_type iface,
  28                                    bool ccp2_strobe)
  29{
  30        u32 reg;
  31        u32 shift, mode;
  32
  33        regmap_read(phy->isp->syscon, phy->isp->syscon_offset, &reg);
  34
  35        switch (iface) {
  36        default:
  37        /* Should not happen in practice, but let's keep the compiler happy. */
  38        case ISP_INTERFACE_CCP2B_PHY1:
  39                reg &= ~OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
  40                shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT;
  41                break;
  42        case ISP_INTERFACE_CSI2C_PHY1:
  43                shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY1_SHIFT;
  44                mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY;
  45                break;
  46        case ISP_INTERFACE_CCP2B_PHY2:
  47                reg |= OMAP3630_CONTROL_CAMERA_PHY_CTRL_CSI1_RX_SEL_PHY2;
  48                shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT;
  49                break;
  50        case ISP_INTERFACE_CSI2A_PHY2:
  51                shift = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_PHY2_SHIFT;
  52                mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_DPHY;
  53                break;
  54        }
  55
  56        /* Select data/clock or data/strobe mode for CCP2 */
  57        if (iface == ISP_INTERFACE_CCP2B_PHY1 ||
  58            iface == ISP_INTERFACE_CCP2B_PHY2) {
  59                if (ccp2_strobe)
  60                        mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_STROBE;
  61                else
  62                        mode = OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_CCP2_DATA_CLOCK;
  63        }
  64
  65        reg &= ~(OMAP3630_CONTROL_CAMERA_PHY_CTRL_CAMMODE_MASK << shift);
  66        reg |= mode << shift;
  67
  68        regmap_write(phy->isp->syscon, phy->isp->syscon_offset, reg);
  69}
  70
  71static void csiphy_routing_cfg_3430(struct isp_csiphy *phy, u32 iface, bool on,
  72                                    bool ccp2_strobe)
  73{
  74        u32 csirxfe = OMAP343X_CONTROL_CSIRXFE_PWRDNZ
  75                | OMAP343X_CONTROL_CSIRXFE_RESET;
  76
  77        /* Only the CCP2B on PHY1 is configurable. */
  78        if (iface != ISP_INTERFACE_CCP2B_PHY1)
  79                return;
  80
  81        if (!on) {
  82                regmap_write(phy->isp->syscon, phy->isp->syscon_offset, 0);
  83                return;
  84        }
  85
  86        if (ccp2_strobe)
  87                csirxfe |= OMAP343X_CONTROL_CSIRXFE_SELFORM;
  88
  89        regmap_write(phy->isp->syscon, phy->isp->syscon_offset, csirxfe);
  90}
  91
  92/*
  93 * Configure OMAP 3 CSI PHY routing.
  94 * @phy: relevant phy device
  95 * @iface: ISP_INTERFACE_*
  96 * @on: power on or off
  97 * @ccp2_strobe: false: data/clock, true: data/strobe
  98 *
  99 * Note that the underlying routing configuration registers are part of the
 100 * control (SCM) register space and part of the CORE power domain on both 3430
 101 * and 3630, so they will not hold their contents in off-mode. This isn't an
 102 * issue since the MPU power domain is forced on whilst the ISP is in use.
 103 */
 104static void csiphy_routing_cfg(struct isp_csiphy *phy,
 105                               enum isp_interface_type iface, bool on,
 106                               bool ccp2_strobe)
 107{
 108        if (phy->isp->phy_type == ISP_PHY_TYPE_3630 && on)
 109                return csiphy_routing_cfg_3630(phy, iface, ccp2_strobe);
 110        if (phy->isp->phy_type == ISP_PHY_TYPE_3430)
 111                return csiphy_routing_cfg_3430(phy, iface, on, ccp2_strobe);
 112}
 113
 114/*
 115 * csiphy_power_autoswitch_enable
 116 * @enable: Sets or clears the autoswitch function enable flag.
 117 */
 118static void csiphy_power_autoswitch_enable(struct isp_csiphy *phy, bool enable)
 119{
 120        isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
 121                        ISPCSI2_PHY_CFG_PWR_AUTO,
 122                        enable ? ISPCSI2_PHY_CFG_PWR_AUTO : 0);
 123}
 124
 125/*
 126 * csiphy_set_power
 127 * @power: Power state to be set.
 128 *
 129 * Returns 0 if successful, or -EBUSY if the retry count is exceeded.
 130 */
 131static int csiphy_set_power(struct isp_csiphy *phy, u32 power)
 132{
 133        u32 reg;
 134        u8 retry_count;
 135
 136        isp_reg_clr_set(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG,
 137                        ISPCSI2_PHY_CFG_PWR_CMD_MASK, power);
 138
 139        retry_count = 0;
 140        do {
 141                udelay(50);
 142                reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG) &
 143                                    ISPCSI2_PHY_CFG_PWR_STATUS_MASK;
 144
 145                if (reg != power >> 2)
 146                        retry_count++;
 147
 148        } while ((reg != power >> 2) && (retry_count < 100));
 149
 150        if (retry_count == 100) {
 151                dev_err(phy->isp->dev, "CSI2 CIO set power failed!\n");
 152                return -EBUSY;
 153        }
 154
 155        return 0;
 156}
 157
 158/*
 159 * TCLK values are OK at their reset values
 160 */
 161#define TCLK_TERM       0
 162#define TCLK_MISS       1
 163#define TCLK_SETTLE     14
 164
 165static int omap3isp_csiphy_config(struct isp_csiphy *phy)
 166{
 167        struct isp_pipeline *pipe = to_isp_pipeline(phy->entity);
 168        struct isp_bus_cfg *buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
 169        struct isp_csiphy_lanes_cfg *lanes;
 170        int csi2_ddrclk_khz;
 171        unsigned int num_data_lanes, used_lanes = 0;
 172        unsigned int i;
 173        u32 reg;
 174
 175        if (buscfg->interface == ISP_INTERFACE_CCP2B_PHY1
 176            || buscfg->interface == ISP_INTERFACE_CCP2B_PHY2) {
 177                lanes = &buscfg->bus.ccp2.lanecfg;
 178                num_data_lanes = 1;
 179        } else {
 180                lanes = &buscfg->bus.csi2.lanecfg;
 181                num_data_lanes = buscfg->bus.csi2.num_data_lanes;
 182        }
 183
 184        if (num_data_lanes > phy->num_data_lanes)
 185                return -EINVAL;
 186
 187        /* Clock and data lanes verification */
 188        for (i = 0; i < num_data_lanes; i++) {
 189                if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3)
 190                        return -EINVAL;
 191
 192                if (used_lanes & (1 << lanes->data[i].pos))
 193                        return -EINVAL;
 194
 195                used_lanes |= 1 << lanes->data[i].pos;
 196        }
 197
 198        if (lanes->clk.pol > 1 || lanes->clk.pos > 3)
 199                return -EINVAL;
 200
 201        if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos))
 202                return -EINVAL;
 203
 204        /*
 205         * The PHY configuration is lost in off mode, that's not an
 206         * issue since the MPU power domain is forced on whilst the
 207         * ISP is in use.
 208         */
 209        csiphy_routing_cfg(phy, buscfg->interface, true,
 210                           buscfg->bus.ccp2.phy_layer);
 211
 212        /* DPHY timing configuration */
 213        /* CSI-2 is DDR and we only count used lanes. */
 214        csi2_ddrclk_khz = pipe->external_rate / 1000
 215                / (2 * hweight32(used_lanes)) * pipe->external_width;
 216
 217        reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG0);
 218
 219        reg &= ~(ISPCSIPHY_REG0_THS_TERM_MASK |
 220                 ISPCSIPHY_REG0_THS_SETTLE_MASK);
 221        /* THS_TERM: Programmed value = ceil(12.5 ns/DDRClk period) - 1. */
 222        reg |= (DIV_ROUND_UP(25 * csi2_ddrclk_khz, 2000000) - 1)
 223                << ISPCSIPHY_REG0_THS_TERM_SHIFT;
 224        /* THS_SETTLE: Programmed value = ceil(90 ns/DDRClk period) + 3. */
 225        reg |= (DIV_ROUND_UP(90 * csi2_ddrclk_khz, 1000000) + 3)
 226                << ISPCSIPHY_REG0_THS_SETTLE_SHIFT;
 227
 228        isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG0);
 229
 230        reg = isp_reg_readl(phy->isp, phy->phy_regs, ISPCSIPHY_REG1);
 231
 232        reg &= ~(ISPCSIPHY_REG1_TCLK_TERM_MASK |
 233                 ISPCSIPHY_REG1_TCLK_MISS_MASK |
 234                 ISPCSIPHY_REG1_TCLK_SETTLE_MASK);
 235        reg |= TCLK_TERM << ISPCSIPHY_REG1_TCLK_TERM_SHIFT;
 236        reg |= TCLK_MISS << ISPCSIPHY_REG1_TCLK_MISS_SHIFT;
 237        reg |= TCLK_SETTLE << ISPCSIPHY_REG1_TCLK_SETTLE_SHIFT;
 238
 239        isp_reg_writel(phy->isp, reg, phy->phy_regs, ISPCSIPHY_REG1);
 240
 241        /* DPHY lane configuration */
 242        reg = isp_reg_readl(phy->isp, phy->cfg_regs, ISPCSI2_PHY_CFG);
 243
 244        for (i = 0; i < num_data_lanes; i++) {
 245                reg &= ~(ISPCSI2_PHY_CFG_DATA_POL_MASK(i + 1) |
 246                         ISPCSI2_PHY_CFG_DATA_POSITION_MASK(i + 1));
 247                reg |= (lanes->data[i].pol <<
 248                        ISPCSI2_PHY_CFG_DATA_POL_SHIFT(i + 1));
 249                reg |= (lanes->data[i].pos <<
 250                        ISPCSI2_PHY_CFG_DATA_POSITION_SHIFT(i + 1));
 251        }
 252
 253        reg &= ~(ISPCSI2_PHY_CFG_CLOCK_POL_MASK |
 254                 ISPCSI2_PHY_CFG_CLOCK_POSITION_MASK);
 255        reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT;
 256        reg |= lanes->clk.pos << ISPCSI2_PHY_CFG_CLOCK_POSITION_SHIFT;
 257
 258        isp_reg_writel(phy->isp, reg, phy->cfg_regs, ISPCSI2_PHY_CFG);
 259
 260        return 0;
 261}
 262
 263int omap3isp_csiphy_acquire(struct isp_csiphy *phy, struct media_entity *entity)
 264{
 265        int rval;
 266
 267        if (phy->vdd == NULL) {
 268                dev_err(phy->isp->dev,
 269                        "Power regulator for CSI PHY not available\n");
 270                return -ENODEV;
 271        }
 272
 273        mutex_lock(&phy->mutex);
 274
 275        rval = regulator_enable(phy->vdd);
 276        if (rval < 0)
 277                goto done;
 278
 279        rval = omap3isp_csi2_reset(phy->csi2);
 280        if (rval < 0)
 281                goto done;
 282
 283        phy->entity = entity;
 284
 285        rval = omap3isp_csiphy_config(phy);
 286        if (rval < 0)
 287                goto done;
 288
 289        if (phy->isp->revision == ISP_REVISION_15_0) {
 290                rval = csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_ON);
 291                if (rval) {
 292                        regulator_disable(phy->vdd);
 293                        goto done;
 294                }
 295
 296                csiphy_power_autoswitch_enable(phy, true);
 297        }
 298done:
 299        if (rval < 0)
 300                phy->entity = NULL;
 301
 302        mutex_unlock(&phy->mutex);
 303        return rval;
 304}
 305
 306void omap3isp_csiphy_release(struct isp_csiphy *phy)
 307{
 308        mutex_lock(&phy->mutex);
 309        if (phy->entity) {
 310                struct isp_pipeline *pipe = to_isp_pipeline(phy->entity);
 311                struct isp_bus_cfg *buscfg =
 312                        v4l2_subdev_to_bus_cfg(pipe->external);
 313
 314                csiphy_routing_cfg(phy, buscfg->interface, false,
 315                                   buscfg->bus.ccp2.phy_layer);
 316                if (phy->isp->revision == ISP_REVISION_15_0) {
 317                        csiphy_power_autoswitch_enable(phy, false);
 318                        csiphy_set_power(phy, ISPCSI2_PHY_CFG_PWR_CMD_OFF);
 319                }
 320                regulator_disable(phy->vdd);
 321                phy->entity = NULL;
 322        }
 323        mutex_unlock(&phy->mutex);
 324}
 325
 326/*
 327 * omap3isp_csiphy_init - Initialize the CSI PHY frontends
 328 */
 329int omap3isp_csiphy_init(struct isp_device *isp)
 330{
 331        struct isp_csiphy *phy1 = &isp->isp_csiphy1;
 332        struct isp_csiphy *phy2 = &isp->isp_csiphy2;
 333
 334        phy2->isp = isp;
 335        phy2->csi2 = &isp->isp_csi2a;
 336        phy2->num_data_lanes = ISP_CSIPHY2_NUM_DATA_LANES;
 337        phy2->cfg_regs = OMAP3_ISP_IOMEM_CSI2A_REGS1;
 338        phy2->phy_regs = OMAP3_ISP_IOMEM_CSIPHY2;
 339        mutex_init(&phy2->mutex);
 340
 341        phy1->isp = isp;
 342        mutex_init(&phy1->mutex);
 343
 344        if (isp->revision == ISP_REVISION_15_0) {
 345                phy1->csi2 = &isp->isp_csi2c;
 346                phy1->num_data_lanes = ISP_CSIPHY1_NUM_DATA_LANES;
 347                phy1->cfg_regs = OMAP3_ISP_IOMEM_CSI2C_REGS1;
 348                phy1->phy_regs = OMAP3_ISP_IOMEM_CSIPHY1;
 349        }
 350
 351        return 0;
 352}
 353
 354void omap3isp_csiphy_cleanup(struct isp_device *isp)
 355{
 356        mutex_destroy(&isp->isp_csiphy1.mutex);
 357        mutex_destroy(&isp->isp_csiphy2.mutex);
 358}
 359