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21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/ioport.h>
28#include <linux/spinlock.h>
29#include <linux/dma-mapping.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34#include <linux/io.h>
35#include <linux/clk.h>
36#include <linux/clk-provider.h>
37#include <linux/regulator/consumer.h>
38#include <linux/reset.h>
39#include <linux/interrupt.h>
40#include <linux/bitfield.h>
41#include <linux/pinctrl/consumer.h>
42
43#define DRIVER_NAME "meson-gx-mmc"
44
45#define SD_EMMC_CLOCK 0x0
46#define CLK_DIV_MASK GENMASK(5, 0)
47#define CLK_SRC_MASK GENMASK(7, 6)
48#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
49#define CLK_TX_PHASE_MASK GENMASK(11, 10)
50#define CLK_RX_PHASE_MASK GENMASK(13, 12)
51#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
52#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
53#define CLK_V2_ALWAYS_ON BIT(24)
54
55#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
56#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
57#define CLK_V3_ALWAYS_ON BIT(28)
58
59#define CLK_DELAY_STEP_PS 200
60#define CLK_PHASE_STEP 30
61#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
62
63#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
64#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
65#define CLK_ALWAYS_ON(h) (h->data->always_on)
66
67#define SD_EMMC_DELAY 0x4
68#define SD_EMMC_ADJUST 0x8
69
70#define SD_EMMC_DELAY1 0x4
71#define SD_EMMC_DELAY2 0x8
72#define SD_EMMC_V3_ADJUST 0xc
73
74#define SD_EMMC_CALOUT 0x10
75#define SD_EMMC_START 0x40
76#define START_DESC_INIT BIT(0)
77#define START_DESC_BUSY BIT(1)
78#define START_DESC_ADDR_MASK GENMASK(31, 2)
79
80#define SD_EMMC_CFG 0x44
81#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
82#define CFG_BUS_WIDTH_1 0x0
83#define CFG_BUS_WIDTH_4 0x1
84#define CFG_BUS_WIDTH_8 0x2
85#define CFG_DDR BIT(2)
86#define CFG_BLK_LEN_MASK GENMASK(7, 4)
87#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
88#define CFG_RC_CC_MASK GENMASK(15, 12)
89#define CFG_STOP_CLOCK BIT(22)
90#define CFG_CLK_ALWAYS_ON BIT(18)
91#define CFG_CHK_DS BIT(20)
92#define CFG_AUTO_CLK BIT(23)
93
94#define SD_EMMC_STATUS 0x48
95#define STATUS_BUSY BIT(31)
96#define STATUS_DATI GENMASK(23, 16)
97
98#define SD_EMMC_IRQ_EN 0x4c
99#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
100#define IRQ_TXD_ERR BIT(8)
101#define IRQ_DESC_ERR BIT(9)
102#define IRQ_RESP_ERR BIT(10)
103#define IRQ_CRC_ERR \
104 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
105#define IRQ_RESP_TIMEOUT BIT(11)
106#define IRQ_DESC_TIMEOUT BIT(12)
107#define IRQ_TIMEOUTS \
108 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
109#define IRQ_END_OF_CHAIN BIT(13)
110#define IRQ_RESP_STATUS BIT(14)
111#define IRQ_SDIO BIT(15)
112#define IRQ_EN_MASK \
113 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
114 IRQ_SDIO)
115
116#define SD_EMMC_CMD_CFG 0x50
117#define SD_EMMC_CMD_ARG 0x54
118#define SD_EMMC_CMD_DAT 0x58
119#define SD_EMMC_CMD_RSP 0x5c
120#define SD_EMMC_CMD_RSP1 0x60
121#define SD_EMMC_CMD_RSP2 0x64
122#define SD_EMMC_CMD_RSP3 0x68
123
124#define SD_EMMC_RXD 0x94
125#define SD_EMMC_TXD 0x94
126#define SD_EMMC_LAST_REG SD_EMMC_TXD
127
128#define SD_EMMC_CFG_BLK_SIZE 512
129#define SD_EMMC_CFG_RESP_TIMEOUT 256
130#define SD_EMMC_CMD_TIMEOUT 1024
131#define SD_EMMC_CMD_TIMEOUT_DATA 4096
132#define SD_EMMC_CFG_CMD_GAP 16
133#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
134
135#define SD_EMMC_PRE_REQ_DONE BIT(0)
136#define SD_EMMC_DESC_CHAIN_MODE BIT(1)
137
138#define MUX_CLK_NUM_PARENTS 2
139
140struct meson_mmc_data {
141 unsigned int tx_delay_mask;
142 unsigned int rx_delay_mask;
143 unsigned int always_on;
144};
145
146struct sd_emmc_desc {
147 u32 cmd_cfg;
148 u32 cmd_arg;
149 u32 cmd_data;
150 u32 cmd_resp;
151};
152
153struct meson_host {
154 struct device *dev;
155 struct meson_mmc_data *data;
156 struct mmc_host *mmc;
157 struct mmc_command *cmd;
158
159 spinlock_t lock;
160 void __iomem *regs;
161 struct clk *core_clk;
162 struct clk *mmc_clk;
163 struct clk *rx_clk;
164 struct clk *tx_clk;
165 unsigned long req_rate;
166
167 struct pinctrl *pinctrl;
168 struct pinctrl_state *pins_default;
169 struct pinctrl_state *pins_clk_gate;
170
171 unsigned int bounce_buf_size;
172 void *bounce_buf;
173 dma_addr_t bounce_dma_addr;
174 struct sd_emmc_desc *descs;
175 dma_addr_t descs_dma_addr;
176
177 bool vqmmc_enabled;
178};
179
180#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
181#define CMD_CFG_BLOCK_MODE BIT(9)
182#define CMD_CFG_R1B BIT(10)
183#define CMD_CFG_END_OF_CHAIN BIT(11)
184#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
185#define CMD_CFG_NO_RESP BIT(16)
186#define CMD_CFG_NO_CMD BIT(17)
187#define CMD_CFG_DATA_IO BIT(18)
188#define CMD_CFG_DATA_WR BIT(19)
189#define CMD_CFG_RESP_NOCRC BIT(20)
190#define CMD_CFG_RESP_128 BIT(21)
191#define CMD_CFG_RESP_NUM BIT(22)
192#define CMD_CFG_DATA_NUM BIT(23)
193#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
194#define CMD_CFG_ERROR BIT(30)
195#define CMD_CFG_OWNER BIT(31)
196
197#define CMD_DATA_MASK GENMASK(31, 2)
198#define CMD_DATA_BIG_ENDIAN BIT(1)
199#define CMD_DATA_SRAM BIT(0)
200#define CMD_RESP_MASK GENMASK(31, 1)
201#define CMD_RESP_SRAM BIT(0)
202
203struct meson_mmc_phase {
204 struct clk_hw hw;
205 void __iomem *reg;
206 unsigned long phase_mask;
207 unsigned long delay_mask;
208 unsigned int delay_step_ps;
209};
210
211#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
212
213static int meson_mmc_clk_get_phase(struct clk_hw *hw)
214{
215 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
216 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
217 unsigned long period_ps, p, d;
218 int degrees;
219 u32 val;
220
221 val = readl(mmc->reg);
222 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
223 degrees = p * 360 / phase_num;
224
225 if (mmc->delay_mask) {
226 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
227 clk_get_rate(hw->clk));
228 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
229 degrees += d * mmc->delay_step_ps * 360 / period_ps;
230 degrees %= 360;
231 }
232
233 return degrees;
234}
235
236static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
237 unsigned int phase,
238 unsigned int delay)
239{
240 u32 val;
241
242 val = readl(mmc->reg);
243 val &= ~mmc->phase_mask;
244 val |= phase << __ffs(mmc->phase_mask);
245
246 if (mmc->delay_mask) {
247 val &= ~mmc->delay_mask;
248 val |= delay << __ffs(mmc->delay_mask);
249 }
250
251 writel(val, mmc->reg);
252}
253
254static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
255{
256 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
257 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
258 unsigned long period_ps, d = 0, r;
259 uint64_t p;
260
261 p = degrees % 360;
262
263 if (!mmc->delay_mask) {
264 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
265 } else {
266 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
267 clk_get_rate(hw->clk));
268
269
270
271
272 r = do_div(p, 360 / phase_num);
273 d = DIV_ROUND_CLOSEST(r * period_ps,
274 360 * mmc->delay_step_ps);
275 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
276 }
277
278 meson_mmc_apply_phase_delay(mmc, p, d);
279 return 0;
280}
281
282static const struct clk_ops meson_mmc_clk_phase_ops = {
283 .get_phase = meson_mmc_clk_get_phase,
284 .set_phase = meson_mmc_clk_set_phase,
285};
286
287static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
288{
289 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
290
291 if (!timeout)
292 return SD_EMMC_CMD_TIMEOUT_DATA;
293
294 timeout = roundup_pow_of_two(timeout);
295
296 return min(timeout, 32768U);
297}
298
299static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
300{
301 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
302 return cmd->mrq->cmd;
303 else if (mmc_op_multi(cmd->opcode) &&
304 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
305 return cmd->mrq->stop;
306 else
307 return NULL;
308}
309
310static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
311 struct mmc_request *mrq)
312{
313 struct mmc_data *data = mrq->data;
314 struct scatterlist *sg;
315 int i;
316 bool use_desc_chain_mode = true;
317
318
319
320
321
322
323
324 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
325 return;
326
327 for_each_sg(data->sg, sg, data->sg_len, i)
328
329 if (sg->offset & 7) {
330 WARN_ONCE(1, "unaligned scatterlist buffer\n");
331 use_desc_chain_mode = false;
332 break;
333 }
334
335 if (use_desc_chain_mode)
336 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
337}
338
339static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
340{
341 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
342}
343
344static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
345{
346 return data && data->flags & MMC_DATA_READ &&
347 !meson_mmc_desc_chain_mode(data);
348}
349
350static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
351{
352 struct mmc_data *data = mrq->data;
353
354 if (!data)
355 return;
356
357 meson_mmc_get_transfer_mode(mmc, mrq);
358 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
359
360 if (!meson_mmc_desc_chain_mode(data))
361 return;
362
363 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
364 mmc_get_dma_dir(data));
365 if (!data->sg_count)
366 dev_err(mmc_dev(mmc), "dma_map_sg failed");
367}
368
369static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
370 int err)
371{
372 struct mmc_data *data = mrq->data;
373
374 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
375 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
376 mmc_get_dma_dir(data));
377}
378
379static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
380{
381 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
382 ios->timing == MMC_TIMING_UHS_DDR50 ||
383 ios->timing == MMC_TIMING_MMC_HS400)
384 return true;
385
386 return false;
387}
388
389
390
391
392
393
394
395static void meson_mmc_clk_gate(struct meson_host *host)
396{
397 u32 cfg;
398
399 if (host->pins_clk_gate) {
400 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
401 } else {
402
403
404
405
406 cfg = readl(host->regs + SD_EMMC_CFG);
407 cfg |= CFG_STOP_CLOCK;
408 writel(cfg, host->regs + SD_EMMC_CFG);
409 }
410}
411
412static void meson_mmc_clk_ungate(struct meson_host *host)
413{
414 u32 cfg;
415
416 if (host->pins_clk_gate)
417 pinctrl_select_state(host->pinctrl, host->pins_default);
418
419
420 cfg = readl(host->regs + SD_EMMC_CFG);
421 cfg &= ~CFG_STOP_CLOCK;
422 writel(cfg, host->regs + SD_EMMC_CFG);
423}
424
425static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
426{
427 struct mmc_host *mmc = host->mmc;
428 unsigned long rate = ios->clock;
429 int ret;
430 u32 cfg;
431
432
433 if (meson_mmc_timing_is_ddr(ios))
434 rate <<= 1;
435
436
437 if (host->req_rate == rate)
438 return 0;
439
440
441 meson_mmc_clk_gate(host);
442 host->req_rate = 0;
443
444 if (!rate) {
445 mmc->actual_clock = 0;
446
447 return 0;
448 }
449
450
451 cfg = readl(host->regs + SD_EMMC_CFG);
452 cfg |= CFG_STOP_CLOCK;
453 writel(cfg, host->regs + SD_EMMC_CFG);
454
455 ret = clk_set_rate(host->mmc_clk, rate);
456 if (ret) {
457 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
458 rate, ret);
459 return ret;
460 }
461
462 host->req_rate = rate;
463 mmc->actual_clock = clk_get_rate(host->mmc_clk);
464
465
466 if (meson_mmc_timing_is_ddr(ios))
467 mmc->actual_clock >>= 1;
468
469 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
470 if (ios->clock != mmc->actual_clock)
471 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
472
473
474 meson_mmc_clk_ungate(host);
475
476 return 0;
477}
478
479
480
481
482
483
484static int meson_mmc_clk_init(struct meson_host *host)
485{
486 struct clk_init_data init;
487 struct clk_mux *mux;
488 struct clk_divider *div;
489 struct meson_mmc_phase *core, *tx, *rx;
490 struct clk *clk;
491 char clk_name[32];
492 int i, ret = 0;
493 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
494 const char *clk_parent[1];
495 u32 clk_reg;
496
497
498 clk_reg = 0;
499 clk_reg |= CLK_ALWAYS_ON(host);
500 clk_reg |= CLK_DIV_MASK;
501 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
502
503
504 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
505 struct clk *clk;
506 char name[16];
507
508 snprintf(name, sizeof(name), "clkin%d", i);
509 clk = devm_clk_get(host->dev, name);
510 if (IS_ERR(clk)) {
511 if (clk != ERR_PTR(-EPROBE_DEFER))
512 dev_err(host->dev, "Missing clock %s\n", name);
513 return PTR_ERR(clk);
514 }
515
516 mux_parent_names[i] = __clk_get_name(clk);
517 }
518
519
520 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
521 if (!mux)
522 return -ENOMEM;
523
524 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
525 init.name = clk_name;
526 init.ops = &clk_mux_ops;
527 init.flags = 0;
528 init.parent_names = mux_parent_names;
529 init.num_parents = MUX_CLK_NUM_PARENTS;
530
531 mux->reg = host->regs + SD_EMMC_CLOCK;
532 mux->shift = __ffs(CLK_SRC_MASK);
533 mux->mask = CLK_SRC_MASK >> mux->shift;
534 mux->hw.init = &init;
535
536 clk = devm_clk_register(host->dev, &mux->hw);
537 if (WARN_ON(IS_ERR(clk)))
538 return PTR_ERR(clk);
539
540
541 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
542 if (!div)
543 return -ENOMEM;
544
545 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
546 init.name = clk_name;
547 init.ops = &clk_divider_ops;
548 init.flags = CLK_SET_RATE_PARENT;
549 clk_parent[0] = __clk_get_name(clk);
550 init.parent_names = clk_parent;
551 init.num_parents = 1;
552
553 div->reg = host->regs + SD_EMMC_CLOCK;
554 div->shift = __ffs(CLK_DIV_MASK);
555 div->width = __builtin_popcountl(CLK_DIV_MASK);
556 div->hw.init = &init;
557 div->flags = CLK_DIVIDER_ONE_BASED;
558
559 clk = devm_clk_register(host->dev, &div->hw);
560 if (WARN_ON(IS_ERR(clk)))
561 return PTR_ERR(clk);
562
563
564 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
565 if (!core)
566 return -ENOMEM;
567
568 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
569 init.name = clk_name;
570 init.ops = &meson_mmc_clk_phase_ops;
571 init.flags = CLK_SET_RATE_PARENT;
572 clk_parent[0] = __clk_get_name(clk);
573 init.parent_names = clk_parent;
574 init.num_parents = 1;
575
576 core->reg = host->regs + SD_EMMC_CLOCK;
577 core->phase_mask = CLK_CORE_PHASE_MASK;
578 core->hw.init = &init;
579
580 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
581 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
582 return PTR_ERR(host->mmc_clk);
583
584
585 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
586 if (!tx)
587 return -ENOMEM;
588
589 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
590 init.name = clk_name;
591 init.ops = &meson_mmc_clk_phase_ops;
592 init.flags = 0;
593 clk_parent[0] = __clk_get_name(host->mmc_clk);
594 init.parent_names = clk_parent;
595 init.num_parents = 1;
596
597 tx->reg = host->regs + SD_EMMC_CLOCK;
598 tx->phase_mask = CLK_TX_PHASE_MASK;
599 tx->delay_mask = CLK_TX_DELAY_MASK(host);
600 tx->delay_step_ps = CLK_DELAY_STEP_PS;
601 tx->hw.init = &init;
602
603 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
604 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
605 return PTR_ERR(host->tx_clk);
606
607
608 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
609 if (!rx)
610 return -ENOMEM;
611
612 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
613 init.name = clk_name;
614 init.ops = &meson_mmc_clk_phase_ops;
615 init.flags = 0;
616 clk_parent[0] = __clk_get_name(host->mmc_clk);
617 init.parent_names = clk_parent;
618 init.num_parents = 1;
619
620 rx->reg = host->regs + SD_EMMC_CLOCK;
621 rx->phase_mask = CLK_RX_PHASE_MASK;
622 rx->delay_mask = CLK_RX_DELAY_MASK(host);
623 rx->delay_step_ps = CLK_DELAY_STEP_PS;
624 rx->hw.init = &init;
625
626 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
627 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
628 return PTR_ERR(host->rx_clk);
629
630
631 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
632 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
633 if (ret)
634 return ret;
635
636
637
638
639
640
641
642 clk_set_phase(host->mmc_clk, 180);
643 clk_set_phase(host->tx_clk, 270);
644 clk_set_phase(host->rx_clk, 0);
645
646 return clk_prepare_enable(host->mmc_clk);
647}
648
649static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
650{
651 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
652 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
653
654
655
656
657
658 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
659 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
660 CLK_PHASE_POINT_NUM);
661 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
662}
663
664static void meson_mmc_find_next_region(unsigned long *map,
665 unsigned long *start,
666 unsigned long *stop)
667{
668 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
669 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
670}
671
672static int meson_mmc_find_tuning_point(unsigned long *test)
673{
674 unsigned long shift, stop, offset = 0, start = 0, size = 0;
675
676
677 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
678 return 0;
679 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
680 return -EIO;
681
682
683
684
685
686 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
687 if (shift != 0)
688 meson_mmc_shift_map(test, shift);
689
690 while (start < CLK_PHASE_POINT_NUM) {
691 meson_mmc_find_next_region(test, &start, &stop);
692
693 if ((stop - start) > size) {
694 offset = start;
695 size = stop - start;
696 }
697
698 start = stop;
699 }
700
701
702 offset += (size / 2);
703
704
705 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
706
707 return offset;
708}
709
710static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
711 struct clk *clk)
712{
713 int point, ret;
714 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
715
716 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
717 __clk_get_name(clk));
718 bitmap_zero(test, CLK_PHASE_POINT_NUM);
719
720
721 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
722 clk_set_phase(clk, point * CLK_PHASE_STEP);
723 ret = mmc_send_tuning(mmc, opcode, NULL);
724 if (!ret)
725 set_bit(point, test);
726 }
727
728
729 point = meson_mmc_find_tuning_point(test);
730 if (point < 0)
731 return point;
732
733 clk_set_phase(clk, point * CLK_PHASE_STEP);
734 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
735 clk_get_phase(clk));
736 return 0;
737}
738
739static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
740{
741 struct meson_host *host = mmc_priv(mmc);
742
743 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
744}
745
746static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
747{
748 struct meson_host *host = mmc_priv(mmc);
749 u32 bus_width, val;
750 int err;
751
752
753
754
755
756 switch (ios->power_mode) {
757 case MMC_POWER_OFF:
758 if (!IS_ERR(mmc->supply.vmmc))
759 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
760
761 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
762 regulator_disable(mmc->supply.vqmmc);
763 host->vqmmc_enabled = false;
764 }
765
766 break;
767
768 case MMC_POWER_UP:
769 if (!IS_ERR(mmc->supply.vmmc))
770 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
771
772
773 clk_set_phase(host->rx_clk, 0);
774
775 break;
776
777 case MMC_POWER_ON:
778 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
779 int ret = regulator_enable(mmc->supply.vqmmc);
780
781 if (ret < 0)
782 dev_err(host->dev,
783 "failed to enable vqmmc regulator\n");
784 else
785 host->vqmmc_enabled = true;
786 }
787
788 break;
789 }
790
791
792 switch (ios->bus_width) {
793 case MMC_BUS_WIDTH_1:
794 bus_width = CFG_BUS_WIDTH_1;
795 break;
796 case MMC_BUS_WIDTH_4:
797 bus_width = CFG_BUS_WIDTH_4;
798 break;
799 case MMC_BUS_WIDTH_8:
800 bus_width = CFG_BUS_WIDTH_8;
801 break;
802 default:
803 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
804 ios->bus_width);
805 bus_width = CFG_BUS_WIDTH_4;
806 }
807
808 val = readl(host->regs + SD_EMMC_CFG);
809 val &= ~CFG_BUS_WIDTH_MASK;
810 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
811
812 val &= ~CFG_DDR;
813 if (meson_mmc_timing_is_ddr(ios))
814 val |= CFG_DDR;
815
816 val &= ~CFG_CHK_DS;
817 if (ios->timing == MMC_TIMING_MMC_HS400)
818 val |= CFG_CHK_DS;
819
820 err = meson_mmc_clk_set(host, ios);
821 if (err)
822 dev_err(host->dev, "Failed to set clock: %d\n,", err);
823
824 writel(val, host->regs + SD_EMMC_CFG);
825 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
826}
827
828static void meson_mmc_request_done(struct mmc_host *mmc,
829 struct mmc_request *mrq)
830{
831 struct meson_host *host = mmc_priv(mmc);
832
833 host->cmd = NULL;
834 mmc_request_done(host->mmc, mrq);
835}
836
837static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
838{
839 struct meson_host *host = mmc_priv(mmc);
840 u32 cfg, blksz_old;
841
842 cfg = readl(host->regs + SD_EMMC_CFG);
843 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
844
845 if (!is_power_of_2(blksz))
846 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
847
848 blksz = ilog2(blksz);
849
850
851 if (blksz == blksz_old)
852 return;
853
854 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
855 blksz_old, blksz);
856
857 cfg &= ~CFG_BLK_LEN_MASK;
858 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
859 writel(cfg, host->regs + SD_EMMC_CFG);
860}
861
862static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
863{
864 if (cmd->flags & MMC_RSP_PRESENT) {
865 if (cmd->flags & MMC_RSP_136)
866 *cmd_cfg |= CMD_CFG_RESP_128;
867 *cmd_cfg |= CMD_CFG_RESP_NUM;
868
869 if (!(cmd->flags & MMC_RSP_CRC))
870 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
871
872 if (cmd->flags & MMC_RSP_BUSY)
873 *cmd_cfg |= CMD_CFG_R1B;
874 } else {
875 *cmd_cfg |= CMD_CFG_NO_RESP;
876 }
877}
878
879static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
880{
881 struct meson_host *host = mmc_priv(mmc);
882 struct sd_emmc_desc *desc = host->descs;
883 struct mmc_data *data = host->cmd->data;
884 struct scatterlist *sg;
885 u32 start;
886 int i;
887
888 if (data->flags & MMC_DATA_WRITE)
889 cmd_cfg |= CMD_CFG_DATA_WR;
890
891 if (data->blocks > 1) {
892 cmd_cfg |= CMD_CFG_BLOCK_MODE;
893 meson_mmc_set_blksz(mmc, data->blksz);
894 }
895
896 for_each_sg(data->sg, sg, data->sg_count, i) {
897 unsigned int len = sg_dma_len(sg);
898
899 if (data->blocks > 1)
900 len /= data->blksz;
901
902 desc[i].cmd_cfg = cmd_cfg;
903 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
904 if (i > 0)
905 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
906 desc[i].cmd_arg = host->cmd->arg;
907 desc[i].cmd_resp = 0;
908 desc[i].cmd_data = sg_dma_address(sg);
909 }
910 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
911
912 dma_wmb();
913 start = host->descs_dma_addr | START_DESC_BUSY;
914 writel(start, host->regs + SD_EMMC_START);
915}
916
917static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
918{
919 struct meson_host *host = mmc_priv(mmc);
920 struct mmc_data *data = cmd->data;
921 u32 cmd_cfg = 0, cmd_data = 0;
922 unsigned int xfer_bytes = 0;
923
924
925 dma_rmb();
926
927 host->cmd = cmd;
928
929 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
930 cmd_cfg |= CMD_CFG_OWNER;
931
932 meson_mmc_set_response_bits(cmd, &cmd_cfg);
933
934
935 if (data) {
936 data->bytes_xfered = 0;
937 cmd_cfg |= CMD_CFG_DATA_IO;
938 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
939 ilog2(meson_mmc_get_timeout_msecs(data)));
940
941 if (meson_mmc_desc_chain_mode(data)) {
942 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
943 return;
944 }
945
946 if (data->blocks > 1) {
947 cmd_cfg |= CMD_CFG_BLOCK_MODE;
948 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
949 data->blocks);
950 meson_mmc_set_blksz(mmc, data->blksz);
951 } else {
952 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
953 }
954
955 xfer_bytes = data->blksz * data->blocks;
956 if (data->flags & MMC_DATA_WRITE) {
957 cmd_cfg |= CMD_CFG_DATA_WR;
958 WARN_ON(xfer_bytes > host->bounce_buf_size);
959 sg_copy_to_buffer(data->sg, data->sg_len,
960 host->bounce_buf, xfer_bytes);
961 dma_wmb();
962 }
963
964 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
965 } else {
966 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
967 ilog2(SD_EMMC_CMD_TIMEOUT));
968 }
969
970
971 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
972 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
973 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
974 writel(0, host->regs + SD_EMMC_CMD_RSP);
975 wmb();
976 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
977}
978
979static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
980{
981 struct meson_host *host = mmc_priv(mmc);
982 bool needs_pre_post_req = mrq->data &&
983 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
984
985 if (needs_pre_post_req) {
986 meson_mmc_get_transfer_mode(mmc, mrq);
987 if (!meson_mmc_desc_chain_mode(mrq->data))
988 needs_pre_post_req = false;
989 }
990
991 if (needs_pre_post_req)
992 meson_mmc_pre_req(mmc, mrq);
993
994
995 writel(0, host->regs + SD_EMMC_START);
996
997 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
998
999 if (needs_pre_post_req)
1000 meson_mmc_post_req(mmc, mrq, 0);
1001}
1002
1003static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
1004{
1005 struct meson_host *host = mmc_priv(mmc);
1006
1007 if (cmd->flags & MMC_RSP_136) {
1008 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
1009 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
1010 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
1011 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
1012 } else if (cmd->flags & MMC_RSP_PRESENT) {
1013 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
1014 }
1015}
1016
1017static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
1018{
1019 struct meson_host *host = dev_id;
1020 struct mmc_command *cmd;
1021 struct mmc_data *data;
1022 u32 irq_en, status, raw_status;
1023 irqreturn_t ret = IRQ_NONE;
1024
1025 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1026 return IRQ_NONE;
1027
1028 spin_lock(&host->lock);
1029
1030 cmd = host->cmd;
1031 data = cmd->data;
1032 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1033 raw_status = readl(host->regs + SD_EMMC_STATUS);
1034 status = raw_status & irq_en;
1035
1036 cmd->error = 0;
1037 if (status & IRQ_CRC_ERR) {
1038 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1039 cmd->error = -EILSEQ;
1040 ret = IRQ_HANDLED;
1041 goto out;
1042 }
1043
1044 if (status & IRQ_TIMEOUTS) {
1045 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1046 cmd->error = -ETIMEDOUT;
1047 ret = IRQ_HANDLED;
1048 goto out;
1049 }
1050
1051 meson_mmc_read_resp(host->mmc, cmd);
1052
1053 if (status & IRQ_SDIO) {
1054 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1055 ret = IRQ_HANDLED;
1056 }
1057
1058 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1059 if (data && !cmd->error)
1060 data->bytes_xfered = data->blksz * data->blocks;
1061 if (meson_mmc_bounce_buf_read(data) ||
1062 meson_mmc_get_next_command(cmd))
1063 ret = IRQ_WAKE_THREAD;
1064 else
1065 ret = IRQ_HANDLED;
1066 }
1067
1068out:
1069
1070 writel(irq_en, host->regs + SD_EMMC_STATUS);
1071
1072 if (ret == IRQ_HANDLED)
1073 meson_mmc_request_done(host->mmc, cmd->mrq);
1074 else if (ret == IRQ_NONE)
1075 dev_warn(host->dev,
1076 "Unexpected IRQ! status=0x%08x, irq_en=0x%08x\n",
1077 raw_status, irq_en);
1078
1079 spin_unlock(&host->lock);
1080 return ret;
1081}
1082
1083static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1084{
1085 struct meson_host *host = dev_id;
1086 struct mmc_command *next_cmd, *cmd = host->cmd;
1087 struct mmc_data *data;
1088 unsigned int xfer_bytes;
1089
1090 if (WARN_ON(!cmd))
1091 return IRQ_NONE;
1092
1093 data = cmd->data;
1094 if (meson_mmc_bounce_buf_read(data)) {
1095 xfer_bytes = data->blksz * data->blocks;
1096 WARN_ON(xfer_bytes > host->bounce_buf_size);
1097 sg_copy_from_buffer(data->sg, data->sg_len,
1098 host->bounce_buf, xfer_bytes);
1099 }
1100
1101 next_cmd = meson_mmc_get_next_command(cmd);
1102 if (next_cmd)
1103 meson_mmc_start_cmd(host->mmc, next_cmd);
1104 else
1105 meson_mmc_request_done(host->mmc, cmd->mrq);
1106
1107 return IRQ_HANDLED;
1108}
1109
1110
1111
1112
1113
1114static int meson_mmc_get_cd(struct mmc_host *mmc)
1115{
1116 int status = mmc_gpio_get_cd(mmc);
1117
1118 if (status == -ENOSYS)
1119 return 1;
1120
1121 return status;
1122}
1123
1124static void meson_mmc_cfg_init(struct meson_host *host)
1125{
1126 u32 cfg = 0;
1127
1128 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1129 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1130 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1131 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1132
1133 writel(cfg, host->regs + SD_EMMC_CFG);
1134}
1135
1136static int meson_mmc_card_busy(struct mmc_host *mmc)
1137{
1138 struct meson_host *host = mmc_priv(mmc);
1139 u32 regval;
1140
1141 regval = readl(host->regs + SD_EMMC_STATUS);
1142
1143
1144 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1145}
1146
1147static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1148{
1149
1150 if (!IS_ERR(mmc->supply.vqmmc)) {
1151
1152
1153
1154
1155
1156
1157
1158 return mmc_regulator_set_vqmmc(mmc, ios);
1159 }
1160
1161
1162 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1163 return 0;
1164
1165 return -EINVAL;
1166}
1167
1168static const struct mmc_host_ops meson_mmc_ops = {
1169 .request = meson_mmc_request,
1170 .set_ios = meson_mmc_set_ios,
1171 .get_cd = meson_mmc_get_cd,
1172 .pre_req = meson_mmc_pre_req,
1173 .post_req = meson_mmc_post_req,
1174 .execute_tuning = meson_mmc_execute_tuning,
1175 .card_busy = meson_mmc_card_busy,
1176 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1177};
1178
1179static int meson_mmc_probe(struct platform_device *pdev)
1180{
1181 struct resource *res;
1182 struct meson_host *host;
1183 struct mmc_host *mmc;
1184 int ret, irq;
1185
1186 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1187 if (!mmc)
1188 return -ENOMEM;
1189 host = mmc_priv(mmc);
1190 host->mmc = mmc;
1191 host->dev = &pdev->dev;
1192 dev_set_drvdata(&pdev->dev, host);
1193
1194 spin_lock_init(&host->lock);
1195
1196
1197 host->vqmmc_enabled = false;
1198 ret = mmc_regulator_get_supply(mmc);
1199 if (ret)
1200 goto free_host;
1201
1202 ret = mmc_of_parse(mmc);
1203 if (ret) {
1204 if (ret != -EPROBE_DEFER)
1205 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1206 goto free_host;
1207 }
1208
1209 host->data = (struct meson_mmc_data *)
1210 of_device_get_match_data(&pdev->dev);
1211 if (!host->data) {
1212 ret = -EINVAL;
1213 goto free_host;
1214 }
1215
1216 ret = device_reset_optional(&pdev->dev);
1217 if (ret) {
1218 if (ret != -EPROBE_DEFER)
1219 dev_err(&pdev->dev, "device reset failed: %d\n", ret);
1220
1221 return ret;
1222 }
1223
1224 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1225 host->regs = devm_ioremap_resource(&pdev->dev, res);
1226 if (IS_ERR(host->regs)) {
1227 ret = PTR_ERR(host->regs);
1228 goto free_host;
1229 }
1230
1231 irq = platform_get_irq(pdev, 0);
1232 if (irq <= 0) {
1233 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1234 ret = -EINVAL;
1235 goto free_host;
1236 }
1237
1238 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1239 if (IS_ERR(host->pinctrl)) {
1240 ret = PTR_ERR(host->pinctrl);
1241 goto free_host;
1242 }
1243
1244 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1245 PINCTRL_STATE_DEFAULT);
1246 if (IS_ERR(host->pins_default)) {
1247 ret = PTR_ERR(host->pins_default);
1248 goto free_host;
1249 }
1250
1251 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1252 "clk-gate");
1253 if (IS_ERR(host->pins_clk_gate)) {
1254 dev_warn(&pdev->dev,
1255 "can't get clk-gate pinctrl, using clk_stop bit\n");
1256 host->pins_clk_gate = NULL;
1257 }
1258
1259 host->core_clk = devm_clk_get(&pdev->dev, "core");
1260 if (IS_ERR(host->core_clk)) {
1261 ret = PTR_ERR(host->core_clk);
1262 goto free_host;
1263 }
1264
1265 ret = clk_prepare_enable(host->core_clk);
1266 if (ret)
1267 goto free_host;
1268
1269 ret = meson_mmc_clk_init(host);
1270 if (ret)
1271 goto err_core_clk;
1272
1273
1274 meson_mmc_cfg_init(host);
1275
1276
1277 writel(0, host->regs + SD_EMMC_START);
1278
1279
1280 writel(0, host->regs + SD_EMMC_IRQ_EN);
1281 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1282 host->regs + SD_EMMC_STATUS);
1283 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1284 host->regs + SD_EMMC_IRQ_EN);
1285
1286 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
1287 meson_mmc_irq_thread, IRQF_SHARED,
1288 NULL, host);
1289 if (ret)
1290 goto err_init_clk;
1291
1292 mmc->caps |= MMC_CAP_CMD23;
1293 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1294 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1295 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1296 mmc->max_seg_size = mmc->max_req_size;
1297
1298
1299 host->bounce_buf_size = mmc->max_req_size;
1300 host->bounce_buf =
1301 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1302 &host->bounce_dma_addr, GFP_KERNEL);
1303 if (host->bounce_buf == NULL) {
1304 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1305 ret = -ENOMEM;
1306 goto err_init_clk;
1307 }
1308
1309 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1310 &host->descs_dma_addr, GFP_KERNEL);
1311 if (!host->descs) {
1312 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1313 ret = -ENOMEM;
1314 goto err_bounce_buf;
1315 }
1316
1317 mmc->ops = &meson_mmc_ops;
1318 mmc_add_host(mmc);
1319
1320 return 0;
1321
1322err_bounce_buf:
1323 dma_free_coherent(host->dev, host->bounce_buf_size,
1324 host->bounce_buf, host->bounce_dma_addr);
1325err_init_clk:
1326 clk_disable_unprepare(host->mmc_clk);
1327err_core_clk:
1328 clk_disable_unprepare(host->core_clk);
1329free_host:
1330 mmc_free_host(mmc);
1331 return ret;
1332}
1333
1334static int meson_mmc_remove(struct platform_device *pdev)
1335{
1336 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1337
1338 mmc_remove_host(host->mmc);
1339
1340
1341 writel(0, host->regs + SD_EMMC_IRQ_EN);
1342
1343 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1344 host->descs, host->descs_dma_addr);
1345 dma_free_coherent(host->dev, host->bounce_buf_size,
1346 host->bounce_buf, host->bounce_dma_addr);
1347
1348 clk_disable_unprepare(host->mmc_clk);
1349 clk_disable_unprepare(host->core_clk);
1350
1351 mmc_free_host(host->mmc);
1352 return 0;
1353}
1354
1355static const struct meson_mmc_data meson_gx_data = {
1356 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1357 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1358 .always_on = CLK_V2_ALWAYS_ON,
1359};
1360
1361static const struct meson_mmc_data meson_axg_data = {
1362 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1363 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1364 .always_on = CLK_V3_ALWAYS_ON,
1365};
1366
1367static const struct of_device_id meson_mmc_of_match[] = {
1368 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1369 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1370 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1371 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1372 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1373 {}
1374};
1375MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1376
1377static struct platform_driver meson_mmc_driver = {
1378 .probe = meson_mmc_probe,
1379 .remove = meson_mmc_remove,
1380 .driver = {
1381 .name = DRIVER_NAME,
1382 .of_match_table = of_match_ptr(meson_mmc_of_match),
1383 },
1384};
1385
1386module_platform_driver(meson_mmc_driver);
1387
1388MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1389MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1390MODULE_LICENSE("GPL v2");
1391
