LXR linux/drivers/net/ethernet/intel/ice/ice

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c) 2018, Intel Corporation. */
   3
   4#ifndef _ICE_TYPE_H_
   5#define _ICE_TYPE_H_
   6
   7#include "ice_status.h"
   8#include "ice_hw_autogen.h"
   9#include "ice_osdep.h"
  10#include "ice_controlq.h"
  11#include "ice_lan_tx_rx.h"
  12
  13#define ICE_BYTES_PER_WORD      2
  14#define ICE_BYTES_PER_DWORD     4
  15
  16static inline bool ice_is_tc_ena(u8 bitmap, u8 tc)
  17{
  18        return test_bit(tc, (unsigned long *)&bitmap);
  19}
  20
  21/* debug masks - set these bits in hw->debug_mask to control output */
  22#define ICE_DBG_INIT            BIT_ULL(1)
  23#define ICE_DBG_LINK            BIT_ULL(4)
  24#define ICE_DBG_QCTX            BIT_ULL(6)
  25#define ICE_DBG_NVM             BIT_ULL(7)
  26#define ICE_DBG_LAN             BIT_ULL(8)
  27#define ICE_DBG_SW              BIT_ULL(13)
  28#define ICE_DBG_SCHED           BIT_ULL(14)
  29#define ICE_DBG_RES             BIT_ULL(17)
  30#define ICE_DBG_AQ_MSG          BIT_ULL(24)
  31#define ICE_DBG_AQ_CMD          BIT_ULL(27)
  32#define ICE_DBG_USER            BIT_ULL(31)
  33
  34enum ice_aq_res_ids {
  35        ICE_NVM_RES_ID = 1,
  36        ICE_SPD_RES_ID,
  37        ICE_GLOBAL_CFG_LOCK_RES_ID,
  38        ICE_CHANGE_LOCK_RES_ID
  39};
  40
  41enum ice_aq_res_access_type {
  42        ICE_RES_READ = 1,
  43        ICE_RES_WRITE
  44};
  45
  46enum ice_fc_mode {
  47        ICE_FC_NONE = 0,
  48        ICE_FC_RX_PAUSE,
  49        ICE_FC_TX_PAUSE,
  50        ICE_FC_FULL,
  51        ICE_FC_PFC,
  52        ICE_FC_DFLT
  53};
  54
  55enum ice_set_fc_aq_failures {
  56        ICE_SET_FC_AQ_FAIL_NONE = 0,
  57        ICE_SET_FC_AQ_FAIL_GET,
  58        ICE_SET_FC_AQ_FAIL_SET,
  59        ICE_SET_FC_AQ_FAIL_UPDATE
  60};
  61
  62/* Various MAC types */
  63enum ice_mac_type {
  64        ICE_MAC_UNKNOWN = 0,
  65        ICE_MAC_GENERIC,
  66};
  67
  68/* Media Types */
  69enum ice_media_type {
  70        ICE_MEDIA_UNKNOWN = 0,
  71        ICE_MEDIA_FIBER,
  72        ICE_MEDIA_BASET,
  73        ICE_MEDIA_BACKPLANE,
  74        ICE_MEDIA_DA,
  75};
  76
  77enum ice_vsi_type {
  78        ICE_VSI_PF = 0,
  79};
  80
  81struct ice_link_status {
  82        /* Refer to ice_aq_phy_type for bits definition */
  83        u64 phy_type_low;
  84        u16 max_frame_size;
  85        u16 link_speed;
  86        bool lse_ena;   /* Link Status Event notification */
  87        u8 link_info;
  88        u8 an_info;
  89        u8 ext_info;
  90        u8 pacing;
  91        u8 req_speeds;
  92        /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
  93         * ice_aqc_get_phy_caps structure
  94         */
  95        u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
  96};
  97
  98/* PHY info such as phy_type, etc... */
  99struct ice_phy_info {
 100        struct ice_link_status link_info;
 101        struct ice_link_status link_info_old;
 102        u64 phy_type_low;
 103        enum ice_media_type media_type;
 104        bool get_link_info;
 105};
 106
 107/* Common HW capabilities for SW use */
 108struct ice_hw_common_caps {
 109        /* TX/RX queues */
 110        u16 num_rxq;            /* Number/Total RX queues */
 111        u16 rxq_first_id;       /* First queue ID for RX queues */
 112        u16 num_txq;            /* Number/Total TX queues */
 113        u16 txq_first_id;       /* First queue ID for TX queues */
 114
 115        /* MSI-X vectors */
 116        u16 num_msix_vectors;
 117        u16 msix_vector_first_id;
 118
 119        /* Max MTU for function or device */
 120        u16 max_mtu;
 121
 122        /* RSS related capabilities */
 123        u16 rss_table_size;             /* 512 for PFs and 64 for VFs */
 124        u8 rss_table_entry_width;       /* RSS Entry width in bits */
 125};
 126
 127/* Function specific capabilities */
 128struct ice_hw_func_caps {
 129        struct ice_hw_common_caps common_cap;
 130        u32 guaranteed_num_vsi;
 131};
 132
 133/* Device wide capabilities */
 134struct ice_hw_dev_caps {
 135        struct ice_hw_common_caps common_cap;
 136        u32 num_vsi_allocd_to_host;     /* Excluding EMP VSI */
 137};
 138
 139/* MAC info */
 140struct ice_mac_info {
 141        u8 lan_addr[ETH_ALEN];
 142        u8 perm_addr[ETH_ALEN];
 143};
 144
 145/* Various RESET request, These are not tied with HW reset types */
 146enum ice_reset_req {
 147        ICE_RESET_PFR   = 0,
 148        ICE_RESET_CORER = 1,
 149        ICE_RESET_GLOBR = 2,
 150};
 151
 152/* Bus parameters */
 153struct ice_bus_info {
 154        u16 device;
 155        u8 func;
 156};
 157
 158/* Flow control (FC) parameters */
 159struct ice_fc_info {
 160        enum ice_fc_mode current_mode;  /* FC mode in effect */
 161        enum ice_fc_mode req_mode;      /* FC mode requested by caller */
 162};
 163
 164/* NVM Information */
 165struct ice_nvm_info {
 166        u32 eetrack;              /* NVM data version */
 167        u32 oem_ver;              /* OEM version info */
 168        u16 sr_words;             /* Shadow RAM size in words */
 169        u16 ver;                  /* NVM package version */
 170        bool blank_nvm_mode;      /* is NVM empty (no FW present) */
 171};
 172
 173/* Max number of port to queue branches w.r.t topology */
 174#define ICE_MAX_TRAFFIC_CLASS 8
 175#define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
 176
 177struct ice_sched_node {
 178        struct ice_sched_node *parent;
 179        struct ice_sched_node *sibling; /* next sibling in the same layer */
 180        struct ice_sched_node **children;
 181        struct ice_aqc_txsched_elem_data info;
 182        u32 agg_id;                     /* aggregator group id */
 183        u16 vsi_id;
 184        bool in_use;                    /* suspended or in use */
 185        u8 tx_sched_layer;              /* Logical Layer (1-9) */
 186        u8 num_children;
 187        u8 tc_num;
 188        u8 owner;
 189#define ICE_SCHED_NODE_OWNER_LAN        0
 190};
 191
 192/* Access Macros for Tx Sched Elements data */
 193#define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
 194
 195/* The aggregator type determines if identifier is for a VSI group,
 196 * aggregator group, aggregator of queues, or queue group.
 197 */
 198enum ice_agg_type {
 199        ICE_AGG_TYPE_UNKNOWN = 0,
 200        ICE_AGG_TYPE_VSI,
 201        ICE_AGG_TYPE_AGG, /* aggregator */
 202        ICE_AGG_TYPE_Q,
 203        ICE_AGG_TYPE_QG
 204};
 205
 206#define ICE_SCHED_DFLT_RL_PROF_ID       0
 207
 208/* vsi type list entry to locate corresponding vsi/ag nodes */
 209struct ice_sched_vsi_info {
 210        struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
 211        struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
 212        struct list_head list_entry;
 213        u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
 214        u16 vsi_id;
 215};
 216
 217/* driver defines the policy */
 218struct ice_sched_tx_policy {
 219        u16 max_num_vsis;
 220        u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
 221        bool rdma_ena;
 222};
 223
 224struct ice_port_info {
 225        struct ice_sched_node *root;    /* Root Node per Port */
 226        struct ice_hw *hw;              /* back pointer to hw instance */
 227        u32 last_node_teid;             /* scheduler last node info */
 228        u16 sw_id;                      /* Initial switch ID belongs to port */
 229        u16 pf_vf_num;
 230        u8 port_state;
 231#define ICE_SCHED_PORT_STATE_INIT       0x0
 232#define ICE_SCHED_PORT_STATE_READY      0x1
 233        u16 dflt_tx_vsi_rule_id;
 234        u16 dflt_tx_vsi_num;
 235        u16 dflt_rx_vsi_rule_id;
 236        u16 dflt_rx_vsi_num;
 237        struct ice_fc_info fc;
 238        struct ice_mac_info mac;
 239        struct ice_phy_info phy;
 240        struct mutex sched_lock;        /* protect access to TXSched tree */
 241        struct ice_sched_tx_policy sched_policy;
 242        struct list_head vsi_info_list;
 243        struct list_head agg_list;      /* lists all aggregator */
 244        u8 lport;
 245#define ICE_LPORT_MASK          0xff
 246        bool is_vf;
 247};
 248
 249struct ice_switch_info {
 250        /* Switch VSI lists to MAC/VLAN translation */
 251        struct mutex mac_list_lock;             /* protect MAC list */
 252        struct list_head mac_list_head;
 253        struct mutex vlan_list_lock;            /* protect VLAN list */
 254        struct list_head vlan_list_head;
 255        struct mutex eth_m_list_lock;   /* protect ethtype list */
 256        struct list_head eth_m_list_head;
 257        struct mutex promisc_list_lock; /* protect promisc mode list */
 258        struct list_head promisc_list_head;
 259        struct mutex mac_vlan_list_lock;        /* protect MAC-VLAN list */
 260        struct list_head mac_vlan_list_head;
 261
 262        struct list_head vsi_list_map_head;
 263};
 264
 265/* Port hardware description */
 266struct ice_hw {
 267        u8 __iomem *hw_addr;
 268        void *back;
 269        struct ice_aqc_layer_props *layer_info;
 270        struct ice_port_info *port_info;
 271        u64 debug_mask;         /* bitmap for debug mask */
 272        enum ice_mac_type mac_type;
 273
 274        /* pci info */
 275        u16 device_id;
 276        u16 vendor_id;
 277        u16 subsystem_device_id;
 278        u16 subsystem_vendor_id;
 279        u8 revision_id;
 280
 281        u8 pf_id;               /* device profile info */
 282
 283        /* TX Scheduler values */
 284        u16 num_tx_sched_layers;
 285        u16 num_tx_sched_phys_layers;
 286        u8 flattened_layers;
 287        u8 max_cgds;
 288        u8 sw_entry_point_layer;
 289
 290        bool evb_veb;           /* true for VEB, false for VEPA */
 291        struct ice_bus_info bus;
 292        struct ice_nvm_info nvm;
 293        struct ice_hw_dev_caps dev_caps;        /* device capabilities */
 294        struct ice_hw_func_caps func_caps;      /* function capabilities */
 295
 296        struct ice_switch_info *switch_info;    /* switch filter lists */
 297
 298        /* Control Queue info */
 299        struct ice_ctl_q_info adminq;
 300
 301        u8 api_branch;          /* API branch version */
 302        u8 api_maj_ver;         /* API major version */
 303        u8 api_min_ver;         /* API minor version */
 304        u8 api_patch;           /* API patch version */
 305        u8 fw_branch;           /* firmware branch version */
 306        u8 fw_maj_ver;          /* firmware major version */
 307        u8 fw_min_ver;          /* firmware minor version */
 308        u8 fw_patch;            /* firmware patch version */
 309        u32 fw_build;           /* firmware build number */
 310
 311        /* minimum allowed value for different speeds */
 312#define ICE_ITR_GRAN_MIN_200    1
 313#define ICE_ITR_GRAN_MIN_100    1
 314#define ICE_ITR_GRAN_MIN_50     2
 315#define ICE_ITR_GRAN_MIN_25     4
 316        /* ITR granularity in 1 us */
 317        u8 itr_gran_200;
 318        u8 itr_gran_100;
 319        u8 itr_gran_50;
 320        u8 itr_gran_25;
 321        bool ucast_shared;      /* true if VSIs can share unicast addr */
 322
 323};
 324
 325/* Statistics collected by each port, VSI, VEB, and S-channel */
 326struct ice_eth_stats {
 327        u64 rx_bytes;                   /* gorc */
 328        u64 rx_unicast;                 /* uprc */
 329        u64 rx_multicast;               /* mprc */
 330        u64 rx_broadcast;               /* bprc */
 331        u64 rx_discards;                /* rdpc */
 332        u64 rx_unknown_protocol;        /* rupp */
 333        u64 tx_bytes;                   /* gotc */
 334        u64 tx_unicast;                 /* uptc */
 335        u64 tx_multicast;               /* mptc */
 336        u64 tx_broadcast;               /* bptc */
 337        u64 tx_discards;                /* tdpc */
 338        u64 tx_errors;                  /* tepc */
 339};
 340
 341/* Statistics collected by the MAC */
 342struct ice_hw_port_stats {
 343        /* eth stats collected by the port */
 344        struct ice_eth_stats eth;
 345        /* additional port specific stats */
 346        u64 tx_dropped_link_down;       /* tdold */
 347        u64 crc_errors;                 /* crcerrs */
 348        u64 illegal_bytes;              /* illerrc */
 349        u64 error_bytes;                /* errbc */
 350        u64 mac_local_faults;           /* mlfc */
 351        u64 mac_remote_faults;          /* mrfc */
 352        u64 rx_len_errors;              /* rlec */
 353        u64 link_xon_rx;                /* lxonrxc */
 354        u64 link_xoff_rx;               /* lxoffrxc */
 355        u64 link_xon_tx;                /* lxontxc */
 356        u64 link_xoff_tx;               /* lxofftxc */
 357        u64 rx_size_64;                 /* prc64 */
 358        u64 rx_size_127;                /* prc127 */
 359        u64 rx_size_255;                /* prc255 */
 360        u64 rx_size_511;                /* prc511 */
 361        u64 rx_size_1023;               /* prc1023 */
 362        u64 rx_size_1522;               /* prc1522 */
 363        u64 rx_size_big;                /* prc9522 */
 364        u64 rx_undersize;               /* ruc */
 365        u64 rx_fragments;               /* rfc */
 366        u64 rx_oversize;                /* roc */
 367        u64 rx_jabber;                  /* rjc */
 368        u64 tx_size_64;                 /* ptc64 */
 369        u64 tx_size_127;                /* ptc127 */
 370        u64 tx_size_255;                /* ptc255 */
 371        u64 tx_size_511;                /* ptc511 */
 372        u64 tx_size_1023;               /* ptc1023 */
 373        u64 tx_size_1522;               /* ptc1522 */
 374        u64 tx_size_big;                /* ptc9522 */
 375};
 376
 377/* Checksum and Shadow RAM pointers */
 378#define ICE_SR_NVM_DEV_STARTER_VER      0x18
 379#define ICE_SR_NVM_EETRACK_LO           0x2D
 380#define ICE_SR_NVM_EETRACK_HI           0x2E
 381#define ICE_NVM_VER_LO_SHIFT            0
 382#define ICE_NVM_VER_LO_MASK             (0xff << ICE_NVM_VER_LO_SHIFT)
 383#define ICE_NVM_VER_HI_SHIFT            12
 384#define ICE_NVM_VER_HI_MASK             (0xf << ICE_NVM_VER_HI_SHIFT)
 385#define ICE_OEM_VER_PATCH_SHIFT         0
 386#define ICE_OEM_VER_PATCH_MASK          (0xff << ICE_OEM_VER_PATCH_SHIFT)
 387#define ICE_OEM_VER_BUILD_SHIFT         8
 388#define ICE_OEM_VER_BUILD_MASK          (0xffff << ICE_OEM_VER_BUILD_SHIFT)
 389#define ICE_OEM_VER_SHIFT               24
 390#define ICE_OEM_VER_MASK                (0xff << ICE_OEM_VER_SHIFT)
 391#define ICE_SR_SECTOR_SIZE_IN_WORDS     0x800
 392#define ICE_SR_WORDS_IN_1KB             512
 393
 394#endif /* _ICE_TYPE_H_ */
 395