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38
39#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
40
41#include <linux/module.h>
42#include <linux/kernel.h>
43#include <linux/mm.h>
44#include <linux/net.h>
45#include <linux/skbuff.h>
46#include <linux/netdevice.h>
47#include <linux/if_arp.h>
48#include <linux/delay.h>
49#include <linux/hdlc.h>
50#include <linux/ioport.h>
51#include <linux/init.h>
52#include <linux/gfp.h>
53#include <asm/dma.h>
54#include <asm/io.h>
55#define RT_LOCK
56#define RT_UNLOCK
57#include <linux/spinlock.h>
58
59#include "z85230.h"
60
61
62
63
64
65
66
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72
73
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75
76
77
78static inline int z8530_read_port(unsigned long p)
79{
80 u8 r=inb(Z8530_PORT_OF(p));
81 if(p&Z8530_PORT_SLEEP)
82 udelay(5);
83 return r;
84}
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102static inline void z8530_write_port(unsigned long p, u8 d)
103{
104 outb(d,Z8530_PORT_OF(p));
105 if(p&Z8530_PORT_SLEEP)
106 udelay(5);
107}
108
109
110
111static void z8530_rx_done(struct z8530_channel *c);
112static void z8530_tx_done(struct z8530_channel *c);
113
114
115
116
117
118
119
120
121
122
123
124
125
126static inline u8 read_zsreg(struct z8530_channel *c, u8 reg)
127{
128 if(reg)
129 z8530_write_port(c->ctrlio, reg);
130 return z8530_read_port(c->ctrlio);
131}
132
133
134
135
136
137
138
139
140
141static inline u8 read_zsdata(struct z8530_channel *c)
142{
143 u8 r;
144 r=z8530_read_port(c->dataio);
145 return r;
146}
147
148
149
150
151
152
153
154
155
156
157
158
159
160static inline void write_zsreg(struct z8530_channel *c, u8 reg, u8 val)
161{
162 if(reg)
163 z8530_write_port(c->ctrlio, reg);
164 z8530_write_port(c->ctrlio, val);
165
166}
167
168
169
170
171
172
173
174
175
176static inline void write_zsctrl(struct z8530_channel *c, u8 val)
177{
178 z8530_write_port(c->ctrlio, val);
179}
180
181
182
183
184
185
186
187
188
189
190static inline void write_zsdata(struct z8530_channel *c, u8 val)
191{
192 z8530_write_port(c->dataio, val);
193}
194
195
196
197
198
199u8 z8530_dead_port[]=
200{
201 255
202};
203
204EXPORT_SYMBOL(z8530_dead_port);
205
206
207
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209
210
211
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214
215
216u8 z8530_hdlc_kilostream[]=
217{
218 4, SYNC_ENAB|SDLC|X1CLK,
219 2, 0,
220 1, 0,
221 3, ENT_HM|RxCRC_ENAB|Rx8,
222 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
223 9, 0,
224 6, 0xFF,
225 7, FLAG,
226 10, ABUNDER|NRZ|CRCPS,
227 11, TCTRxCP,
228 14, DISDPLL,
229 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
230 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
231 9, NV|MIE|NORESET,
232 255
233};
234
235EXPORT_SYMBOL(z8530_hdlc_kilostream);
236
237
238
239
240
241u8 z8530_hdlc_kilostream_85230[]=
242{
243 4, SYNC_ENAB|SDLC|X1CLK,
244 2, 0,
245 1, 0,
246 3, ENT_HM|RxCRC_ENAB|Rx8,
247 5, TxCRC_ENAB|RTS|TxENAB|Tx8|DTR,
248 9, 0,
249 6, 0xFF,
250 7, FLAG,
251 10, ABUNDER|NRZ|CRCPS,
252 11, TCTRxCP,
253 14, DISDPLL,
254 15, DCDIE|SYNCIE|CTSIE|TxUIE|BRKIE,
255 1, EXT_INT_ENAB|TxINT_ENAB|INT_ALL_Rx,
256 9, NV|MIE|NORESET,
257 23, 3,
258
259 255
260};
261
262EXPORT_SYMBOL(z8530_hdlc_kilostream_85230);
263
264
265
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268
269
270
271
272
273
274
275
276static void z8530_flush_fifo(struct z8530_channel *c)
277{
278 read_zsreg(c, R1);
279 read_zsreg(c, R1);
280 read_zsreg(c, R1);
281 read_zsreg(c, R1);
282 if(c->dev->type==Z85230)
283 {
284 read_zsreg(c, R1);
285 read_zsreg(c, R1);
286 read_zsreg(c, R1);
287 read_zsreg(c, R1);
288 }
289}
290
291
292
293
294
295
296
297
298
299
300
301
302static void z8530_rtsdtr(struct z8530_channel *c, int set)
303{
304 if (set)
305 c->regs[5] |= (RTS | DTR);
306 else
307 c->regs[5] &= ~(RTS | DTR);
308 write_zsreg(c, R5, c->regs[5]);
309}
310
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334
335static void z8530_rx(struct z8530_channel *c)
336{
337 u8 ch,stat;
338
339 while(1)
340 {
341
342 if(!(read_zsreg(c, R0)&1))
343 break;
344 ch=read_zsdata(c);
345 stat=read_zsreg(c, R1);
346
347
348
349
350 if(c->count < c->max)
351 {
352 *c->dptr++=ch;
353 c->count++;
354 }
355
356 if(stat&END_FR)
357 {
358
359
360
361
362 if(stat&(Rx_OVR|CRC_ERR))
363 {
364
365 if(c->skb)
366 c->dptr=c->skb->data;
367 c->count=0;
368 if(stat&Rx_OVR)
369 {
370 pr_warn("%s: overrun\n", c->dev->name);
371 c->rx_overrun++;
372 }
373 if(stat&CRC_ERR)
374 {
375 c->rx_crc_err++;
376
377 }
378
379 }
380 else
381 {
382
383
384
385
386 z8530_rx_done(c);
387 write_zsctrl(c, RES_Rx_CRC);
388 }
389 }
390 }
391
392
393
394 write_zsctrl(c, ERR_RES);
395 write_zsctrl(c, RES_H_IUS);
396}
397
398
399
400
401
402
403
404
405
406
407
408
409static void z8530_tx(struct z8530_channel *c)
410{
411 while(c->txcount) {
412
413 if(!(read_zsreg(c, R0)&4))
414 return;
415 c->txcount--;
416
417
418
419 write_zsreg(c, R8, *c->tx_ptr++);
420 write_zsctrl(c, RES_H_IUS);
421
422 if(c->txcount==0)
423 {
424 write_zsctrl(c, RES_EOM_L);
425 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
426 }
427 }
428
429
430
431
432
433
434 write_zsctrl(c, RES_Tx_P);
435
436 z8530_tx_done(c);
437 write_zsctrl(c, RES_H_IUS);
438}
439
440
441
442
443
444
445
446
447
448
449
450static void z8530_status(struct z8530_channel *chan)
451{
452 u8 status, altered;
453
454 status = read_zsreg(chan, R0);
455 altered = chan->status ^ status;
456
457 chan->status = status;
458
459 if (status & TxEOM) {
460
461 chan->netdevice->stats.tx_fifo_errors++;
462 write_zsctrl(chan, ERR_RES);
463 z8530_tx_done(chan);
464 }
465
466 if (altered & chan->dcdcheck)
467 {
468 if (status & chan->dcdcheck) {
469 pr_info("%s: DCD raised\n", chan->dev->name);
470 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
471 if (chan->netdevice)
472 netif_carrier_on(chan->netdevice);
473 } else {
474 pr_info("%s: DCD lost\n", chan->dev->name);
475 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
476 z8530_flush_fifo(chan);
477 if (chan->netdevice)
478 netif_carrier_off(chan->netdevice);
479 }
480
481 }
482 write_zsctrl(chan, RES_EXT_INT);
483 write_zsctrl(chan, RES_H_IUS);
484}
485
486struct z8530_irqhandler z8530_sync = {
487 .rx = z8530_rx,
488 .tx = z8530_tx,
489 .status = z8530_status,
490};
491
492EXPORT_SYMBOL(z8530_sync);
493
494
495
496
497
498
499
500
501
502
503
504static void z8530_dma_rx(struct z8530_channel *chan)
505{
506 if(chan->rxdma_on)
507 {
508
509 u8 status;
510
511 read_zsreg(chan, R7);
512 read_zsreg(chan, R6);
513
514 status=read_zsreg(chan, R1);
515
516 if(status&END_FR)
517 {
518 z8530_rx_done(chan);
519 }
520 write_zsctrl(chan, ERR_RES);
521 write_zsctrl(chan, RES_H_IUS);
522 }
523 else
524 {
525
526 z8530_rx(chan);
527 }
528}
529
530
531
532
533
534
535
536
537
538static void z8530_dma_tx(struct z8530_channel *chan)
539{
540 if(!chan->dma_tx)
541 {
542 pr_warn("Hey who turned the DMA off?\n");
543 z8530_tx(chan);
544 return;
545 }
546
547 pr_err("DMA tx - bogus event!\n");
548 z8530_tx(chan);
549}
550
551
552
553
554
555
556
557
558
559
560
561static void z8530_dma_status(struct z8530_channel *chan)
562{
563 u8 status, altered;
564
565 status=read_zsreg(chan, R0);
566 altered=chan->status^status;
567
568 chan->status=status;
569
570
571 if(chan->dma_tx)
572 {
573 if(status&TxEOM)
574 {
575 unsigned long flags;
576
577 flags=claim_dma_lock();
578 disable_dma(chan->txdma);
579 clear_dma_ff(chan->txdma);
580 chan->txdma_on=0;
581 release_dma_lock(flags);
582 z8530_tx_done(chan);
583 }
584 }
585
586 if (altered & chan->dcdcheck)
587 {
588 if (status & chan->dcdcheck) {
589 pr_info("%s: DCD raised\n", chan->dev->name);
590 write_zsreg(chan, R3, chan->regs[3] | RxENABLE);
591 if (chan->netdevice)
592 netif_carrier_on(chan->netdevice);
593 } else {
594 pr_info("%s: DCD lost\n", chan->dev->name);
595 write_zsreg(chan, R3, chan->regs[3] & ~RxENABLE);
596 z8530_flush_fifo(chan);
597 if (chan->netdevice)
598 netif_carrier_off(chan->netdevice);
599 }
600 }
601
602 write_zsctrl(chan, RES_EXT_INT);
603 write_zsctrl(chan, RES_H_IUS);
604}
605
606static struct z8530_irqhandler z8530_dma_sync = {
607 .rx = z8530_dma_rx,
608 .tx = z8530_dma_tx,
609 .status = z8530_dma_status,
610};
611
612static struct z8530_irqhandler z8530_txdma_sync = {
613 .rx = z8530_rx,
614 .tx = z8530_dma_tx,
615 .status = z8530_dma_status,
616};
617
618
619
620
621
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623
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625
626
627
628static void z8530_rx_clear(struct z8530_channel *c)
629{
630
631
632
633 u8 stat;
634
635 read_zsdata(c);
636 stat=read_zsreg(c, R1);
637
638 if(stat&END_FR)
639 write_zsctrl(c, RES_Rx_CRC);
640
641
642
643 write_zsctrl(c, ERR_RES);
644 write_zsctrl(c, RES_H_IUS);
645}
646
647
648
649
650
651
652
653
654
655
656static void z8530_tx_clear(struct z8530_channel *c)
657{
658 write_zsctrl(c, RES_Tx_P);
659 write_zsctrl(c, RES_H_IUS);
660}
661
662
663
664
665
666
667
668
669
670
671static void z8530_status_clear(struct z8530_channel *chan)
672{
673 u8 status=read_zsreg(chan, R0);
674 if(status&TxEOM)
675 write_zsctrl(chan, ERR_RES);
676 write_zsctrl(chan, RES_EXT_INT);
677 write_zsctrl(chan, RES_H_IUS);
678}
679
680struct z8530_irqhandler z8530_nop = {
681 .rx = z8530_rx_clear,
682 .tx = z8530_tx_clear,
683 .status = z8530_status_clear,
684};
685
686
687EXPORT_SYMBOL(z8530_nop);
688
689
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703
704
705irqreturn_t z8530_interrupt(int irq, void *dev_id)
706{
707 struct z8530_dev *dev=dev_id;
708 u8 uninitialized_var(intr);
709 static volatile int locker=0;
710 int work=0;
711 struct z8530_irqhandler *irqs;
712
713 if(locker)
714 {
715 pr_err("IRQ re-enter\n");
716 return IRQ_NONE;
717 }
718 locker=1;
719
720 spin_lock(&dev->lock);
721
722 while(++work<5000)
723 {
724
725 intr = read_zsreg(&dev->chanA, R3);
726 if(!(intr & (CHARxIP|CHATxIP|CHAEXT|CHBRxIP|CHBTxIP|CHBEXT)))
727 break;
728
729
730
731
732
733
734
735 irqs=dev->chanA.irqs;
736
737 if(intr & (CHARxIP|CHATxIP|CHAEXT))
738 {
739 if(intr&CHARxIP)
740 irqs->rx(&dev->chanA);
741 if(intr&CHATxIP)
742 irqs->tx(&dev->chanA);
743 if(intr&CHAEXT)
744 irqs->status(&dev->chanA);
745 }
746
747 irqs=dev->chanB.irqs;
748
749 if(intr & (CHBRxIP|CHBTxIP|CHBEXT))
750 {
751 if(intr&CHBRxIP)
752 irqs->rx(&dev->chanB);
753 if(intr&CHBTxIP)
754 irqs->tx(&dev->chanB);
755 if(intr&CHBEXT)
756 irqs->status(&dev->chanB);
757 }
758 }
759 spin_unlock(&dev->lock);
760 if(work==5000)
761 pr_err("%s: interrupt jammed - abort(0x%X)!\n",
762 dev->name, intr);
763
764 locker=0;
765 return IRQ_HANDLED;
766}
767
768EXPORT_SYMBOL(z8530_interrupt);
769
770static const u8 reg_init[16]=
771{
772 0,0,0,0,
773 0,0,0,0,
774 0,0,0,0,
775 0x55,0,0,0
776};
777
778
779
780
781
782
783
784
785
786
787
788int z8530_sync_open(struct net_device *dev, struct z8530_channel *c)
789{
790 unsigned long flags;
791
792 spin_lock_irqsave(c->lock, flags);
793
794 c->sync = 1;
795 c->mtu = dev->mtu+64;
796 c->count = 0;
797 c->skb = NULL;
798 c->skb2 = NULL;
799 c->irqs = &z8530_sync;
800
801
802 z8530_rx_done(c);
803 z8530_rx_done(c);
804 z8530_rtsdtr(c,1);
805 c->dma_tx = 0;
806 c->regs[R1]|=TxINT_ENAB;
807 write_zsreg(c, R1, c->regs[R1]);
808 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
809
810 spin_unlock_irqrestore(c->lock, flags);
811 return 0;
812}
813
814
815EXPORT_SYMBOL(z8530_sync_open);
816
817
818
819
820
821
822
823
824
825
826int z8530_sync_close(struct net_device *dev, struct z8530_channel *c)
827{
828 u8 chk;
829 unsigned long flags;
830
831 spin_lock_irqsave(c->lock, flags);
832 c->irqs = &z8530_nop;
833 c->max = 0;
834 c->sync = 0;
835
836 chk=read_zsreg(c,R0);
837 write_zsreg(c, R3, c->regs[R3]);
838 z8530_rtsdtr(c,0);
839
840 spin_unlock_irqrestore(c->lock, flags);
841 return 0;
842}
843
844EXPORT_SYMBOL(z8530_sync_close);
845
846
847
848
849
850
851
852
853
854
855
856int z8530_sync_dma_open(struct net_device *dev, struct z8530_channel *c)
857{
858 unsigned long cflags, dflags;
859
860 c->sync = 1;
861 c->mtu = dev->mtu+64;
862 c->count = 0;
863 c->skb = NULL;
864 c->skb2 = NULL;
865
866
867
868 c->rxdma_on = 0;
869 c->txdma_on = 0;
870
871
872
873
874
875
876
877 if(c->mtu > PAGE_SIZE/2)
878 return -EMSGSIZE;
879
880 c->rx_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
881 if(c->rx_buf[0]==NULL)
882 return -ENOBUFS;
883 c->rx_buf[1]=c->rx_buf[0]+PAGE_SIZE/2;
884
885 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
886 if(c->tx_dma_buf[0]==NULL)
887 {
888 free_page((unsigned long)c->rx_buf[0]);
889 c->rx_buf[0]=NULL;
890 return -ENOBUFS;
891 }
892 c->tx_dma_buf[1]=c->tx_dma_buf[0]+PAGE_SIZE/2;
893
894 c->tx_dma_used=0;
895 c->dma_tx = 1;
896 c->dma_num=0;
897 c->dma_ready=1;
898
899
900
901
902
903 spin_lock_irqsave(c->lock, cflags);
904
905
906
907
908
909 c->regs[R14]|= DTRREQ;
910 write_zsreg(c, R14, c->regs[R14]);
911
912 c->regs[R1]&= ~TxINT_ENAB;
913 write_zsreg(c, R1, c->regs[R1]);
914
915
916
917
918
919 c->regs[R1]|= WT_FN_RDYFN;
920 c->regs[R1]|= WT_RDY_RT;
921 c->regs[R1]|= INT_ERR_Rx;
922 c->regs[R1]&= ~TxINT_ENAB;
923 write_zsreg(c, R1, c->regs[R1]);
924 c->regs[R1]|= WT_RDY_ENAB;
925 write_zsreg(c, R1, c->regs[R1]);
926
927
928
929
930
931
932
933
934
935 dflags=claim_dma_lock();
936
937 disable_dma(c->rxdma);
938 clear_dma_ff(c->rxdma);
939 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
940 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[0]));
941 set_dma_count(c->rxdma, c->mtu);
942 enable_dma(c->rxdma);
943
944 disable_dma(c->txdma);
945 clear_dma_ff(c->txdma);
946 set_dma_mode(c->txdma, DMA_MODE_WRITE);
947 disable_dma(c->txdma);
948
949 release_dma_lock(dflags);
950
951
952
953
954
955 c->rxdma_on = 1;
956 c->txdma_on = 1;
957 c->tx_dma_used = 1;
958
959 c->irqs = &z8530_dma_sync;
960 z8530_rtsdtr(c,1);
961 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
962
963 spin_unlock_irqrestore(c->lock, cflags);
964
965 return 0;
966}
967
968EXPORT_SYMBOL(z8530_sync_dma_open);
969
970
971
972
973
974
975
976
977
978
979int z8530_sync_dma_close(struct net_device *dev, struct z8530_channel *c)
980{
981 u8 chk;
982 unsigned long flags;
983
984 c->irqs = &z8530_nop;
985 c->max = 0;
986 c->sync = 0;
987
988
989
990
991
992 flags=claim_dma_lock();
993 disable_dma(c->rxdma);
994 clear_dma_ff(c->rxdma);
995
996 c->rxdma_on = 0;
997
998 disable_dma(c->txdma);
999 clear_dma_ff(c->txdma);
1000 release_dma_lock(flags);
1001
1002 c->txdma_on = 0;
1003 c->tx_dma_used = 0;
1004
1005 spin_lock_irqsave(c->lock, flags);
1006
1007
1008
1009
1010
1011 c->regs[R1]&= ~WT_RDY_ENAB;
1012 write_zsreg(c, R1, c->regs[R1]);
1013 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1014 c->regs[R1]|= INT_ALL_Rx;
1015 write_zsreg(c, R1, c->regs[R1]);
1016 c->regs[R14]&= ~DTRREQ;
1017 write_zsreg(c, R14, c->regs[R14]);
1018
1019 if(c->rx_buf[0])
1020 {
1021 free_page((unsigned long)c->rx_buf[0]);
1022 c->rx_buf[0]=NULL;
1023 }
1024 if(c->tx_dma_buf[0])
1025 {
1026 free_page((unsigned long)c->tx_dma_buf[0]);
1027 c->tx_dma_buf[0]=NULL;
1028 }
1029 chk=read_zsreg(c,R0);
1030 write_zsreg(c, R3, c->regs[R3]);
1031 z8530_rtsdtr(c,0);
1032
1033 spin_unlock_irqrestore(c->lock, flags);
1034
1035 return 0;
1036}
1037
1038EXPORT_SYMBOL(z8530_sync_dma_close);
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050int z8530_sync_txdma_open(struct net_device *dev, struct z8530_channel *c)
1051{
1052 unsigned long cflags, dflags;
1053
1054 printk("Opening sync interface for TX-DMA\n");
1055 c->sync = 1;
1056 c->mtu = dev->mtu+64;
1057 c->count = 0;
1058 c->skb = NULL;
1059 c->skb2 = NULL;
1060
1061
1062
1063
1064
1065
1066
1067 if(c->mtu > PAGE_SIZE/2)
1068 return -EMSGSIZE;
1069
1070 c->tx_dma_buf[0]=(void *)get_zeroed_page(GFP_KERNEL|GFP_DMA);
1071 if(c->tx_dma_buf[0]==NULL)
1072 return -ENOBUFS;
1073
1074 c->tx_dma_buf[1] = c->tx_dma_buf[0] + PAGE_SIZE/2;
1075
1076
1077 spin_lock_irqsave(c->lock, cflags);
1078
1079
1080
1081
1082
1083 z8530_rx_done(c);
1084 z8530_rx_done(c);
1085
1086
1087
1088
1089
1090 c->rxdma_on = 0;
1091 c->txdma_on = 0;
1092
1093 c->tx_dma_used=0;
1094 c->dma_num=0;
1095 c->dma_ready=1;
1096 c->dma_tx = 1;
1097
1098
1099
1100
1101
1102
1103
1104
1105 c->regs[R14]|= DTRREQ;
1106 write_zsreg(c, R14, c->regs[R14]);
1107
1108 c->regs[R1]&= ~TxINT_ENAB;
1109 write_zsreg(c, R1, c->regs[R1]);
1110
1111
1112
1113
1114
1115 dflags = claim_dma_lock();
1116
1117 disable_dma(c->txdma);
1118 clear_dma_ff(c->txdma);
1119 set_dma_mode(c->txdma, DMA_MODE_WRITE);
1120 disable_dma(c->txdma);
1121
1122 release_dma_lock(dflags);
1123
1124
1125
1126
1127
1128 c->rxdma_on = 0;
1129 c->txdma_on = 1;
1130 c->tx_dma_used = 1;
1131
1132 c->irqs = &z8530_txdma_sync;
1133 z8530_rtsdtr(c,1);
1134 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1135 spin_unlock_irqrestore(c->lock, cflags);
1136
1137 return 0;
1138}
1139
1140EXPORT_SYMBOL(z8530_sync_txdma_open);
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151int z8530_sync_txdma_close(struct net_device *dev, struct z8530_channel *c)
1152{
1153 unsigned long dflags, cflags;
1154 u8 chk;
1155
1156
1157 spin_lock_irqsave(c->lock, cflags);
1158
1159 c->irqs = &z8530_nop;
1160 c->max = 0;
1161 c->sync = 0;
1162
1163
1164
1165
1166
1167 dflags = claim_dma_lock();
1168
1169 disable_dma(c->txdma);
1170 clear_dma_ff(c->txdma);
1171 c->txdma_on = 0;
1172 c->tx_dma_used = 0;
1173
1174 release_dma_lock(dflags);
1175
1176
1177
1178
1179
1180 c->regs[R1]&= ~WT_RDY_ENAB;
1181 write_zsreg(c, R1, c->regs[R1]);
1182 c->regs[R1]&= ~(WT_RDY_RT|WT_FN_RDYFN|INT_ERR_Rx);
1183 c->regs[R1]|= INT_ALL_Rx;
1184 write_zsreg(c, R1, c->regs[R1]);
1185 c->regs[R14]&= ~DTRREQ;
1186 write_zsreg(c, R14, c->regs[R14]);
1187
1188 if(c->tx_dma_buf[0])
1189 {
1190 free_page((unsigned long)c->tx_dma_buf[0]);
1191 c->tx_dma_buf[0]=NULL;
1192 }
1193 chk=read_zsreg(c,R0);
1194 write_zsreg(c, R3, c->regs[R3]);
1195 z8530_rtsdtr(c,0);
1196
1197 spin_unlock_irqrestore(c->lock, cflags);
1198 return 0;
1199}
1200
1201
1202EXPORT_SYMBOL(z8530_sync_txdma_close);
1203
1204
1205
1206
1207
1208
1209
1210static const char *z8530_type_name[]={
1211 "Z8530",
1212 "Z85C30",
1213 "Z85230"
1214};
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227void z8530_describe(struct z8530_dev *dev, char *mapping, unsigned long io)
1228{
1229 pr_info("%s: %s found at %s 0x%lX, IRQ %d\n",
1230 dev->name,
1231 z8530_type_name[dev->type],
1232 mapping,
1233 Z8530_PORT_OF(io),
1234 dev->irq);
1235}
1236
1237EXPORT_SYMBOL(z8530_describe);
1238
1239
1240
1241
1242
1243static inline int do_z8530_init(struct z8530_dev *dev)
1244{
1245
1246
1247 dev->chanA.irqs=&z8530_nop;
1248 dev->chanB.irqs=&z8530_nop;
1249 dev->chanA.dcdcheck=DCD;
1250 dev->chanB.dcdcheck=DCD;
1251
1252
1253 write_zsreg(&dev->chanA, R9, 0xC0);
1254 udelay(200);
1255
1256 write_zsreg(&dev->chanA, R12, 0xAA);
1257 if(read_zsreg(&dev->chanA, R12)!=0xAA)
1258 return -ENODEV;
1259 write_zsreg(&dev->chanA, R12, 0x55);
1260 if(read_zsreg(&dev->chanA, R12)!=0x55)
1261 return -ENODEV;
1262
1263 dev->type=Z8530;
1264
1265
1266
1267
1268
1269 write_zsreg(&dev->chanA, R15, 0x01);
1270
1271
1272
1273
1274
1275
1276 if(read_zsreg(&dev->chanA, R15)==0x01)
1277 {
1278
1279
1280 write_zsreg(&dev->chanA, R8, 0);
1281 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP)
1282 dev->type = Z85230;
1283 else
1284 dev->type = Z85C30;
1285 }
1286
1287
1288
1289
1290
1291
1292
1293 write_zsreg(&dev->chanA, R15, 0);
1294
1295
1296
1297
1298
1299 memcpy(dev->chanA.regs, reg_init, 16);
1300 memcpy(dev->chanB.regs, reg_init ,16);
1301
1302 return 0;
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322int z8530_init(struct z8530_dev *dev)
1323{
1324 unsigned long flags;
1325 int ret;
1326
1327
1328 spin_lock_init(&dev->lock);
1329 dev->chanA.lock = &dev->lock;
1330 dev->chanB.lock = &dev->lock;
1331
1332 spin_lock_irqsave(&dev->lock, flags);
1333 ret = do_z8530_init(dev);
1334 spin_unlock_irqrestore(&dev->lock, flags);
1335
1336 return ret;
1337}
1338
1339
1340EXPORT_SYMBOL(z8530_init);
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353int z8530_shutdown(struct z8530_dev *dev)
1354{
1355 unsigned long flags;
1356
1357
1358 spin_lock_irqsave(&dev->lock, flags);
1359 dev->chanA.irqs=&z8530_nop;
1360 dev->chanB.irqs=&z8530_nop;
1361 write_zsreg(&dev->chanA, R9, 0xC0);
1362
1363 udelay(100);
1364 spin_unlock_irqrestore(&dev->lock, flags);
1365 return 0;
1366}
1367
1368EXPORT_SYMBOL(z8530_shutdown);
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381int z8530_channel_load(struct z8530_channel *c, u8 *rtable)
1382{
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(c->lock, flags);
1386
1387 while(*rtable!=255)
1388 {
1389 int reg=*rtable++;
1390 if(reg>0x0F)
1391 write_zsreg(c, R15, c->regs[15]|1);
1392 write_zsreg(c, reg&0x0F, *rtable);
1393 if(reg>0x0F)
1394 write_zsreg(c, R15, c->regs[15]&~1);
1395 c->regs[reg]=*rtable++;
1396 }
1397 c->rx_function=z8530_null_rx;
1398 c->skb=NULL;
1399 c->tx_skb=NULL;
1400 c->tx_next_skb=NULL;
1401 c->mtu=1500;
1402 c->max=0;
1403 c->count=0;
1404 c->status=read_zsreg(c, R0);
1405 c->sync=1;
1406 write_zsreg(c, R3, c->regs[R3]|RxENABLE);
1407
1408 spin_unlock_irqrestore(c->lock, flags);
1409 return 0;
1410}
1411
1412EXPORT_SYMBOL(z8530_channel_load);
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429static void z8530_tx_begin(struct z8530_channel *c)
1430{
1431 unsigned long flags;
1432 if(c->tx_skb)
1433 return;
1434
1435 c->tx_skb=c->tx_next_skb;
1436 c->tx_next_skb=NULL;
1437 c->tx_ptr=c->tx_next_ptr;
1438
1439 if(c->tx_skb==NULL)
1440 {
1441
1442 if(c->dma_tx)
1443 {
1444 flags=claim_dma_lock();
1445 disable_dma(c->txdma);
1446
1447
1448
1449 if (get_dma_residue(c->txdma))
1450 {
1451 c->netdevice->stats.tx_dropped++;
1452 c->netdevice->stats.tx_fifo_errors++;
1453 }
1454 release_dma_lock(flags);
1455 }
1456 c->txcount=0;
1457 }
1458 else
1459 {
1460 c->txcount=c->tx_skb->len;
1461
1462
1463 if(c->dma_tx)
1464 {
1465
1466
1467
1468
1469
1470
1471
1472 flags=claim_dma_lock();
1473 disable_dma(c->txdma);
1474
1475
1476
1477
1478
1479
1480 if(c->dev->type!=Z85230)
1481 {
1482 write_zsctrl(c, RES_Tx_CRC);
1483 write_zsctrl(c, RES_EOM_L);
1484 }
1485 write_zsreg(c, R10, c->regs[10]&~ABUNDER);
1486 clear_dma_ff(c->txdma);
1487 set_dma_addr(c->txdma, virt_to_bus(c->tx_ptr));
1488 set_dma_count(c->txdma, c->txcount);
1489 enable_dma(c->txdma);
1490 release_dma_lock(flags);
1491 write_zsctrl(c, RES_EOM_L);
1492 write_zsreg(c, R5, c->regs[R5]|TxENAB);
1493 }
1494 else
1495 {
1496
1497
1498 write_zsreg(c, R10, c->regs[10]);
1499 write_zsctrl(c, RES_Tx_CRC);
1500
1501 while(c->txcount && (read_zsreg(c,R0)&Tx_BUF_EMP))
1502 {
1503 write_zsreg(c, R8, *c->tx_ptr++);
1504 c->txcount--;
1505 }
1506
1507 }
1508 }
1509
1510
1511
1512 netif_wake_queue(c->netdevice);
1513}
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526static void z8530_tx_done(struct z8530_channel *c)
1527{
1528 struct sk_buff *skb;
1529
1530
1531 if (c->tx_skb == NULL)
1532 return;
1533
1534 skb = c->tx_skb;
1535 c->tx_skb = NULL;
1536 z8530_tx_begin(c);
1537 c->netdevice->stats.tx_packets++;
1538 c->netdevice->stats.tx_bytes += skb->len;
1539 dev_kfree_skb_irq(skb);
1540}
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551void z8530_null_rx(struct z8530_channel *c, struct sk_buff *skb)
1552{
1553 dev_kfree_skb_any(skb);
1554}
1555
1556EXPORT_SYMBOL(z8530_null_rx);
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571static void z8530_rx_done(struct z8530_channel *c)
1572{
1573 struct sk_buff *skb;
1574 int ct;
1575
1576
1577
1578
1579
1580 if(c->rxdma_on)
1581 {
1582
1583
1584
1585
1586
1587 int ready=c->dma_ready;
1588 unsigned char *rxb=c->rx_buf[c->dma_num];
1589 unsigned long flags;
1590
1591
1592
1593
1594
1595 flags=claim_dma_lock();
1596
1597 disable_dma(c->rxdma);
1598 clear_dma_ff(c->rxdma);
1599 c->rxdma_on=0;
1600 ct=c->mtu-get_dma_residue(c->rxdma);
1601 if(ct<0)
1602 ct=2;
1603 c->dma_ready=0;
1604
1605
1606
1607
1608
1609
1610 if(ready)
1611 {
1612 c->dma_num^=1;
1613 set_dma_mode(c->rxdma, DMA_MODE_READ|0x10);
1614 set_dma_addr(c->rxdma, virt_to_bus(c->rx_buf[c->dma_num]));
1615 set_dma_count(c->rxdma, c->mtu);
1616 c->rxdma_on = 1;
1617 enable_dma(c->rxdma);
1618
1619
1620 write_zsreg(c, R0, RES_Rx_CRC);
1621 }
1622 else
1623
1624
1625 netdev_warn(c->netdevice, "DMA flip overrun!\n");
1626
1627 release_dma_lock(flags);
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637 skb = dev_alloc_skb(ct);
1638 if (skb == NULL) {
1639 c->netdevice->stats.rx_dropped++;
1640 netdev_warn(c->netdevice, "Memory squeeze\n");
1641 } else {
1642 skb_put(skb, ct);
1643 skb_copy_to_linear_data(skb, rxb, ct);
1644 c->netdevice->stats.rx_packets++;
1645 c->netdevice->stats.rx_bytes += ct;
1646 }
1647 c->dma_ready = 1;
1648 } else {
1649 RT_LOCK;
1650 skb = c->skb;
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664 ct=c->count;
1665
1666 c->skb = c->skb2;
1667 c->count = 0;
1668 c->max = c->mtu;
1669 if (c->skb) {
1670 c->dptr = c->skb->data;
1671 c->max = c->mtu;
1672 } else {
1673 c->count = 0;
1674 c->max = 0;
1675 }
1676 RT_UNLOCK;
1677
1678 c->skb2 = dev_alloc_skb(c->mtu);
1679 if (c->skb2 == NULL)
1680 netdev_warn(c->netdevice, "memory squeeze\n");
1681 else
1682 skb_put(c->skb2, c->mtu);
1683 c->netdevice->stats.rx_packets++;
1684 c->netdevice->stats.rx_bytes += ct;
1685 }
1686
1687
1688
1689 if (skb) {
1690 skb_trim(skb, ct);
1691 c->rx_function(c, skb);
1692 } else {
1693 c->netdevice->stats.rx_dropped++;
1694 netdev_err(c->netdevice, "Lost a frame\n");
1695 }
1696}
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706static inline int spans_boundary(struct sk_buff *skb)
1707{
1708 unsigned long a=(unsigned long)skb->data;
1709 a^=(a+skb->len);
1710 if(a&0x00010000)
1711 return 1;
1712 return 0;
1713}
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729netdev_tx_t z8530_queue_xmit(struct z8530_channel *c, struct sk_buff *skb)
1730{
1731 unsigned long flags;
1732
1733 netif_stop_queue(c->netdevice);
1734 if(c->tx_next_skb)
1735 return NETDEV_TX_BUSY;
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745 if(c->dma_tx && ((unsigned long)(virt_to_bus(skb->data+skb->len))>=16*1024*1024 || spans_boundary(skb)))
1746 {
1747
1748
1749
1750
1751
1752
1753
1754 c->tx_next_ptr=c->tx_dma_buf[c->tx_dma_used];
1755 c->tx_dma_used^=1;
1756 skb_copy_from_linear_data(skb, c->tx_next_ptr, skb->len);
1757 }
1758 else
1759 c->tx_next_ptr=skb->data;
1760 RT_LOCK;
1761 c->tx_next_skb=skb;
1762 RT_UNLOCK;
1763
1764 spin_lock_irqsave(c->lock, flags);
1765 z8530_tx_begin(c);
1766 spin_unlock_irqrestore(c->lock, flags);
1767
1768 return NETDEV_TX_OK;
1769}
1770
1771EXPORT_SYMBOL(z8530_queue_xmit);
1772
1773
1774
1775
1776static const char banner[] __initconst =
1777 KERN_INFO "Generic Z85C30/Z85230 interface driver v0.02\n";
1778
1779static int __init z85230_init_driver(void)
1780{
1781 printk(banner);
1782 return 0;
1783}
1784module_init(z85230_init_driver);
1785
1786static void __exit z85230_cleanup_driver(void)
1787{
1788}
1789module_exit(z85230_cleanup_driver);
1790
1791MODULE_AUTHOR("Red Hat Inc.");
1792MODULE_DESCRIPTION("Z85x30 synchronous driver core");
1793MODULE_LICENSE("GPL");
1794