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67#ifndef __iwl_prph_h__
68#define __iwl_prph_h__
69#include <linux/bitfield.h>
70
71
72
73
74
75#define PRPH_BASE (0x00000)
76#define PRPH_END (0xFFFFF)
77
78
79#define APMG_BASE (PRPH_BASE + 0x3000)
80#define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000)
81#define APMG_CLK_EN_REG (APMG_BASE + 0x0004)
82#define APMG_CLK_DIS_REG (APMG_BASE + 0x0008)
83#define APMG_PS_CTRL_REG (APMG_BASE + 0x000c)
84#define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010)
85#define APMG_RFKILL_REG (APMG_BASE + 0x0014)
86#define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c)
87#define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020)
88#define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058)
89#define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C)
90
91#define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001)
92#define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200)
93#define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800)
94
95#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000)
96#define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000)
97#define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000)
98#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000)
99#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000)
100#define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0)
101#define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060)
102
103#define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200)
104#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800)
105#define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000)
106
107#define APMG_RTC_INT_STT_RFKILL (0x10000000)
108
109
110#define DEVICE_SYSTEM_TIME_REG 0xA0206C
111
112
113#define DEVICE_SET_NMI_REG 0x00a01c30
114#define DEVICE_SET_NMI_VAL_DRV BIT(7)
115
116#define UREG_NIC_SET_NMI_DRIVER 0x00a05c10
117#define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER_MSK 0xff000000
118
119
120#define SHR_BASE 0x00a10000
121
122
123#define SHR_APMG_GP1_REG 0x01dc
124#define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG)
125#define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004
126#define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000
127
128
129#define SHR_APMG_DL_CFG_REG 0x01c4
130#define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG)
131#define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0
132#define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080
133#define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100
134
135
136#define SHR_APMG_XTAL_CFG_REG 0x1c0
137#define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000
138
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142
143#define RELEASE_CPU_RESET (0x300C)
144#define RELEASE_CPU_RESET_BIT BIT(24)
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149
150#define SHR_MISC_WFM_DTS_EN (0x00a10024)
151#define DTSC_CFG_MODE (0x00a10604)
152#define DTSC_VREF_AVG (0x00a10648)
153#define DTSC_VREF5_AVG (0x00a1064c)
154#define DTSC_CFG_MODE_PERIODIC (0x2)
155#define DTSC_PTAT_AVG (0x00a10650)
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228
229#define SCD_MEM_LOWER_BOUND (0x0000)
230
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234
235
236#define SCD_WIN_SIZE 64
237#define SCD_FRAME_LIMIT 64
238
239#define SCD_TXFIFO_POS_TID (0)
240#define SCD_TXFIFO_POS_RA (4)
241#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
242
243
244#define SCD_QUEUE_STTS_REG_POS_TXF (0)
245#define SCD_QUEUE_STTS_REG_POS_ACTIVE (3)
246#define SCD_QUEUE_STTS_REG_POS_WSL (4)
247#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19)
248#define SCD_QUEUE_STTS_REG_MSK (0x017F0000)
249
250#define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00)
251#define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000)
252#define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v)
253
254#define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F)
255#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000)
256#define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v)
257
258#define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0)
259#define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18)
260
261
262#define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600)
263#define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
264
265
266#define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0)
267#define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
268
269
270#define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0)
271#define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808)
272
273#define SCD_CONTEXT_QUEUE_OFFSET(x)\
274 (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8))
275
276#define SCD_TX_STTS_QUEUE_OFFSET(x)\
277 (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16))
278
279#define SCD_TRANS_TBL_OFFSET_QUEUE(x) \
280 ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc)
281
282#define SCD_BASE (PRPH_BASE + 0xa02c00)
283
284#define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0)
285#define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8)
286#define SCD_AIT (SCD_BASE + 0x0c)
287#define SCD_TXFACT (SCD_BASE + 0x10)
288#define SCD_ACTIVE (SCD_BASE + 0x14)
289#define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8)
290#define SCD_CHAINEXT_EN (SCD_BASE + 0x244)
291#define SCD_AGGR_SEL (SCD_BASE + 0x248)
292#define SCD_INTERRUPT_MASK (SCD_BASE + 0x108)
293#define SCD_GP_CTRL (SCD_BASE + 0x1a8)
294#define SCD_EN_CTRL (SCD_BASE + 0x254)
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298
299#define OSC_CLK (0xa04068)
300#define OSC_CLK_FORCE_CONTROL (0x8)
301
302#define FH_UCODE_LOAD_STATUS (0x1AF0)
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308
309#define UREG_UCODE_LOAD_STATUS (0xa05c40)
310#define UREG_CPU_INIT_RUN (0xa05c44)
311
312#define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78)
313#define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C)
314
315#define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000)
316#define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400)
317
318#define LMAC2_PRPH_OFFSET (0x100000)
319
320
321#define RXF_SIZE_ADDR (0xa00c88)
322#define RXF_RD_D_SPACE (0xa00c40)
323#define RXF_RD_WR_PTR (0xa00c50)
324#define RXF_RD_RD_PTR (0xa00c54)
325#define RXF_RD_FENCE_PTR (0xa00c4c)
326#define RXF_SET_FENCE_MODE (0xa00c14)
327#define RXF_LD_WR2FENCE (0xa00c1c)
328#define RXF_FIFO_RD_FENCE_INC (0xa00c68)
329#define RXF_SIZE_BYTE_CND_POS (7)
330#define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS)
331#define RXF_DIFF_FROM_PREV (0x200)
332
333#define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10)
334#define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c)
335
336
337#define TXF_FIFO_ITEM_CNT (0xa00438)
338#define TXF_WR_PTR (0xa00414)
339#define TXF_RD_PTR (0xa00410)
340#define TXF_FENCE_PTR (0xa00418)
341#define TXF_LOCK_FENCE (0xa00424)
342#define TXF_LARC_NUM (0xa0043c)
343#define TXF_READ_MODIFY_DATA (0xa00448)
344#define TXF_READ_MODIFY_ADDR (0xa0044c)
345
346
347#define TXF_CPU2_FIFO_ITEM_CNT (0xA00538)
348#define TXF_CPU2_WR_PTR (0xA00514)
349#define TXF_CPU2_RD_PTR (0xA00510)
350#define TXF_CPU2_FENCE_PTR (0xA00518)
351#define TXF_CPU2_LOCK_FENCE (0xA00524)
352#define TXF_CPU2_NUM (0xA0053C)
353#define TXF_CPU2_READ_MODIFY_DATA (0xA00548)
354#define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C)
355
356
357#define RSP_RADIO_CMD (0xa02804)
358#define RSP_RADIO_RDDAT (0xa02814)
359#define RADIO_RSP_ADDR_POS (6)
360#define RADIO_RSP_RD_CMD (3)
361
362
363#define MON_BUFF_SAMPLE_CTL (0xa03c00)
364#define MON_BUFF_BASE_ADDR (0xa03c3c)
365#define MON_BUFF_END_ADDR (0xa03c40)
366#define MON_BUFF_WRPTR (0xa03c44)
367#define MON_BUFF_CYCLE_CNT (0xa03c48)
368
369#define MON_DMARB_RD_CTL_ADDR (0xa03c60)
370#define MON_DMARB_RD_DATA_ADDR (0xa03c5c)
371
372#define DBGC_IN_SAMPLE (0xa03c00)
373#define DBGC_OUT_CTRL (0xa03c0c)
374
375
376#define WFPM_PS_CTL_CLR 0xA0300C
377#define WFMP_MAC_ADDR_0 0xA03080
378#define WFMP_MAC_ADDR_1 0xA03084
379#define LMPM_PMG_EN 0xA01CEC
380#define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078
381#define RFIC_REG_RD 0xAD0470
382#define WFPM_CTRL_REG 0xA03030
383#define WFPM_GP2 0xA030B4
384enum {
385 ENABLE_WFPM = BIT(31),
386 WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,
387};
388
389#define AUX_MISC_REG 0xA200B0
390enum {
391 HW_STEP_LOCATION_BITS = 24,
392};
393
394#define AUX_MISC_MASTER1_EN 0xA20818
395enum aux_misc_master1_en {
396 AUX_MISC_MASTER1_EN_SBE_MSK = 0x1,
397};
398
399#define AUX_MISC_MASTER1_SMPHR_STATUS 0xA20800
400#define RSA_ENABLE 0xA24B08
401#define PREG_AUX_BUS_WPROT_0 0xA04CC0
402#define SB_CPU_1_STATUS 0xA01E30
403#define SB_CPU_2_STATUS 0xA01E34
404#define UMAG_SB_CPU_1_STATUS 0xA038C0
405#define UMAG_SB_CPU_2_STATUS 0xA038C4
406#define UMAG_GEN_HW_STATUS 0xA038C8
407
408
409enum {
410 UMAG_GEN_HW_IS_FPGA = BIT(1),
411};
412
413
414#define LMPM_CHICK 0xA01FF8
415enum {
416 LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0),
417};
418
419
420#define LMPM_PAGE_PASS_NOTIF 0xA03824
421enum {
422 LMPM_PAGE_PASS_NOTIF_POS = BIT(20),
423};
424
425#define UREG_CHICK (0xA05C00)
426#define UREG_CHICK_MSI_ENABLE BIT(24)
427#define UREG_CHICK_MSIX_ENABLE BIT(25)
428#endif
429