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17#include <linux/delay.h>
18#include "mt76x2.h"
19#include "mt76x2_eeprom.h"
20#include "mt76x2_mcu.h"
21
22struct mt76x2_reg_pair {
23 u32 reg;
24 u32 value;
25};
26
27static bool
28mt76x2_wait_for_mac(struct mt76x2_dev *dev)
29{
30 int i;
31
32 for (i = 0; i < 500; i++) {
33 switch (mt76_rr(dev, MT_MAC_CSR0)) {
34 case 0:
35 case ~0:
36 break;
37 default:
38 return true;
39 }
40 usleep_range(5000, 10000);
41 }
42
43 return false;
44}
45
46static bool
47wait_for_wpdma(struct mt76x2_dev *dev)
48{
49 return mt76_poll(dev, MT_WPDMA_GLO_CFG,
50 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
51 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
52 0, 1000);
53}
54
55static void
56mt76x2_mac_pbf_init(struct mt76x2_dev *dev)
57{
58 u32 val;
59
60 val = MT_PBF_SYS_CTRL_MCU_RESET |
61 MT_PBF_SYS_CTRL_DMA_RESET |
62 MT_PBF_SYS_CTRL_MAC_RESET |
63 MT_PBF_SYS_CTRL_PBF_RESET |
64 MT_PBF_SYS_CTRL_ASY_RESET;
65
66 mt76_set(dev, MT_PBF_SYS_CTRL, val);
67 mt76_clear(dev, MT_PBF_SYS_CTRL, val);
68
69 mt76_wr(dev, MT_PBF_TX_MAX_PCNT, 0xefef3f1f);
70 mt76_wr(dev, MT_PBF_RX_MAX_PCNT, 0xfebf);
71}
72
73static void
74mt76x2_write_reg_pairs(struct mt76x2_dev *dev,
75 const struct mt76x2_reg_pair *data, int len)
76{
77 while (len > 0) {
78 mt76_wr(dev, data->reg, data->value);
79 len--;
80 data++;
81 }
82}
83
84static void
85mt76_write_mac_initvals(struct mt76x2_dev *dev)
86{
87#define DEFAULT_PROT_CFG \
88 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
89 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
90 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
91 MT_PROT_CFG_RTS_THRESH)
92
93#define DEFAULT_PROT_CFG_20 \
94 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
95 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
96 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
97 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
98
99#define DEFAULT_PROT_CFG_40 \
100 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
101 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
102 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
103 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
104
105 static const struct mt76x2_reg_pair vals[] = {
106
107 { MT_PBF_SYS_CTRL, 0x00080c00 },
108 { MT_PBF_CFG, 0x1efebcff },
109 { MT_FCE_PSE_CTRL, 0x00000001 },
110 { MT_MAC_SYS_CTRL, 0x0000000c },
111 { MT_MAX_LEN_CFG, 0x003e3f00 },
112 { MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
113 { MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
114 { MT_XIFS_TIME_CFG, 0x33a40d0a },
115 { MT_BKOFF_SLOT_CFG, 0x00000209 },
116 { MT_TBTT_SYNC_CFG, 0x00422010 },
117 { MT_PWR_PIN_CFG, 0x00000000 },
118 { 0x1238, 0x001700c8 },
119 { MT_TX_SW_CFG0, 0x00101001 },
120 { MT_TX_SW_CFG1, 0x00010000 },
121 { MT_TX_SW_CFG2, 0x00000000 },
122 { MT_TXOP_CTRL_CFG, 0x0400583f },
123 { MT_TX_RTS_CFG, 0x00100020 },
124 { MT_TX_TIMEOUT_CFG, 0x000a2290 },
125 { MT_TX_RETRY_CFG, 0x47f01f0f },
126 { MT_EXP_ACK_TIME, 0x002c00dc },
127 { MT_TX_PROT_CFG6, 0xe3f42004 },
128 { MT_TX_PROT_CFG7, 0xe3f42084 },
129 { MT_TX_PROT_CFG8, 0xe3f42104 },
130 { MT_PIFS_TX_CFG, 0x00060fff },
131 { MT_RX_FILTR_CFG, 0x00015f97 },
132 { MT_LEGACY_BASIC_RATE, 0x0000017f },
133 { MT_HT_BASIC_RATE, 0x00004003 },
134 { MT_PN_PAD_MODE, 0x00000003 },
135 { MT_TXOP_HLDR_ET, 0x00000002 },
136 { 0xa44, 0x00000000 },
137 { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
138 { MT_TSO_CTRL, 0x00000000 },
139 { MT_AUX_CLK_CFG, 0x00000000 },
140 { MT_DACCLK_EN_DLY_CFG, 0x00000000 },
141 { MT_TX_ALC_CFG_4, 0x00000000 },
142 { MT_TX_ALC_VGA3, 0x00000000 },
143 { MT_TX_PWR_CFG_0, 0x3a3a3a3a },
144 { MT_TX_PWR_CFG_1, 0x3a3a3a3a },
145 { MT_TX_PWR_CFG_2, 0x3a3a3a3a },
146 { MT_TX_PWR_CFG_3, 0x3a3a3a3a },
147 { MT_TX_PWR_CFG_4, 0x3a3a3a3a },
148 { MT_TX_PWR_CFG_7, 0x3a3a3a3a },
149 { MT_TX_PWR_CFG_8, 0x0000003a },
150 { MT_TX_PWR_CFG_9, 0x0000003a },
151 { MT_EFUSE_CTRL, 0x0000d000 },
152 { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
153 { MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
154 { MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
155 { MT_TX_SW_CFG3, 0x00000004 },
156 { MT_HT_FBK_TO_LEGACY, 0x00001818 },
157 { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
158 { MT_PROT_AUTO_TX_CFG, 0x00830083 },
159 { MT_HT_CTRL_CFG, 0x000001ff },
160 };
161 struct mt76x2_reg_pair prot_vals[] = {
162 { MT_CCK_PROT_CFG, DEFAULT_PROT_CFG },
163 { MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG },
164 { MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
165 { MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
166 { MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
167 { MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
168 };
169
170 mt76x2_write_reg_pairs(dev, vals, ARRAY_SIZE(vals));
171 mt76x2_write_reg_pairs(dev, prot_vals, ARRAY_SIZE(prot_vals));
172}
173
174static void
175mt76x2_fixup_xtal(struct mt76x2_dev *dev)
176{
177 u16 eep_val;
178 s8 offset = 0;
179
180 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_2);
181
182 offset = eep_val & 0x7f;
183 if ((eep_val & 0xff) == 0xff)
184 offset = 0;
185 else if (eep_val & 0x80)
186 offset = 0 - offset;
187
188 eep_val >>= 8;
189 if (eep_val == 0x00 || eep_val == 0xff) {
190 eep_val = mt76x2_eeprom_get(dev, MT_EE_XTAL_TRIM_1);
191 eep_val &= 0xff;
192
193 if (eep_val == 0x00 || eep_val == 0xff)
194 eep_val = 0x14;
195 }
196
197 eep_val &= 0x7f;
198 mt76_rmw_field(dev, MT_XO_CTRL5, MT_XO_CTRL5_C2_VAL, eep_val + offset);
199 mt76_set(dev, MT_XO_CTRL6, MT_XO_CTRL6_C2_CTRL);
200
201 eep_val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_2);
202 switch (FIELD_GET(MT_EE_NIC_CONF_2_XTAL_OPTION, eep_val)) {
203 case 0:
204 mt76_wr(dev, MT_XO_CTRL7, 0x5c1fee80);
205 break;
206 case 1:
207 mt76_wr(dev, MT_XO_CTRL7, 0x5c1feed0);
208 break;
209 default:
210 break;
211 }
212}
213
214static void
215mt76x2_init_beacon_offsets(struct mt76x2_dev *dev)
216{
217 u16 base = MT_BEACON_BASE;
218 u32 regs[4] = {};
219 int i;
220
221 for (i = 0; i < 16; i++) {
222 u16 addr = dev->beacon_offsets[i];
223
224 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
225 }
226
227 for (i = 0; i < 4; i++)
228 mt76_wr(dev, MT_BCN_OFFSET(i), regs[i]);
229}
230
231static int mt76x2_mac_reset(struct mt76x2_dev *dev, bool hard)
232{
233 static const u8 null_addr[ETH_ALEN] = {};
234 const u8 *macaddr = dev->mt76.macaddr;
235 u32 val;
236 int i, k;
237
238 if (!mt76x2_wait_for_mac(dev))
239 return -ETIMEDOUT;
240
241 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
242
243 val &= ~(MT_WPDMA_GLO_CFG_TX_DMA_EN |
244 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
245 MT_WPDMA_GLO_CFG_RX_DMA_EN |
246 MT_WPDMA_GLO_CFG_RX_DMA_BUSY |
247 MT_WPDMA_GLO_CFG_DMA_BURST_SIZE);
248 val |= FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3);
249
250 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
251
252 mt76x2_mac_pbf_init(dev);
253 mt76_write_mac_initvals(dev);
254 mt76x2_fixup_xtal(dev);
255
256 mt76_clear(dev, MT_MAC_SYS_CTRL,
257 MT_MAC_SYS_CTRL_RESET_CSR |
258 MT_MAC_SYS_CTRL_RESET_BBP);
259
260 if (is_mt7612(dev))
261 mt76_clear(dev, MT_COEXCFG0, MT_COEXCFG0_COEX_EN);
262
263 mt76_set(dev, MT_EXT_CCA_CFG, 0x0000f000);
264 mt76_clear(dev, MT_TX_ALC_CFG_4, BIT(31));
265
266 mt76_wr(dev, MT_RF_BYPASS_0, 0x06000000);
267 mt76_wr(dev, MT_RF_SETTING_0, 0x08800000);
268 usleep_range(5000, 10000);
269 mt76_wr(dev, MT_RF_BYPASS_0, 0x00000000);
270
271 mt76_wr(dev, MT_MCU_CLOCK_CTL, 0x1401);
272 mt76_clear(dev, MT_FCE_L2_STUFF, MT_FCE_L2_STUFF_WR_MPDU_LEN_EN);
273
274 mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(macaddr));
275 mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(macaddr + 4));
276
277 mt76_wr(dev, MT_MAC_BSSID_DW0, get_unaligned_le32(macaddr));
278 mt76_wr(dev, MT_MAC_BSSID_DW1, get_unaligned_le16(macaddr + 4) |
279 FIELD_PREP(MT_MAC_BSSID_DW1_MBSS_MODE, 3) |
280 MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT);
281
282
283 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_PRE_TBTT,
284 8 << 4);
285 mt76_rmw_field(dev, MT_INT_TIMER_CFG, MT_INT_TIMER_CFG_GP_TIMER,
286 MT_DFS_GP_INTERVAL);
287 mt76_wr(dev, MT_INT_TIMER_EN, 0);
288
289 mt76_wr(dev, MT_BCN_BYPASS_MASK, 0xffff);
290 if (!hard)
291 return 0;
292
293 for (i = 0; i < 256 / 32; i++)
294 mt76_wr(dev, MT_WCID_DROP_BASE + i * 4, 0);
295
296 for (i = 0; i < 256; i++)
297 mt76x2_mac_wcid_setup(dev, i, 0, NULL);
298
299 for (i = 0; i < MT_MAX_VIFS; i++)
300 mt76x2_mac_wcid_setup(dev, MT_VIF_WCID(i), i, NULL);
301
302 for (i = 0; i < 16; i++)
303 for (k = 0; k < 4; k++)
304 mt76x2_mac_shared_key_setup(dev, i, k, NULL);
305
306 for (i = 0; i < 8; i++) {
307 mt76x2_mac_set_bssid(dev, i, null_addr);
308 mt76x2_mac_set_beacon(dev, i, NULL);
309 }
310
311 for (i = 0; i < 16; i++)
312 mt76_rr(dev, MT_TX_STAT_FIFO);
313
314 mt76_wr(dev, MT_CH_TIME_CFG,
315 MT_CH_TIME_CFG_TIMER_EN |
316 MT_CH_TIME_CFG_TX_AS_BUSY |
317 MT_CH_TIME_CFG_RX_AS_BUSY |
318 MT_CH_TIME_CFG_NAV_AS_BUSY |
319 MT_CH_TIME_CFG_EIFS_AS_BUSY |
320 FIELD_PREP(MT_CH_TIME_CFG_CH_TIMER_CLR, 1));
321
322 mt76x2_init_beacon_offsets(dev);
323
324 mt76x2_set_tx_ackto(dev);
325
326 return 0;
327}
328
329int mt76x2_mac_start(struct mt76x2_dev *dev)
330{
331 int i;
332
333 for (i = 0; i < 16; i++)
334 mt76_rr(dev, MT_TX_AGG_CNT(i));
335
336 for (i = 0; i < 16; i++)
337 mt76_rr(dev, MT_TX_STAT_FIFO);
338
339 memset(dev->aggr_stats, 0, sizeof(dev->aggr_stats));
340
341 mt76_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
342 wait_for_wpdma(dev);
343 usleep_range(50, 100);
344
345 mt76_set(dev, MT_WPDMA_GLO_CFG,
346 MT_WPDMA_GLO_CFG_TX_DMA_EN |
347 MT_WPDMA_GLO_CFG_RX_DMA_EN);
348
349 mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
350
351 mt76_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
352
353 mt76_wr(dev, MT_MAC_SYS_CTRL,
354 MT_MAC_SYS_CTRL_ENABLE_TX |
355 MT_MAC_SYS_CTRL_ENABLE_RX);
356
357 mt76x2_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL |
358 MT_INT_TX_STAT);
359
360 return 0;
361}
362
363void mt76x2_mac_stop(struct mt76x2_dev *dev, bool force)
364{
365 bool stopped = false;
366 u32 rts_cfg;
367 int i;
368
369 mt76_wr(dev, MT_MAC_SYS_CTRL, 0);
370
371 rts_cfg = mt76_rr(dev, MT_TX_RTS_CFG);
372 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg & ~MT_TX_RTS_CFG_RETRY_LIMIT);
373
374
375 for (i = 0; i < 300; i++) {
376 if ((mt76_rr(dev, MT_MAC_STATUS) &
377 (MT_MAC_STATUS_RX | MT_MAC_STATUS_TX)) ||
378 mt76_rr(dev, MT_BBP(IBI, 12))) {
379 udelay(1);
380 continue;
381 }
382
383 stopped = true;
384 break;
385 }
386
387 if (force && !stopped) {
388 mt76_set(dev, MT_BBP(CORE, 4), BIT(1));
389 mt76_clear(dev, MT_BBP(CORE, 4), BIT(1));
390
391 mt76_set(dev, MT_BBP(CORE, 4), BIT(0));
392 mt76_clear(dev, MT_BBP(CORE, 4), BIT(0));
393 }
394
395 mt76_wr(dev, MT_TX_RTS_CFG, rts_cfg);
396}
397
398void mt76x2_mac_resume(struct mt76x2_dev *dev)
399{
400 mt76_wr(dev, MT_MAC_SYS_CTRL,
401 MT_MAC_SYS_CTRL_ENABLE_TX |
402 MT_MAC_SYS_CTRL_ENABLE_RX);
403}
404
405static void
406mt76x2_power_on_rf_patch(struct mt76x2_dev *dev)
407{
408 mt76_set(dev, 0x10130, BIT(0) | BIT(16));
409 udelay(1);
410
411 mt76_clear(dev, 0x1001c, 0xff);
412 mt76_set(dev, 0x1001c, 0x30);
413
414 mt76_wr(dev, 0x10014, 0x484f);
415 udelay(1);
416
417 mt76_set(dev, 0x10130, BIT(17));
418 udelay(125);
419
420 mt76_clear(dev, 0x10130, BIT(16));
421 udelay(50);
422
423 mt76_set(dev, 0x1014c, BIT(19) | BIT(20));
424}
425
426static void
427mt76x2_power_on_rf(struct mt76x2_dev *dev, int unit)
428{
429 int shift = unit ? 8 : 0;
430
431
432 mt76_set(dev, 0x10130, BIT(0) << shift);
433 udelay(10);
434
435
436 mt76_set(dev, 0x10130, (BIT(1) | BIT(3) | BIT(4) | BIT(5)) << shift);
437 udelay(10);
438
439
440 mt76_clear(dev, 0x10130, BIT(2) << shift);
441 udelay(10);
442
443 mt76x2_power_on_rf_patch(dev);
444
445 mt76_set(dev, 0x530, 0xf);
446}
447
448static void
449mt76x2_power_on(struct mt76x2_dev *dev)
450{
451 u32 val;
452
453
454 mt76_set(dev, MT_WLAN_MTC_CTRL, MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP);
455
456 val = MT_WLAN_MTC_CTRL_STATE_UP |
457 MT_WLAN_MTC_CTRL_PWR_ACK |
458 MT_WLAN_MTC_CTRL_PWR_ACK_S;
459
460 mt76_poll(dev, MT_WLAN_MTC_CTRL, val, val, 1000);
461
462 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0x7f << 16);
463 udelay(10);
464
465 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
466 udelay(10);
467
468 mt76_set(dev, MT_WLAN_MTC_CTRL, 0xf << 24);
469 mt76_clear(dev, MT_WLAN_MTC_CTRL, 0xfff);
470
471
472 mt76_clear(dev, 0x11204, BIT(3));
473
474
475 mt76_set(dev, 0x10080, BIT(0));
476
477
478 mt76_clear(dev, 0x10064, BIT(18));
479
480 mt76x2_power_on_rf(dev, 0);
481 mt76x2_power_on_rf(dev, 1);
482}
483
484void mt76x2_set_tx_ackto(struct mt76x2_dev *dev)
485{
486 u8 ackto, sifs, slottime = dev->slottime;
487
488
489 slottime += 3 * dev->coverage_class;
490 mt76_rmw_field(dev, MT_BKOFF_SLOT_CFG,
491 MT_BKOFF_SLOT_CFG_SLOTTIME, slottime);
492
493 sifs = mt76_get_field(dev, MT_XIFS_TIME_CFG,
494 MT_XIFS_TIME_CFG_OFDM_SIFS);
495
496 ackto = slottime + sifs;
497 mt76_rmw_field(dev, MT_TX_TIMEOUT_CFG,
498 MT_TX_TIMEOUT_CFG_ACKTO, ackto);
499}
500
501static void
502mt76x2_set_wlan_state(struct mt76x2_dev *dev, bool enable)
503{
504 u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
505
506 if (enable)
507 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
508 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
509 else
510 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
511 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
512
513 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
514 udelay(20);
515}
516
517static void
518mt76x2_reset_wlan(struct mt76x2_dev *dev, bool enable)
519{
520 u32 val;
521
522 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
523
524 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
525
526 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
527 val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
528 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
529 udelay(20);
530
531 val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
532 }
533
534 mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
535 udelay(20);
536
537 mt76x2_set_wlan_state(dev, enable);
538}
539
540int mt76x2_init_hardware(struct mt76x2_dev *dev)
541{
542 static const u16 beacon_offsets[16] = {
543
544 0xc000,
545 0xc400,
546 0xc800,
547 0xcc00,
548 0xd000,
549 0xd400,
550 0xd800,
551 0xdc00,
552
553
554 0xc000,
555 0xc000,
556 0xc000,
557 0xc000,
558 0xc000,
559 0xc000,
560 0xc000,
561 0xc000,
562 };
563 u32 val;
564 int ret;
565
566 dev->beacon_offsets = beacon_offsets;
567 tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet,
568 (unsigned long) dev);
569
570 dev->chainmask = 0x202;
571 dev->global_wcid.idx = 255;
572 dev->global_wcid.hw_key_idx = -1;
573 dev->slottime = 9;
574
575 val = mt76_rr(dev, MT_WPDMA_GLO_CFG);
576 val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE |
577 MT_WPDMA_GLO_CFG_BIG_ENDIAN |
578 MT_WPDMA_GLO_CFG_HDR_SEG_LEN;
579 val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE;
580 mt76_wr(dev, MT_WPDMA_GLO_CFG, val);
581
582 mt76x2_reset_wlan(dev, true);
583 mt76x2_power_on(dev);
584
585 ret = mt76x2_eeprom_init(dev);
586 if (ret)
587 return ret;
588
589 ret = mt76x2_mac_reset(dev, true);
590 if (ret)
591 return ret;
592
593 dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG);
594
595 ret = mt76x2_dma_init(dev);
596 if (ret)
597 return ret;
598
599 set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state);
600 ret = mt76x2_mac_start(dev);
601 if (ret)
602 return ret;
603
604 ret = mt76x2_mcu_init(dev);
605 if (ret)
606 return ret;
607
608 mt76x2_mac_stop(dev, false);
609
610 return 0;
611}
612
613void mt76x2_stop_hardware(struct mt76x2_dev *dev)
614{
615 cancel_delayed_work_sync(&dev->cal_work);
616 cancel_delayed_work_sync(&dev->mac_work);
617 mt76x2_mcu_set_radio_state(dev, false);
618 mt76x2_mac_stop(dev, false);
619}
620
621void mt76x2_cleanup(struct mt76x2_dev *dev)
622{
623 tasklet_disable(&dev->dfs_pd.dfs_tasklet);
624 tasklet_disable(&dev->pre_tbtt_tasklet);
625 mt76x2_stop_hardware(dev);
626 mt76x2_dma_cleanup(dev);
627 mt76x2_mcu_cleanup(dev);
628}
629
630struct mt76x2_dev *mt76x2_alloc_device(struct device *pdev)
631{
632 static const struct mt76_driver_ops drv_ops = {
633 .txwi_size = sizeof(struct mt76x2_txwi),
634 .update_survey = mt76x2_update_channel,
635 .tx_prepare_skb = mt76x2_tx_prepare_skb,
636 .tx_complete_skb = mt76x2_tx_complete_skb,
637 .rx_skb = mt76x2_queue_rx_skb,
638 .rx_poll_complete = mt76x2_rx_poll_complete,
639 .sta_ps = mt76x2_sta_ps,
640 };
641 struct mt76x2_dev *dev;
642 struct mt76_dev *mdev;
643
644 mdev = mt76_alloc_device(sizeof(*dev), &mt76x2_ops);
645 if (!mdev)
646 return NULL;
647
648 dev = container_of(mdev, struct mt76x2_dev, mt76);
649 mdev->dev = pdev;
650 mdev->drv = &drv_ops;
651 mutex_init(&dev->mutex);
652 spin_lock_init(&dev->irq_lock);
653
654 return dev;
655}
656
657static void mt76x2_regd_notifier(struct wiphy *wiphy,
658 struct regulatory_request *request)
659{
660 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
661 struct mt76x2_dev *dev = hw->priv;
662
663 mt76x2_dfs_set_domain(dev, request->dfs_region);
664}
665
666#define CCK_RATE(_idx, _rate) { \
667 .bitrate = _rate, \
668 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
669 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
670 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
671}
672
673#define OFDM_RATE(_idx, _rate) { \
674 .bitrate = _rate, \
675 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
676 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
677}
678
679static struct ieee80211_rate mt76x2_rates[] = {
680 CCK_RATE(0, 10),
681 CCK_RATE(1, 20),
682 CCK_RATE(2, 55),
683 CCK_RATE(3, 110),
684 OFDM_RATE(0, 60),
685 OFDM_RATE(1, 90),
686 OFDM_RATE(2, 120),
687 OFDM_RATE(3, 180),
688 OFDM_RATE(4, 240),
689 OFDM_RATE(5, 360),
690 OFDM_RATE(6, 480),
691 OFDM_RATE(7, 540),
692};
693
694static const struct ieee80211_iface_limit if_limits[] = {
695 {
696 .max = 1,
697 .types = BIT(NL80211_IFTYPE_ADHOC)
698 }, {
699 .max = 8,
700 .types = BIT(NL80211_IFTYPE_STATION) |
701#ifdef CONFIG_MAC80211_MESH
702 BIT(NL80211_IFTYPE_MESH_POINT) |
703#endif
704 BIT(NL80211_IFTYPE_AP)
705 },
706};
707
708static const struct ieee80211_iface_combination if_comb[] = {
709 {
710 .limits = if_limits,
711 .n_limits = ARRAY_SIZE(if_limits),
712 .max_interfaces = 8,
713 .num_different_channels = 1,
714 .beacon_int_infra_match = true,
715 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) |
716 BIT(NL80211_CHAN_WIDTH_20) |
717 BIT(NL80211_CHAN_WIDTH_40) |
718 BIT(NL80211_CHAN_WIDTH_80),
719 }
720};
721
722static void mt76x2_led_set_config(struct mt76_dev *mt76, u8 delay_on,
723 u8 delay_off)
724{
725 struct mt76x2_dev *dev = container_of(mt76, struct mt76x2_dev,
726 mt76);
727 u32 val;
728
729 val = MT_LED_STATUS_DURATION(0xff) |
730 MT_LED_STATUS_OFF(delay_off) |
731 MT_LED_STATUS_ON(delay_on);
732
733 mt76_wr(dev, MT_LED_S0(mt76->led_pin), val);
734 mt76_wr(dev, MT_LED_S1(mt76->led_pin), val);
735
736 val = MT_LED_CTRL_REPLAY(mt76->led_pin) |
737 MT_LED_CTRL_KICK(mt76->led_pin);
738 if (mt76->led_al)
739 val |= MT_LED_CTRL_POLARITY(mt76->led_pin);
740 mt76_wr(dev, MT_LED_CTRL, val);
741}
742
743static int mt76x2_led_set_blink(struct led_classdev *led_cdev,
744 unsigned long *delay_on,
745 unsigned long *delay_off)
746{
747 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
748 led_cdev);
749 u8 delta_on, delta_off;
750
751 delta_off = max_t(u8, *delay_off / 10, 1);
752 delta_on = max_t(u8, *delay_on / 10, 1);
753
754 mt76x2_led_set_config(mt76, delta_on, delta_off);
755 return 0;
756}
757
758static void mt76x2_led_set_brightness(struct led_classdev *led_cdev,
759 enum led_brightness brightness)
760{
761 struct mt76_dev *mt76 = container_of(led_cdev, struct mt76_dev,
762 led_cdev);
763
764 if (!brightness)
765 mt76x2_led_set_config(mt76, 0, 0xff);
766 else
767 mt76x2_led_set_config(mt76, 0xff, 0);
768}
769
770static void
771mt76x2_init_txpower(struct mt76x2_dev *dev,
772 struct ieee80211_supported_band *sband)
773{
774 struct ieee80211_channel *chan;
775 struct mt76x2_tx_power_info txp;
776 struct mt76_rate_power t = {};
777 int target_power;
778 int i;
779
780 for (i = 0; i < sband->n_channels; i++) {
781 chan = &sband->channels[i];
782
783 mt76x2_get_power_info(dev, &txp, chan);
784
785 target_power = max_t(int, (txp.chain[0].target_power +
786 txp.chain[0].delta),
787 (txp.chain[1].target_power +
788 txp.chain[1].delta));
789
790 mt76x2_get_rate_power(dev, &t, chan);
791
792 chan->max_power = mt76x2_get_max_rate_power(&t) +
793 target_power;
794 chan->max_power /= 2;
795
796
797 chan->max_power += 3;
798 }
799}
800
801int mt76x2_register_device(struct mt76x2_dev *dev)
802{
803 struct ieee80211_hw *hw = mt76_hw(dev);
804 struct wiphy *wiphy = hw->wiphy;
805 void *status_fifo;
806 int fifo_size;
807 int i, ret;
808
809 fifo_size = roundup_pow_of_two(32 * sizeof(struct mt76x2_tx_status));
810 status_fifo = devm_kzalloc(dev->mt76.dev, fifo_size, GFP_KERNEL);
811 if (!status_fifo)
812 return -ENOMEM;
813
814 kfifo_init(&dev->txstatus_fifo, status_fifo, fifo_size);
815
816 ret = mt76x2_init_hardware(dev);
817 if (ret)
818 return ret;
819
820 hw->queues = 4;
821 hw->max_rates = 1;
822 hw->max_report_rates = 7;
823 hw->max_rate_tries = 1;
824 hw->extra_tx_headroom = 2;
825
826 hw->sta_data_size = sizeof(struct mt76x2_sta);
827 hw->vif_data_size = sizeof(struct mt76x2_vif);
828
829 for (i = 0; i < ARRAY_SIZE(dev->macaddr_list); i++) {
830 u8 *addr = dev->macaddr_list[i].addr;
831
832 memcpy(addr, dev->mt76.macaddr, ETH_ALEN);
833
834 if (!i)
835 continue;
836
837 addr[0] |= BIT(1);
838 addr[0] ^= ((i - 1) << 2);
839 }
840 wiphy->addresses = dev->macaddr_list;
841 wiphy->n_addresses = ARRAY_SIZE(dev->macaddr_list);
842
843 wiphy->iface_combinations = if_comb;
844 wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
845
846 wiphy->reg_notifier = mt76x2_regd_notifier;
847
848 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS);
849
850 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
851 ieee80211_hw_set(hw, SUPPORTS_REORDERING_BUFFER);
852
853 INIT_DELAYED_WORK(&dev->cal_work, mt76x2_phy_calibrate);
854 INIT_DELAYED_WORK(&dev->mac_work, mt76x2_mac_work);
855
856 dev->mt76.sband_2g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
857 dev->mt76.sband_5g.sband.ht_cap.cap |= IEEE80211_HT_CAP_LDPC_CODING;
858
859 mt76x2_dfs_init_detector(dev);
860
861
862 dev->mt76.led_cdev.brightness_set = mt76x2_led_set_brightness;
863 dev->mt76.led_cdev.blink_set = mt76x2_led_set_blink;
864
865
866 dev->mt76.antenna_mask = 3;
867
868 ret = mt76_register_device(&dev->mt76, true, mt76x2_rates,
869 ARRAY_SIZE(mt76x2_rates));
870 if (ret)
871 goto fail;
872
873 mt76x2_init_debugfs(dev);
874 mt76x2_init_txpower(dev, &dev->mt76.sband_2g.sband);
875 mt76x2_init_txpower(dev, &dev->mt76.sband_5g.sband);
876
877 return 0;
878
879fail:
880 mt76x2_stop_hardware(dev);
881 return ret;
882}
883
884
885
