LXR linux/drivers/pci/pci.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef DRIVERS_PCI_H
   3#define DRIVERS_PCI_H
   4
   5#define PCI_FIND_CAP_TTL        48
   6
   7#define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
   8
   9extern const unsigned char pcie_link_speed[];
  10
  11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  12
  13/* Functions internal to the PCI core code */
  14
  15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  19{ return; }
  20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  21{ return; }
  22#else
  23void pci_create_firmware_label_files(struct pci_dev *pdev);
  24void pci_remove_firmware_label_files(struct pci_dev *pdev);
  25#endif
  26void pci_cleanup_rom(struct pci_dev *dev);
  27
  28enum pci_mmap_api {
  29        PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  30        PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  31};
  32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  33                  enum pci_mmap_api mmap_api);
  34
  35int pci_probe_reset_function(struct pci_dev *dev);
  36
  37/**
  38 * struct pci_platform_pm_ops - Firmware PM callbacks
  39 *
  40 * @is_manageable: returns 'true' if given device is power manageable by the
  41 *                 platform firmware
  42 *
  43 * @set_state: invokes the platform firmware to set the device's power state
  44 *
  45 * @get_state: queries the platform firmware for a device's current power state
  46 *
  47 * @choose_state: returns PCI power state of given device preferred by the
  48 *                platform; to be used during system-wide transitions from a
  49 *                sleeping state to the working state and vice versa
  50 *
  51 * @set_wakeup: enables/disables wakeup capability for the device
  52 *
  53 * @need_resume: returns 'true' if the given device (which is currently
  54 *               suspended) needs to be resumed to be configured for system
  55 *               wakeup.
  56 *
  57 * If given platform is generally capable of power managing PCI devices, all of
  58 * these callbacks are mandatory.
  59 */
  60struct pci_platform_pm_ops {
  61        bool (*is_manageable)(struct pci_dev *dev);
  62        int (*set_state)(struct pci_dev *dev, pci_power_t state);
  63        pci_power_t (*get_state)(struct pci_dev *dev);
  64        pci_power_t (*choose_state)(struct pci_dev *dev);
  65        int (*set_wakeup)(struct pci_dev *dev, bool enable);
  66        bool (*need_resume)(struct pci_dev *dev);
  67};
  68
  69int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  70void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  71void pci_power_up(struct pci_dev *dev);
  72void pci_disable_enabled_device(struct pci_dev *dev);
  73int pci_finish_runtime_suspend(struct pci_dev *dev);
  74void pcie_clear_root_pme_status(struct pci_dev *dev);
  75int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  76void pci_pme_restore(struct pci_dev *dev);
  77bool pci_dev_keep_suspended(struct pci_dev *dev);
  78void pci_dev_complete_resume(struct pci_dev *pci_dev);
  79void pci_config_pm_runtime_get(struct pci_dev *dev);
  80void pci_config_pm_runtime_put(struct pci_dev *dev);
  81void pci_pm_init(struct pci_dev *dev);
  82void pci_ea_init(struct pci_dev *dev);
  83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  84void pci_free_cap_save_buffers(struct pci_dev *dev);
  85bool pci_bridge_d3_possible(struct pci_dev *dev);
  86void pci_bridge_d3_update(struct pci_dev *dev);
  87
  88static inline void pci_wakeup_event(struct pci_dev *dev)
  89{
  90        /* Wait 100 ms before the system can be put into a sleep state. */
  91        pm_wakeup_event(&dev->dev, 100);
  92}
  93
  94static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
  95{
  96        return !!(pci_dev->subordinate);
  97}
  98
  99static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 100{
 101        /*
 102         * Currently we allow normal PCI devices and PCI bridges transition
 103         * into D3 if their bridge_d3 is set.
 104         */
 105        return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 106}
 107
 108int pci_vpd_init(struct pci_dev *dev);
 109void pci_vpd_release(struct pci_dev *dev);
 110void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 111void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 112
 113/* PCI /proc functions */
 114#ifdef CONFIG_PROC_FS
 115int pci_proc_attach_device(struct pci_dev *dev);
 116int pci_proc_detach_device(struct pci_dev *dev);
 117int pci_proc_detach_bus(struct pci_bus *bus);
 118#else
 119static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 120static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 121static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 122#endif
 123
 124/* Functions for PCI Hotplug drivers to use */
 125int pci_hp_add_bridge(struct pci_dev *dev);
 126
 127#ifdef HAVE_PCI_LEGACY
 128void pci_create_legacy_files(struct pci_bus *bus);
 129void pci_remove_legacy_files(struct pci_bus *bus);
 130#else
 131static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 132static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 133#endif
 134
 135/* Lock for read/write access to pci device and bus lists */
 136extern struct rw_semaphore pci_bus_sem;
 137
 138extern raw_spinlock_t pci_lock;
 139
 140extern unsigned int pci_pm_d3_delay;
 141
 142#ifdef CONFIG_PCI_MSI
 143void pci_no_msi(void);
 144#else
 145static inline void pci_no_msi(void) { }
 146#endif
 147
 148static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
 149{
 150        u16 control;
 151
 152        pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 153        control &= ~PCI_MSI_FLAGS_ENABLE;
 154        if (enable)
 155                control |= PCI_MSI_FLAGS_ENABLE;
 156        pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 157}
 158
 159static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 160{
 161        u16 ctrl;
 162
 163        pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 164        ctrl &= ~clear;
 165        ctrl |= set;
 166        pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 167}
 168
 169void pci_realloc_get_opt(char *);
 170
 171static inline int pci_no_d1d2(struct pci_dev *dev)
 172{
 173        unsigned int parent_dstates = 0;
 174
 175        if (dev->bus->self)
 176                parent_dstates = dev->bus->self->no_d1d2;
 177        return (dev->no_d1d2 || parent_dstates);
 178
 179}
 180extern const struct attribute_group *pci_dev_groups[];
 181extern const struct attribute_group *pcibus_groups[];
 182extern const struct device_type pci_dev_type;
 183extern const struct attribute_group *pci_bus_groups[];
 184
 185
 186/**
 187 * pci_match_one_device - Tell if a PCI device structure has a matching
 188 *                        PCI device id structure
 189 * @id: single PCI device id structure to match
 190 * @dev: the PCI device structure to match against
 191 *
 192 * Returns the matching pci_device_id structure or %NULL if there is no match.
 193 */
 194static inline const struct pci_device_id *
 195pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 196{
 197        if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 198            (id->device == PCI_ANY_ID || id->device == dev->device) &&
 199            (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 200            (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 201            !((id->class ^ dev->class) & id->class_mask))
 202                return id;
 203        return NULL;
 204}
 205
 206/* PCI slot sysfs helper code */
 207#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 208
 209extern struct kset *pci_slots_kset;
 210
 211struct pci_slot_attribute {
 212        struct attribute attr;
 213        ssize_t (*show)(struct pci_slot *, char *);
 214        ssize_t (*store)(struct pci_slot *, const char *, size_t);
 215};
 216#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 217
 218enum pci_bar_type {
 219        pci_bar_unknown,        /* Standard PCI BAR probe */
 220        pci_bar_io,             /* An I/O port BAR */
 221        pci_bar_mem32,          /* A 32-bit memory BAR */
 222        pci_bar_mem64,          /* A 64-bit memory BAR */
 223};
 224
 225int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 226bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 227                                int crs_timeout);
 228int pci_setup_device(struct pci_dev *dev);
 229int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 230                    struct resource *res, unsigned int reg);
 231void pci_configure_ari(struct pci_dev *dev);
 232void __pci_bus_size_bridges(struct pci_bus *bus,
 233                        struct list_head *realloc_head);
 234void __pci_bus_assign_resources(const struct pci_bus *bus,
 235                                struct list_head *realloc_head,
 236                                struct list_head *fail_head);
 237bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 238
 239void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 240void pci_disable_bridge_window(struct pci_dev *dev);
 241
 242/* PCIe link information */
 243#define PCIE_SPEED2STR(speed) \
 244        ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
 245         (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
 246         (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
 247         (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
 248         "Unknown speed")
 249
 250/* PCIe speed to Mb/s reduced by encoding overhead */
 251#define PCIE_SPEED2MBS_ENC(speed) \
 252        ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 253         (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 254         (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 255         (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 256         0)
 257
 258enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 259enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 260u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 261                           enum pcie_link_width *width);
 262
 263/* Single Root I/O Virtualization */
 264struct pci_sriov {
 265        int             pos;            /* Capability position */
 266        int             nres;           /* Number of resources */
 267        u32             cap;            /* SR-IOV Capabilities */
 268        u16             ctrl;           /* SR-IOV Control */
 269        u16             total_VFs;      /* Total VFs associated with the PF */
 270        u16             initial_VFs;    /* Initial VFs associated with the PF */
 271        u16             num_VFs;        /* Number of VFs available */
 272        u16             offset;         /* First VF Routing ID offset */
 273        u16             stride;         /* Following VF stride */
 274        u16             vf_device;      /* VF device ID */
 275        u32             pgsz;           /* Page size for BAR alignment */
 276        u8              link;           /* Function Dependency Link */
 277        u8              max_VF_buses;   /* Max buses consumed by VFs */
 278        u16             driver_max_VFs; /* Max num VFs driver supports */
 279        struct pci_dev  *dev;           /* Lowest numbered PF */
 280        struct pci_dev  *self;          /* This PF */
 281        u32             class;          /* VF device */
 282        u8              hdr_type;       /* VF header type */
 283        u16             subsystem_vendor; /* VF subsystem vendor */
 284        u16             subsystem_device; /* VF subsystem device */
 285        resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 286        bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 287};
 288
 289/* pci_dev priv_flags */
 290#define PCI_DEV_DISCONNECTED 0
 291#define PCI_DEV_ADDED 1
 292
 293static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 294{
 295        set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
 296        return 0;
 297}
 298
 299static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 300{
 301        return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
 302}
 303
 304static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 305{
 306        assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 307}
 308
 309static inline bool pci_dev_is_added(const struct pci_dev *dev)
 310{
 311        return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 312}
 313
 314#ifdef CONFIG_PCI_ATS
 315void pci_restore_ats_state(struct pci_dev *dev);
 316#else
 317static inline void pci_restore_ats_state(struct pci_dev *dev)
 318{
 319}
 320#endif /* CONFIG_PCI_ATS */
 321
 322#ifdef CONFIG_PCI_IOV
 323int pci_iov_init(struct pci_dev *dev);
 324void pci_iov_release(struct pci_dev *dev);
 325void pci_iov_remove(struct pci_dev *dev);
 326void pci_iov_update_resource(struct pci_dev *dev, int resno);
 327resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 328void pci_restore_iov_state(struct pci_dev *dev);
 329int pci_iov_bus_range(struct pci_bus *bus);
 330
 331#else
 332static inline int pci_iov_init(struct pci_dev *dev)
 333{
 334        return -ENODEV;
 335}
 336static inline void pci_iov_release(struct pci_dev *dev)
 337
 338{
 339}
 340static inline void pci_iov_remove(struct pci_dev *dev)
 341{
 342}
 343static inline void pci_restore_iov_state(struct pci_dev *dev)
 344{
 345}
 346static inline int pci_iov_bus_range(struct pci_bus *bus)
 347{
 348        return 0;
 349}
 350
 351#endif /* CONFIG_PCI_IOV */
 352
 353unsigned long pci_cardbus_resource_alignment(struct resource *);
 354
 355static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 356                                                     struct resource *res)
 357{
 358#ifdef CONFIG_PCI_IOV
 359        int resno = res - dev->resource;
 360
 361        if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 362                return pci_sriov_resource_alignment(dev, resno);
 363#endif
 364        if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 365                return pci_cardbus_resource_alignment(res);
 366        return resource_alignment(res);
 367}
 368
 369void pci_enable_acs(struct pci_dev *dev);
 370
 371/* PCI error reporting and recovery */
 372void pcie_do_fatal_recovery(struct pci_dev *dev, u32 service);
 373void pcie_do_nonfatal_recovery(struct pci_dev *dev);
 374
 375bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 376#ifdef CONFIG_PCIEASPM
 377void pcie_aspm_init_link_state(struct pci_dev *pdev);
 378void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 379void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 380void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 381#else
 382static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 383static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 384static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 385static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 386#endif
 387
 388#ifdef CONFIG_PCIEASPM_DEBUG
 389void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
 390void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
 391#else
 392static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
 393static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
 394#endif
 395
 396#ifdef CONFIG_PCIE_PTM
 397void pci_ptm_init(struct pci_dev *dev);
 398#else
 399static inline void pci_ptm_init(struct pci_dev *dev) { }
 400#endif
 401
 402struct pci_dev_reset_methods {
 403        u16 vendor;
 404        u16 device;
 405        int (*reset)(struct pci_dev *dev, int probe);
 406};
 407
 408#ifdef CONFIG_PCI_QUIRKS
 409int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 410#else
 411static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 412{
 413        return -ENOTTY;
 414}
 415#endif
 416
 417#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 418int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 419                          struct resource *res);
 420#endif
 421
 422u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
 423int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 424int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 425static inline u64 pci_rebar_size_to_bytes(int size)
 426{
 427        return 1ULL << (size + 20);
 428}
 429
 430struct device_node;
 431
 432#ifdef CONFIG_OF
 433int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 434int of_get_pci_domain_nr(struct device_node *node);
 435int of_pci_get_max_link_speed(struct device_node *node);
 436
 437#else
 438static inline int
 439of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 440{
 441        return -EINVAL;
 442}
 443
 444static inline int
 445of_get_pci_domain_nr(struct device_node *node)
 446{
 447        return -1;
 448}
 449
 450static inline int
 451of_pci_get_max_link_speed(struct device_node *node)
 452{
 453        return -EINVAL;
 454}
 455#endif /* CONFIG_OF */
 456
 457#if defined(CONFIG_OF_ADDRESS)
 458int devm_of_pci_get_host_bridge_resources(struct device *dev,
 459                        unsigned char busno, unsigned char bus_max,
 460                        struct list_head *resources, resource_size_t *io_base);
 461#else
 462static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
 463                        unsigned char busno, unsigned char bus_max,
 464                        struct list_head *resources, resource_size_t *io_base)
 465{
 466        return -EINVAL;
 467}
 468#endif
 469
 470#endif /* DRIVERS_PCI_H */
 471