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15#include <linux/kernel.h>
16
17#include "core.h"
18#include "sh_pfc.h"
19
20#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
21 SH_PFC_PIN_CFG_PULL_UP | \
22 SH_PFC_PIN_CFG_PULL_DOWN)
23
24#define CPU_ALL_PORT(fn, sfx) \
25 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
34 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
37
38
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40
41
42
43#define GPSR0_15 F_(D15, IP7_11_8)
44#define GPSR0_14 F_(D14, IP7_7_4)
45#define GPSR0_13 F_(D13, IP7_3_0)
46#define GPSR0_12 F_(D12, IP6_31_28)
47#define GPSR0_11 F_(D11, IP6_27_24)
48#define GPSR0_10 F_(D10, IP6_23_20)
49#define GPSR0_9 F_(D9, IP6_19_16)
50#define GPSR0_8 F_(D8, IP6_15_12)
51#define GPSR0_7 F_(D7, IP6_11_8)
52#define GPSR0_6 F_(D6, IP6_7_4)
53#define GPSR0_5 F_(D5, IP6_3_0)
54#define GPSR0_4 F_(D4, IP5_31_28)
55#define GPSR0_3 F_(D3, IP5_27_24)
56#define GPSR0_2 F_(D2, IP5_23_20)
57#define GPSR0_1 F_(D1, IP5_19_16)
58#define GPSR0_0 F_(D0, IP5_15_12)
59
60
61#define GPSR1_28 FM(CLKOUT)
62#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
63#define GPSR1_26 F_(WE1_N, IP5_7_4)
64#define GPSR1_25 F_(WE0_N, IP5_3_0)
65#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
66#define GPSR1_23 F_(RD_N, IP4_27_24)
67#define GPSR1_22 F_(BS_N, IP4_23_20)
68#define GPSR1_21 F_(CS1_N, IP4_19_16)
69#define GPSR1_20 F_(CS0_N, IP4_15_12)
70#define GPSR1_19 F_(A19, IP4_11_8)
71#define GPSR1_18 F_(A18, IP4_7_4)
72#define GPSR1_17 F_(A17, IP4_3_0)
73#define GPSR1_16 F_(A16, IP3_31_28)
74#define GPSR1_15 F_(A15, IP3_27_24)
75#define GPSR1_14 F_(A14, IP3_23_20)
76#define GPSR1_13 F_(A13, IP3_19_16)
77#define GPSR1_12 F_(A12, IP3_15_12)
78#define GPSR1_11 F_(A11, IP3_11_8)
79#define GPSR1_10 F_(A10, IP3_7_4)
80#define GPSR1_9 F_(A9, IP3_3_0)
81#define GPSR1_8 F_(A8, IP2_31_28)
82#define GPSR1_7 F_(A7, IP2_27_24)
83#define GPSR1_6 F_(A6, IP2_23_20)
84#define GPSR1_5 F_(A5, IP2_19_16)
85#define GPSR1_4 F_(A4, IP2_15_12)
86#define GPSR1_3 F_(A3, IP2_11_8)
87#define GPSR1_2 F_(A2, IP2_7_4)
88#define GPSR1_1 F_(A1, IP2_3_0)
89#define GPSR1_0 F_(A0, IP1_31_28)
90
91
92#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
93#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
94#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
95#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
96#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
97#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
98#define GPSR2_8 F_(PWM2_A, IP1_27_24)
99#define GPSR2_7 F_(PWM1_A, IP1_23_20)
100#define GPSR2_6 F_(PWM0, IP1_19_16)
101#define GPSR2_5 F_(IRQ5, IP1_15_12)
102#define GPSR2_4 F_(IRQ4, IP1_11_8)
103#define GPSR2_3 F_(IRQ3, IP1_7_4)
104#define GPSR2_2 F_(IRQ2, IP1_3_0)
105#define GPSR2_1 F_(IRQ1, IP0_31_28)
106#define GPSR2_0 F_(IRQ0, IP0_27_24)
107
108
109#define GPSR3_15 F_(SD1_WP, IP11_23_20)
110#define GPSR3_14 F_(SD1_CD, IP11_19_16)
111#define GPSR3_13 F_(SD0_WP, IP11_15_12)
112#define GPSR3_12 F_(SD0_CD, IP11_11_8)
113#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
114#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
115#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
116#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
117#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
118#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
119#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
120#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
121#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
122#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
123#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
124#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
125
126
127#define GPSR4_17 F_(SD3_DS, IP11_7_4)
128#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
129#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
130#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
131#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
132#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
133#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
134#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
135#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
136#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
137#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
138#define GPSR4_6 F_(SD2_DS, IP9_27_24)
139#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
140#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
141#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
142#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
143#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
144#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
145
146
147#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
148#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
149#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
150#define GPSR5_22 FM(MSIOF0_RXD)
151#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
152#define GPSR5_20 FM(MSIOF0_TXD)
153#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
154#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
155#define GPSR5_17 FM(MSIOF0_SCK)
156#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
157#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
158#define GPSR5_14 F_(HTX0, IP13_19_16)
159#define GPSR5_13 F_(HRX0, IP13_15_12)
160#define GPSR5_12 F_(HSCK0, IP13_11_8)
161#define GPSR5_11 F_(RX2_A, IP13_7_4)
162#define GPSR5_10 F_(TX2_A, IP13_3_0)
163#define GPSR5_9 F_(SCK2, IP12_31_28)
164#define GPSR5_8 F_(RTS1_N, IP12_27_24)
165#define GPSR5_7 F_(CTS1_N, IP12_23_20)
166#define GPSR5_6 F_(TX1_A, IP12_19_16)
167#define GPSR5_5 F_(RX1_A, IP12_15_12)
168#define GPSR5_4 F_(RTS0_N, IP12_11_8)
169#define GPSR5_3 F_(CTS0_N, IP12_7_4)
170#define GPSR5_2 F_(TX0, IP12_3_0)
171#define GPSR5_1 F_(RX0, IP11_31_28)
172#define GPSR5_0 F_(SCK0, IP11_27_24)
173
174
175#define GPSR6_31 F_(GP6_31, IP18_7_4)
176#define GPSR6_30 F_(GP6_30, IP18_3_0)
177#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
178#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
179#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
180#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
181#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
182#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
183#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
184#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
185#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
186#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
187#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
188#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
189#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
190#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
191#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
192#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
193#define GPSR6_13 FM(SSI_SDATA5)
194#define GPSR6_12 FM(SSI_WS5)
195#define GPSR6_11 FM(SSI_SCK5)
196#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
197#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
198#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
199#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
200#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
201#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
202#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
203#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
204#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
205#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
206#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
207
208
209#define GPSR7_3 FM(GP7_03)
210#define GPSR7_2 FM(HDMI0_CEC)
211#define GPSR7_1 FM(AVS2)
212#define GPSR7_0 FM(AVS1)
213
214
215
216#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243
244
245#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275
276#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311
312#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
333#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340
341
342#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
362#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
363#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
364#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
365#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
366#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
367#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
368#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
369
370#define PINMUX_GPSR \
371\
372 GPSR6_31 \
373 GPSR6_30 \
374 GPSR6_29 \
375 GPSR1_28 GPSR6_28 \
376 GPSR1_27 GPSR6_27 \
377 GPSR1_26 GPSR6_26 \
378 GPSR1_25 GPSR5_25 GPSR6_25 \
379 GPSR1_24 GPSR5_24 GPSR6_24 \
380 GPSR1_23 GPSR5_23 GPSR6_23 \
381 GPSR1_22 GPSR5_22 GPSR6_22 \
382 GPSR1_21 GPSR5_21 GPSR6_21 \
383 GPSR1_20 GPSR5_20 GPSR6_20 \
384 GPSR1_19 GPSR5_19 GPSR6_19 \
385 GPSR1_18 GPSR5_18 GPSR6_18 \
386 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
387 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
388GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
389GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
390GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
391GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
392GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
393GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
394GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
395GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
396GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
397GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
398GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
399GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
400GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
401GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
402GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
403GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
404
405#define PINMUX_IPSR \
406\
407FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
408FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
409FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
410FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
411FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
412FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
413FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
414FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
415\
416FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
417FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
418FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
419FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
420FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
421FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
422FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
423FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
424\
425FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
426FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
427FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
428FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
429FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
430FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
431FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
432FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
433\
434FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
435FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
436FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
437FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
438FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
439FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
440FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
441FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
442\
443FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
444FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
445FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
446FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
447FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
448FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
449FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
450FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
451
452
453#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
454#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
455#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
456#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
457#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
458#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
459#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
460#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
461#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
462#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
463#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
464#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
465#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
466#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
467#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
468#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
469#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
470#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
471
472
473#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
474#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
476#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
477#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
478#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
479#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
480#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
481#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
482#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
483#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
484#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
485#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
486#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
487#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
488#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
489#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
490#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
491#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
492#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
493#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
494#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
495
496
497#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
498#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
499#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
500#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
501#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
502#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
503#define MOD_SEL2_22 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
504#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
505#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
506#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
507#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
508#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
509#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
510
511#define PINMUX_MOD_SELS \
512\
513MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
514 MOD_SEL2_30 \
515 MOD_SEL1_29_28_27 MOD_SEL2_29 \
516MOD_SEL0_28_27 MOD_SEL2_28_27 \
517MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
518 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
519MOD_SEL0_23 MOD_SEL1_23_22_21 \
520MOD_SEL0_22 MOD_SEL2_22 \
521MOD_SEL0_21 MOD_SEL2_21 \
522MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
523MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
524MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
525 MOD_SEL2_17 \
526MOD_SEL0_16 MOD_SEL1_16 \
527 MOD_SEL1_15_14 \
528MOD_SEL0_14_13 \
529 MOD_SEL1_13 \
530MOD_SEL0_12 MOD_SEL1_12 \
531MOD_SEL0_11 MOD_SEL1_11 \
532MOD_SEL0_10 MOD_SEL1_10 \
533MOD_SEL0_9_8 MOD_SEL1_9 \
534MOD_SEL0_7_6 \
535 MOD_SEL1_6 \
536MOD_SEL0_5 MOD_SEL1_5 \
537MOD_SEL0_4_3 MOD_SEL1_4 \
538 MOD_SEL1_3 \
539 MOD_SEL1_2 \
540 MOD_SEL1_1 \
541 MOD_SEL1_0 MOD_SEL2_0
542
543
544
545
546
547#define PINMUX_STATIC \
548 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
549 FM(QSPI0_IO2) FM(QSPI0_IO3) \
550 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
551 FM(QSPI1_IO2) FM(QSPI1_IO3) \
552 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
553 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
554 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
555 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
556 FM(PRESETOUT) \
557 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
558 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
559
560enum {
561 PINMUX_RESERVED = 0,
562
563 PINMUX_DATA_BEGIN,
564 GP_ALL(DATA),
565 PINMUX_DATA_END,
566
567#define F_(x, y)
568#define FM(x) FN_##x,
569 PINMUX_FUNCTION_BEGIN,
570 GP_ALL(FN),
571 PINMUX_GPSR
572 PINMUX_IPSR
573 PINMUX_MOD_SELS
574 PINMUX_FUNCTION_END,
575#undef F_
576#undef FM
577
578#define F_(x, y)
579#define FM(x) x##_MARK,
580 PINMUX_MARK_BEGIN,
581 PINMUX_GPSR
582 PINMUX_IPSR
583 PINMUX_MOD_SELS
584 PINMUX_STATIC
585 PINMUX_MARK_END,
586#undef F_
587#undef FM
588};
589
590static const u16 pinmux_data[] = {
591 PINMUX_DATA_GP_ALL(),
592
593 PINMUX_SINGLE(AVS1),
594 PINMUX_SINGLE(AVS2),
595 PINMUX_SINGLE(CLKOUT),
596 PINMUX_SINGLE(GP7_03),
597 PINMUX_SINGLE(HDMI0_CEC),
598 PINMUX_SINGLE(MSIOF0_RXD),
599 PINMUX_SINGLE(MSIOF0_SCK),
600 PINMUX_SINGLE(MSIOF0_TXD),
601 PINMUX_SINGLE(SSI_SCK5),
602 PINMUX_SINGLE(SSI_SDATA5),
603 PINMUX_SINGLE(SSI_WS5),
604
605
606 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
607 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
608
609 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
610 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
611 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
612
613 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
614 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
615 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
616
617 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
618 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
619 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
620 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
621
622 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
623 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
625
626 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
629
630 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
631 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
632 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
633 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
635 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
636 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
637
638 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
639 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
640 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
641 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
643 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
644 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
645
646
647 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
648 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
649 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
650 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
651 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
652 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
653
654 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
655 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
660
661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
664 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
665 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
667
668 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
669 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
675
676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
680
681 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
682 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
683 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
684 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
685
686 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
687 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
688 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_GPSR(IP1_31_28, A0),
691 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
692 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
694 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
695 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
696
697
698 PINMUX_IPSR_GPSR(IP2_3_0, A1),
699 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
700 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
701 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
702 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
703 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
704
705 PINMUX_IPSR_GPSR(IP2_7_4, A2),
706 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
707 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
708 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
709 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
710 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
711
712 PINMUX_IPSR_GPSR(IP2_11_8, A3),
713 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
714 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
715 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
716 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
717 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
718
719 PINMUX_IPSR_GPSR(IP2_15_12, A4),
720 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
721 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
722 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
723 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
725
726 PINMUX_IPSR_GPSR(IP2_19_16, A5),
727 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
728 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
729 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
731 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
733
734 PINMUX_IPSR_GPSR(IP2_23_20, A6),
735 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
736 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
737 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
738 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
739 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
741
742 PINMUX_IPSR_GPSR(IP2_27_24, A7),
743 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
744 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
745 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
746 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
747 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
749
750 PINMUX_IPSR_GPSR(IP2_31_28, A8),
751 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
755 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
756 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
757
758
759 PINMUX_IPSR_GPSR(IP3_3_0, A9),
760 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
761 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
762 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
763
764 PINMUX_IPSR_GPSR(IP3_7_4, A10),
765 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
767 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
768
769 PINMUX_IPSR_GPSR(IP3_11_8, A11),
770 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
771 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
772 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
773 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
774 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
775 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
776 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
777 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
778
779 PINMUX_IPSR_GPSR(IP3_15_12, A12),
780 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
781 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
782 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
783 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
784 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
785
786 PINMUX_IPSR_GPSR(IP3_19_16, A13),
787 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
788 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
789 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
790 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
791 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
792
793 PINMUX_IPSR_GPSR(IP3_23_20, A14),
794 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
795 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
796 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
797 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
798 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
799
800 PINMUX_IPSR_GPSR(IP3_27_24, A15),
801 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
802 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
803 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
804 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
805 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
806
807 PINMUX_IPSR_GPSR(IP3_31_28, A16),
808 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
809 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
810 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
811
812
813 PINMUX_IPSR_GPSR(IP4_3_0, A17),
814 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
815 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
816 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
817
818 PINMUX_IPSR_GPSR(IP4_7_4, A18),
819 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
820 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
822
823 PINMUX_IPSR_GPSR(IP4_11_8, A19),
824 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
825 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
826 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
827
828 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
829 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
830
831 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
832 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
833 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
834
835 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
836 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
837 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
838 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
839 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
841 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
842 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
843
844 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
845 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
846 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
850
851 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
852 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
853 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
857
858
859 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
860 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
861 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
862 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
863 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
864 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
865 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
866
867 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
868 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
869 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
870 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
871 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
872 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
873 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
874 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
877 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
878 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
880
881 PINMUX_IPSR_GPSR(IP5_15_12, D0),
882 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
884 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
885 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
886
887 PINMUX_IPSR_GPSR(IP5_19_16, D1),
888 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
890 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
891 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
892
893 PINMUX_IPSR_GPSR(IP5_23_20, D2),
894 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
895 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
896 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
897
898 PINMUX_IPSR_GPSR(IP5_27_24, D3),
899 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
900 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
901 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
902
903 PINMUX_IPSR_GPSR(IP5_31_28, D4),
904 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
905 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
906 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
907
908
909 PINMUX_IPSR_GPSR(IP6_3_0, D5),
910 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
911 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
912 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
913
914 PINMUX_IPSR_GPSR(IP6_7_4, D6),
915 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
916 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
918
919 PINMUX_IPSR_GPSR(IP6_11_8, D7),
920 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
923
924 PINMUX_IPSR_GPSR(IP6_15_12, D8),
925 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
926 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
930
931 PINMUX_IPSR_GPSR(IP6_19_16, D9),
932 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
933 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
935 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
936
937 PINMUX_IPSR_GPSR(IP6_23_20, D10),
938 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
939 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
940 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
941 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
942 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
943 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
944
945 PINMUX_IPSR_GPSR(IP6_27_24, D11),
946 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
947 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
948 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
949 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
950 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
951 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
952
953 PINMUX_IPSR_GPSR(IP6_31_28, D12),
954 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
955 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
956 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
957 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
958 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
959
960
961 PINMUX_IPSR_GPSR(IP7_3_0, D13),
962 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
963 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
964 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
965 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
966 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
967
968 PINMUX_IPSR_GPSR(IP7_7_4, D14),
969 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
970 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
971 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
972 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
973 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
974 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
975
976 PINMUX_IPSR_GPSR(IP7_11_8, D15),
977 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
978 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
979 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
980 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
981 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
982 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
983
984 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
985 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
986 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
987
988 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
989 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
990 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
991
992 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
993 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
994 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
995 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
996
997 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
998 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
999 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1000 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1001
1002
1003 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1004 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1009 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1012
1013 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1014 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1016
1017 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1018 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1019 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDFC_1),
1020 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1021 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1022
1023 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1024 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1025 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDFC_1),
1027 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1028 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1029
1030 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1031 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1032 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
1034 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1036
1037 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1038 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1039 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
1041 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1043
1044 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1045 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1046 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDFC_1),
1048 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1050
1051
1052 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1053 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1054
1055 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1056 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1057
1058 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1059 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1060
1061 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1062 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1063
1064 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1065 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1066
1067 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1068 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1069
1070 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1071 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1072 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1073
1074 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1075 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1076
1077
1078 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1079 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1080
1081 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1082 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1083
1084 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1085 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1086
1087 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1088 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1089
1090 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1091 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1092
1093 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1094 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1095 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1096
1097 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1098 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1099 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1100
1101 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1102 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1103 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1104
1105
1106 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1107 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1108 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1109
1110 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1111 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1112
1113 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1114 PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A, SEL_NDFC_0),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, NFDATA15_A, SEL_NDFC_0),
1120 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1121
1122 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1123 PINMUX_IPSR_MSEL(IP11_19_16, NFRB_N_A, SEL_NDFC_0),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, NFCE_N_A, SEL_NDFC_0),
1128 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1131 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1135 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1137 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1138 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1139 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1140
1141 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1142 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1143 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1145 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1146
1147
1148 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1149 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1152 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1153
1154 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1155 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1157 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1159 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1160 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1161 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1162
1163 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1164 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1167 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1168 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1169 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1170 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1171
1172 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1182 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1183
1184 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1185 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1187 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1189 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1190 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1191
1192 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
1193 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1194 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1195 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1197 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1198 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1199
1200 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1201 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1203 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1205 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1206 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1207
1208
1209 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1211 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1214 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1215
1216 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1222
1223 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1224 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1225 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1226 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
1227 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1230 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1231
1232 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1233 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1234 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
1235 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1238
1239 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1240 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
1242 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1247 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1248 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1249 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
1250 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1253 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1254
1255 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1256 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1257 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1258 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
1259 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1260 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1261 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1262
1263 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1264 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1265 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1266 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1267
1268
1269 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1270 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1271 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDFC_0),
1272 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1273 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1275 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1276 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1277
1278 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1279 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1280 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1281 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1284 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1286
1287 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1288 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1289 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1290
1291 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1292 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1293 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1294 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1295
1296 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1297 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1298 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1301 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1304 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1307 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1308
1309
1310 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
1311
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1313 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
1314
1315 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1316 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1317 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1318
1319 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1320 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1322 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1323
1324 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1325 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1331
1332 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1333 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1339
1340 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1341 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1347
1348 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1349 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1355
1356
1357 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1362
1363 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1364 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1365 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1366
1367 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1368 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1369 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1370 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1371 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1374
1375 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1376 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1377 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1378 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1382
1383 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1384 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1385 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1391
1392 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1393 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1394 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1395 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1396 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1399
1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
1401 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1403 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
1405 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1406 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1408
1409
1410 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1411 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1412
1413 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1414 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1415 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1416 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1417 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1418
1419 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1420 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1421 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1422 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1424 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1426
1427 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1428 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1429 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1430 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1432 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1433
1434 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1435 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
1437 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1438 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1440 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1443
1444 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1445 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1446 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
1447 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1448 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1450 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1453
1454 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1455 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1456 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1458 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1460 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1461 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1462 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1463 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1465
1466 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1467 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1468 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
1469 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1470 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1472 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1473 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1474 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1475
1476
1477 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1478 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1479 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
1480 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1481 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1483 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1484 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1486
1487 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1488 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1489 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
1490 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1491 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1493 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1494 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1496
1497
1498 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1499 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1500 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1501
1502
1503
1504
1505
1506
1507
1508
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
1512};
1513
1514
1515
1516
1517
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521#define PIN_NONE U16_MAX
1522
1523static const struct sh_pfc_pin pinmux_pins[] = {
1524 PINMUX_GPIO_GP_ALL(),
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1576};
1577
1578
1579static const unsigned int avb_link_pins[] = {
1580
1581 RCAR_GP_PIN(2, 12),
1582};
1583static const unsigned int avb_link_mux[] = {
1584 AVB_LINK_MARK,
1585};
1586static const unsigned int avb_magic_pins[] = {
1587
1588 RCAR_GP_PIN(2, 10),
1589};
1590static const unsigned int avb_magic_mux[] = {
1591 AVB_MAGIC_MARK,
1592};
1593static const unsigned int avb_phy_int_pins[] = {
1594
1595 RCAR_GP_PIN(2, 11),
1596};
1597static const unsigned int avb_phy_int_mux[] = {
1598 AVB_PHY_INT_MARK,
1599};
1600static const unsigned int avb_mdio_pins[] = {
1601
1602 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1603};
1604static const unsigned int avb_mdio_mux[] = {
1605 AVB_MDC_MARK, AVB_MDIO_MARK,
1606};
1607static const unsigned int avb_mii_pins[] = {
1608
1609
1610
1611
1612
1613
1614
1615 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1616 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1617 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1618 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1619 PIN_NUMBER('A', 12),
1620
1621};
1622static const unsigned int avb_mii_mux[] = {
1623 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1624 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1625 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1626 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1627 AVB_TXCREFCLK_MARK,
1628};
1629static const unsigned int avb_avtp_pps_pins[] = {
1630
1631 RCAR_GP_PIN(2, 6),
1632};
1633static const unsigned int avb_avtp_pps_mux[] = {
1634 AVB_AVTP_PPS_MARK,
1635};
1636static const unsigned int avb_avtp_match_a_pins[] = {
1637
1638 RCAR_GP_PIN(2, 13),
1639};
1640static const unsigned int avb_avtp_match_a_mux[] = {
1641 AVB_AVTP_MATCH_A_MARK,
1642};
1643static const unsigned int avb_avtp_capture_a_pins[] = {
1644
1645 RCAR_GP_PIN(2, 14),
1646};
1647static const unsigned int avb_avtp_capture_a_mux[] = {
1648 AVB_AVTP_CAPTURE_A_MARK,
1649};
1650static const unsigned int avb_avtp_match_b_pins[] = {
1651
1652 RCAR_GP_PIN(1, 8),
1653};
1654static const unsigned int avb_avtp_match_b_mux[] = {
1655 AVB_AVTP_MATCH_B_MARK,
1656};
1657static const unsigned int avb_avtp_capture_b_pins[] = {
1658
1659 RCAR_GP_PIN(1, 11),
1660};
1661static const unsigned int avb_avtp_capture_b_mux[] = {
1662 AVB_AVTP_CAPTURE_B_MARK,
1663};
1664
1665
1666static const unsigned int du_rgb666_pins[] = {
1667
1668 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1669 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1670 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1671 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1672 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1673 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1674};
1675
1676static const unsigned int du_rgb666_mux[] = {
1677 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1678 DU_DR3_MARK, DU_DR2_MARK,
1679 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1680 DU_DG3_MARK, DU_DG2_MARK,
1681 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1682 DU_DB3_MARK, DU_DB2_MARK,
1683};
1684
1685static const unsigned int du_rgb888_pins[] = {
1686
1687 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1688 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1689 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1690 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1691 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1692 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1693 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1694 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1695 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1696};
1697
1698static const unsigned int du_rgb888_mux[] = {
1699 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1700 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1701 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1702 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1703 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1704 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1705};
1706
1707static const unsigned int du_clk_out_0_pins[] = {
1708
1709 RCAR_GP_PIN(1, 27),
1710};
1711
1712static const unsigned int du_clk_out_0_mux[] = {
1713 DU_DOTCLKOUT0_MARK
1714};
1715
1716static const unsigned int du_clk_out_1_pins[] = {
1717
1718 RCAR_GP_PIN(2, 3),
1719};
1720
1721static const unsigned int du_clk_out_1_mux[] = {
1722 DU_DOTCLKOUT1_MARK
1723};
1724
1725static const unsigned int du_sync_pins[] = {
1726
1727 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1728};
1729
1730static const unsigned int du_sync_mux[] = {
1731 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1732};
1733
1734static const unsigned int du_oddf_pins[] = {
1735
1736 RCAR_GP_PIN(2, 2),
1737};
1738
1739static const unsigned int du_oddf_mux[] = {
1740 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1741};
1742
1743static const unsigned int du_cde_pins[] = {
1744
1745 RCAR_GP_PIN(2, 0),
1746};
1747
1748static const unsigned int du_cde_mux[] = {
1749 DU_CDE_MARK,
1750};
1751
1752static const unsigned int du_disp_pins[] = {
1753
1754 RCAR_GP_PIN(2, 1),
1755};
1756
1757static const unsigned int du_disp_mux[] = {
1758 DU_DISP_MARK,
1759};
1760
1761
1762static const unsigned int i2c1_a_pins[] = {
1763
1764 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1765};
1766static const unsigned int i2c1_a_mux[] = {
1767 SDA1_A_MARK, SCL1_A_MARK,
1768};
1769static const unsigned int i2c1_b_pins[] = {
1770
1771 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1772};
1773static const unsigned int i2c1_b_mux[] = {
1774 SDA1_B_MARK, SCL1_B_MARK,
1775};
1776static const unsigned int i2c2_a_pins[] = {
1777
1778 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1779};
1780static const unsigned int i2c2_a_mux[] = {
1781 SDA2_A_MARK, SCL2_A_MARK,
1782};
1783static const unsigned int i2c2_b_pins[] = {
1784
1785 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1786};
1787static const unsigned int i2c2_b_mux[] = {
1788 SDA2_B_MARK, SCL2_B_MARK,
1789};
1790static const unsigned int i2c6_a_pins[] = {
1791
1792 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1793};
1794static const unsigned int i2c6_a_mux[] = {
1795 SDA6_A_MARK, SCL6_A_MARK,
1796};
1797static const unsigned int i2c6_b_pins[] = {
1798
1799 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1800};
1801static const unsigned int i2c6_b_mux[] = {
1802 SDA6_B_MARK, SCL6_B_MARK,
1803};
1804static const unsigned int i2c6_c_pins[] = {
1805
1806 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1807};
1808static const unsigned int i2c6_c_mux[] = {
1809 SDA6_C_MARK, SCL6_C_MARK,
1810};
1811
1812
1813static const unsigned int intc_ex_irq0_pins[] = {
1814
1815 RCAR_GP_PIN(2, 0),
1816};
1817static const unsigned int intc_ex_irq0_mux[] = {
1818 IRQ0_MARK,
1819};
1820static const unsigned int intc_ex_irq1_pins[] = {
1821
1822 RCAR_GP_PIN(2, 1),
1823};
1824static const unsigned int intc_ex_irq1_mux[] = {
1825 IRQ1_MARK,
1826};
1827static const unsigned int intc_ex_irq2_pins[] = {
1828
1829 RCAR_GP_PIN(2, 2),
1830};
1831static const unsigned int intc_ex_irq2_mux[] = {
1832 IRQ2_MARK,
1833};
1834static const unsigned int intc_ex_irq3_pins[] = {
1835
1836 RCAR_GP_PIN(2, 3),
1837};
1838static const unsigned int intc_ex_irq3_mux[] = {
1839 IRQ3_MARK,
1840};
1841static const unsigned int intc_ex_irq4_pins[] = {
1842
1843 RCAR_GP_PIN(2, 4),
1844};
1845static const unsigned int intc_ex_irq4_mux[] = {
1846 IRQ4_MARK,
1847};
1848static const unsigned int intc_ex_irq5_pins[] = {
1849
1850 RCAR_GP_PIN(2, 5),
1851};
1852static const unsigned int intc_ex_irq5_mux[] = {
1853 IRQ5_MARK,
1854};
1855
1856
1857static const unsigned int msiof0_clk_pins[] = {
1858
1859 RCAR_GP_PIN(5, 17),
1860};
1861static const unsigned int msiof0_clk_mux[] = {
1862 MSIOF0_SCK_MARK,
1863};
1864static const unsigned int msiof0_sync_pins[] = {
1865
1866 RCAR_GP_PIN(5, 18),
1867};
1868static const unsigned int msiof0_sync_mux[] = {
1869 MSIOF0_SYNC_MARK,
1870};
1871static const unsigned int msiof0_ss1_pins[] = {
1872
1873 RCAR_GP_PIN(5, 19),
1874};
1875static const unsigned int msiof0_ss1_mux[] = {
1876 MSIOF0_SS1_MARK,
1877};
1878static const unsigned int msiof0_ss2_pins[] = {
1879
1880 RCAR_GP_PIN(5, 21),
1881};
1882static const unsigned int msiof0_ss2_mux[] = {
1883 MSIOF0_SS2_MARK,
1884};
1885static const unsigned int msiof0_txd_pins[] = {
1886
1887 RCAR_GP_PIN(5, 20),
1888};
1889static const unsigned int msiof0_txd_mux[] = {
1890 MSIOF0_TXD_MARK,
1891};
1892static const unsigned int msiof0_rxd_pins[] = {
1893
1894 RCAR_GP_PIN(5, 22),
1895};
1896static const unsigned int msiof0_rxd_mux[] = {
1897 MSIOF0_RXD_MARK,
1898};
1899
1900static const unsigned int msiof1_clk_a_pins[] = {
1901
1902 RCAR_GP_PIN(6, 8),
1903};
1904static const unsigned int msiof1_clk_a_mux[] = {
1905 MSIOF1_SCK_A_MARK,
1906};
1907static const unsigned int msiof1_sync_a_pins[] = {
1908
1909 RCAR_GP_PIN(6, 9),
1910};
1911static const unsigned int msiof1_sync_a_mux[] = {
1912 MSIOF1_SYNC_A_MARK,
1913};
1914static const unsigned int msiof1_ss1_a_pins[] = {
1915
1916 RCAR_GP_PIN(6, 5),
1917};
1918static const unsigned int msiof1_ss1_a_mux[] = {
1919 MSIOF1_SS1_A_MARK,
1920};
1921static const unsigned int msiof1_ss2_a_pins[] = {
1922
1923 RCAR_GP_PIN(6, 6),
1924};
1925static const unsigned int msiof1_ss2_a_mux[] = {
1926 MSIOF1_SS2_A_MARK,
1927};
1928static const unsigned int msiof1_txd_a_pins[] = {
1929
1930 RCAR_GP_PIN(6, 7),
1931};
1932static const unsigned int msiof1_txd_a_mux[] = {
1933 MSIOF1_TXD_A_MARK,
1934};
1935static const unsigned int msiof1_rxd_a_pins[] = {
1936
1937 RCAR_GP_PIN(6, 10),
1938};
1939static const unsigned int msiof1_rxd_a_mux[] = {
1940 MSIOF1_RXD_A_MARK,
1941};
1942static const unsigned int msiof1_clk_b_pins[] = {
1943
1944 RCAR_GP_PIN(5, 9),
1945};
1946static const unsigned int msiof1_clk_b_mux[] = {
1947 MSIOF1_SCK_B_MARK,
1948};
1949static const unsigned int msiof1_sync_b_pins[] = {
1950
1951 RCAR_GP_PIN(5, 3),
1952};
1953static const unsigned int msiof1_sync_b_mux[] = {
1954 MSIOF1_SYNC_B_MARK,
1955};
1956static const unsigned int msiof1_ss1_b_pins[] = {
1957
1958 RCAR_GP_PIN(5, 4),
1959};
1960static const unsigned int msiof1_ss1_b_mux[] = {
1961 MSIOF1_SS1_B_MARK,
1962};
1963static const unsigned int msiof1_ss2_b_pins[] = {
1964
1965 RCAR_GP_PIN(5, 0),
1966};
1967static const unsigned int msiof1_ss2_b_mux[] = {
1968 MSIOF1_SS2_B_MARK,
1969};
1970static const unsigned int msiof1_txd_b_pins[] = {
1971
1972 RCAR_GP_PIN(5, 8),
1973};
1974static const unsigned int msiof1_txd_b_mux[] = {
1975 MSIOF1_TXD_B_MARK,
1976};
1977static const unsigned int msiof1_rxd_b_pins[] = {
1978
1979 RCAR_GP_PIN(5, 7),
1980};
1981static const unsigned int msiof1_rxd_b_mux[] = {
1982 MSIOF1_RXD_B_MARK,
1983};
1984static const unsigned int msiof1_clk_c_pins[] = {
1985
1986 RCAR_GP_PIN(6, 17),
1987};
1988static const unsigned int msiof1_clk_c_mux[] = {
1989 MSIOF1_SCK_C_MARK,
1990};
1991static const unsigned int msiof1_sync_c_pins[] = {
1992
1993 RCAR_GP_PIN(6, 18),
1994};
1995static const unsigned int msiof1_sync_c_mux[] = {
1996 MSIOF1_SYNC_C_MARK,
1997};
1998static const unsigned int msiof1_ss1_c_pins[] = {
1999
2000 RCAR_GP_PIN(6, 21),
2001};
2002static const unsigned int msiof1_ss1_c_mux[] = {
2003 MSIOF1_SS1_C_MARK,
2004};
2005static const unsigned int msiof1_ss2_c_pins[] = {
2006
2007 RCAR_GP_PIN(6, 27),
2008};
2009static const unsigned int msiof1_ss2_c_mux[] = {
2010 MSIOF1_SS2_C_MARK,
2011};
2012static const unsigned int msiof1_txd_c_pins[] = {
2013
2014 RCAR_GP_PIN(6, 20),
2015};
2016static const unsigned int msiof1_txd_c_mux[] = {
2017 MSIOF1_TXD_C_MARK,
2018};
2019static const unsigned int msiof1_rxd_c_pins[] = {
2020
2021 RCAR_GP_PIN(6, 19),
2022};
2023static const unsigned int msiof1_rxd_c_mux[] = {
2024 MSIOF1_RXD_C_MARK,
2025};
2026static const unsigned int msiof1_clk_d_pins[] = {
2027
2028 RCAR_GP_PIN(5, 12),
2029};
2030static const unsigned int msiof1_clk_d_mux[] = {
2031 MSIOF1_SCK_D_MARK,
2032};
2033static const unsigned int msiof1_sync_d_pins[] = {
2034
2035 RCAR_GP_PIN(5, 15),
2036};
2037static const unsigned int msiof1_sync_d_mux[] = {
2038 MSIOF1_SYNC_D_MARK,
2039};
2040static const unsigned int msiof1_ss1_d_pins[] = {
2041
2042 RCAR_GP_PIN(5, 16),
2043};
2044static const unsigned int msiof1_ss1_d_mux[] = {
2045 MSIOF1_SS1_D_MARK,
2046};
2047static const unsigned int msiof1_ss2_d_pins[] = {
2048
2049 RCAR_GP_PIN(5, 21),
2050};
2051static const unsigned int msiof1_ss2_d_mux[] = {
2052 MSIOF1_SS2_D_MARK,
2053};
2054static const unsigned int msiof1_txd_d_pins[] = {
2055
2056 RCAR_GP_PIN(5, 14),
2057};
2058static const unsigned int msiof1_txd_d_mux[] = {
2059 MSIOF1_TXD_D_MARK,
2060};
2061static const unsigned int msiof1_rxd_d_pins[] = {
2062
2063 RCAR_GP_PIN(5, 13),
2064};
2065static const unsigned int msiof1_rxd_d_mux[] = {
2066 MSIOF1_RXD_D_MARK,
2067};
2068static const unsigned int msiof1_clk_e_pins[] = {
2069
2070 RCAR_GP_PIN(3, 0),
2071};
2072static const unsigned int msiof1_clk_e_mux[] = {
2073 MSIOF1_SCK_E_MARK,
2074};
2075static const unsigned int msiof1_sync_e_pins[] = {
2076
2077 RCAR_GP_PIN(3, 1),
2078};
2079static const unsigned int msiof1_sync_e_mux[] = {
2080 MSIOF1_SYNC_E_MARK,
2081};
2082static const unsigned int msiof1_ss1_e_pins[] = {
2083
2084 RCAR_GP_PIN(3, 4),
2085};
2086static const unsigned int msiof1_ss1_e_mux[] = {
2087 MSIOF1_SS1_E_MARK,
2088};
2089static const unsigned int msiof1_ss2_e_pins[] = {
2090
2091 RCAR_GP_PIN(3, 5),
2092};
2093static const unsigned int msiof1_ss2_e_mux[] = {
2094 MSIOF1_SS2_E_MARK,
2095};
2096static const unsigned int msiof1_txd_e_pins[] = {
2097
2098 RCAR_GP_PIN(3, 3),
2099};
2100static const unsigned int msiof1_txd_e_mux[] = {
2101 MSIOF1_TXD_E_MARK,
2102};
2103static const unsigned int msiof1_rxd_e_pins[] = {
2104
2105 RCAR_GP_PIN(3, 2),
2106};
2107static const unsigned int msiof1_rxd_e_mux[] = {
2108 MSIOF1_RXD_E_MARK,
2109};
2110static const unsigned int msiof1_clk_f_pins[] = {
2111
2112 RCAR_GP_PIN(5, 23),
2113};
2114static const unsigned int msiof1_clk_f_mux[] = {
2115 MSIOF1_SCK_F_MARK,
2116};
2117static const unsigned int msiof1_sync_f_pins[] = {
2118
2119 RCAR_GP_PIN(5, 24),
2120};
2121static const unsigned int msiof1_sync_f_mux[] = {
2122 MSIOF1_SYNC_F_MARK,
2123};
2124static const unsigned int msiof1_ss1_f_pins[] = {
2125
2126 RCAR_GP_PIN(6, 1),
2127};
2128static const unsigned int msiof1_ss1_f_mux[] = {
2129 MSIOF1_SS1_F_MARK,
2130};
2131static const unsigned int msiof1_ss2_f_pins[] = {
2132
2133 RCAR_GP_PIN(6, 2),
2134};
2135static const unsigned int msiof1_ss2_f_mux[] = {
2136 MSIOF1_SS2_F_MARK,
2137};
2138static const unsigned int msiof1_txd_f_pins[] = {
2139
2140 RCAR_GP_PIN(6, 0),
2141};
2142static const unsigned int msiof1_txd_f_mux[] = {
2143 MSIOF1_TXD_F_MARK,
2144};
2145static const unsigned int msiof1_rxd_f_pins[] = {
2146
2147 RCAR_GP_PIN(5, 25),
2148};
2149static const unsigned int msiof1_rxd_f_mux[] = {
2150 MSIOF1_RXD_F_MARK,
2151};
2152static const unsigned int msiof1_clk_g_pins[] = {
2153
2154 RCAR_GP_PIN(3, 6),
2155};
2156static const unsigned int msiof1_clk_g_mux[] = {
2157 MSIOF1_SCK_G_MARK,
2158};
2159static const unsigned int msiof1_sync_g_pins[] = {
2160
2161 RCAR_GP_PIN(3, 7),
2162};
2163static const unsigned int msiof1_sync_g_mux[] = {
2164 MSIOF1_SYNC_G_MARK,
2165};
2166static const unsigned int msiof1_ss1_g_pins[] = {
2167
2168 RCAR_GP_PIN(3, 10),
2169};
2170static const unsigned int msiof1_ss1_g_mux[] = {
2171 MSIOF1_SS1_G_MARK,
2172};
2173static const unsigned int msiof1_ss2_g_pins[] = {
2174
2175 RCAR_GP_PIN(3, 11),
2176};
2177static const unsigned int msiof1_ss2_g_mux[] = {
2178 MSIOF1_SS2_G_MARK,
2179};
2180static const unsigned int msiof1_txd_g_pins[] = {
2181
2182 RCAR_GP_PIN(3, 9),
2183};
2184static const unsigned int msiof1_txd_g_mux[] = {
2185 MSIOF1_TXD_G_MARK,
2186};
2187static const unsigned int msiof1_rxd_g_pins[] = {
2188
2189 RCAR_GP_PIN(3, 8),
2190};
2191static const unsigned int msiof1_rxd_g_mux[] = {
2192 MSIOF1_RXD_G_MARK,
2193};
2194
2195static const unsigned int msiof2_clk_a_pins[] = {
2196
2197 RCAR_GP_PIN(1, 9),
2198};
2199static const unsigned int msiof2_clk_a_mux[] = {
2200 MSIOF2_SCK_A_MARK,
2201};
2202static const unsigned int msiof2_sync_a_pins[] = {
2203
2204 RCAR_GP_PIN(1, 8),
2205};
2206static const unsigned int msiof2_sync_a_mux[] = {
2207 MSIOF2_SYNC_A_MARK,
2208};
2209static const unsigned int msiof2_ss1_a_pins[] = {
2210
2211 RCAR_GP_PIN(1, 6),
2212};
2213static const unsigned int msiof2_ss1_a_mux[] = {
2214 MSIOF2_SS1_A_MARK,
2215};
2216static const unsigned int msiof2_ss2_a_pins[] = {
2217
2218 RCAR_GP_PIN(1, 7),
2219};
2220static const unsigned int msiof2_ss2_a_mux[] = {
2221 MSIOF2_SS2_A_MARK,
2222};
2223static const unsigned int msiof2_txd_a_pins[] = {
2224
2225 RCAR_GP_PIN(1, 11),
2226};
2227static const unsigned int msiof2_txd_a_mux[] = {
2228 MSIOF2_TXD_A_MARK,
2229};
2230static const unsigned int msiof2_rxd_a_pins[] = {
2231
2232 RCAR_GP_PIN(1, 10),
2233};
2234static const unsigned int msiof2_rxd_a_mux[] = {
2235 MSIOF2_RXD_A_MARK,
2236};
2237static const unsigned int msiof2_clk_b_pins[] = {
2238
2239 RCAR_GP_PIN(0, 4),
2240};
2241static const unsigned int msiof2_clk_b_mux[] = {
2242 MSIOF2_SCK_B_MARK,
2243};
2244static const unsigned int msiof2_sync_b_pins[] = {
2245
2246 RCAR_GP_PIN(0, 5),
2247};
2248static const unsigned int msiof2_sync_b_mux[] = {
2249 MSIOF2_SYNC_B_MARK,
2250};
2251static const unsigned int msiof2_ss1_b_pins[] = {
2252
2253 RCAR_GP_PIN(0, 0),
2254};
2255static const unsigned int msiof2_ss1_b_mux[] = {
2256 MSIOF2_SS1_B_MARK,
2257};
2258static const unsigned int msiof2_ss2_b_pins[] = {
2259
2260 RCAR_GP_PIN(0, 1),
2261};
2262static const unsigned int msiof2_ss2_b_mux[] = {
2263 MSIOF2_SS2_B_MARK,
2264};
2265static const unsigned int msiof2_txd_b_pins[] = {
2266
2267 RCAR_GP_PIN(0, 7),
2268};
2269static const unsigned int msiof2_txd_b_mux[] = {
2270 MSIOF2_TXD_B_MARK,
2271};
2272static const unsigned int msiof2_rxd_b_pins[] = {
2273
2274 RCAR_GP_PIN(0, 6),
2275};
2276static const unsigned int msiof2_rxd_b_mux[] = {
2277 MSIOF2_RXD_B_MARK,
2278};
2279static const unsigned int msiof2_clk_c_pins[] = {
2280
2281 RCAR_GP_PIN(2, 12),
2282};
2283static const unsigned int msiof2_clk_c_mux[] = {
2284 MSIOF2_SCK_C_MARK,
2285};
2286static const unsigned int msiof2_sync_c_pins[] = {
2287
2288 RCAR_GP_PIN(2, 11),
2289};
2290static const unsigned int msiof2_sync_c_mux[] = {
2291 MSIOF2_SYNC_C_MARK,
2292};
2293static const unsigned int msiof2_ss1_c_pins[] = {
2294
2295 RCAR_GP_PIN(2, 10),
2296};
2297static const unsigned int msiof2_ss1_c_mux[] = {
2298 MSIOF2_SS1_C_MARK,
2299};
2300static const unsigned int msiof2_ss2_c_pins[] = {
2301
2302 RCAR_GP_PIN(2, 9),
2303};
2304static const unsigned int msiof2_ss2_c_mux[] = {
2305 MSIOF2_SS2_C_MARK,
2306};
2307static const unsigned int msiof2_txd_c_pins[] = {
2308
2309 RCAR_GP_PIN(2, 14),
2310};
2311static const unsigned int msiof2_txd_c_mux[] = {
2312 MSIOF2_TXD_C_MARK,
2313};
2314static const unsigned int msiof2_rxd_c_pins[] = {
2315
2316 RCAR_GP_PIN(2, 13),
2317};
2318static const unsigned int msiof2_rxd_c_mux[] = {
2319 MSIOF2_RXD_C_MARK,
2320};
2321static const unsigned int msiof2_clk_d_pins[] = {
2322
2323 RCAR_GP_PIN(0, 8),
2324};
2325static const unsigned int msiof2_clk_d_mux[] = {
2326 MSIOF2_SCK_D_MARK,
2327};
2328static const unsigned int msiof2_sync_d_pins[] = {
2329
2330 RCAR_GP_PIN(0, 9),
2331};
2332static const unsigned int msiof2_sync_d_mux[] = {
2333 MSIOF2_SYNC_D_MARK,
2334};
2335static const unsigned int msiof2_ss1_d_pins[] = {
2336
2337 RCAR_GP_PIN(0, 12),
2338};
2339static const unsigned int msiof2_ss1_d_mux[] = {
2340 MSIOF2_SS1_D_MARK,
2341};
2342static const unsigned int msiof2_ss2_d_pins[] = {
2343
2344 RCAR_GP_PIN(0, 13),
2345};
2346static const unsigned int msiof2_ss2_d_mux[] = {
2347 MSIOF2_SS2_D_MARK,
2348};
2349static const unsigned int msiof2_txd_d_pins[] = {
2350
2351 RCAR_GP_PIN(0, 11),
2352};
2353static const unsigned int msiof2_txd_d_mux[] = {
2354 MSIOF2_TXD_D_MARK,
2355};
2356static const unsigned int msiof2_rxd_d_pins[] = {
2357
2358 RCAR_GP_PIN(0, 10),
2359};
2360static const unsigned int msiof2_rxd_d_mux[] = {
2361 MSIOF2_RXD_D_MARK,
2362};
2363
2364static const unsigned int msiof3_clk_a_pins[] = {
2365
2366 RCAR_GP_PIN(0, 0),
2367};
2368static const unsigned int msiof3_clk_a_mux[] = {
2369 MSIOF3_SCK_A_MARK,
2370};
2371static const unsigned int msiof3_sync_a_pins[] = {
2372
2373 RCAR_GP_PIN(0, 1),
2374};
2375static const unsigned int msiof3_sync_a_mux[] = {
2376 MSIOF3_SYNC_A_MARK,
2377};
2378static const unsigned int msiof3_ss1_a_pins[] = {
2379
2380 RCAR_GP_PIN(0, 14),
2381};
2382static const unsigned int msiof3_ss1_a_mux[] = {
2383 MSIOF3_SS1_A_MARK,
2384};
2385static const unsigned int msiof3_ss2_a_pins[] = {
2386
2387 RCAR_GP_PIN(0, 15),
2388};
2389static const unsigned int msiof3_ss2_a_mux[] = {
2390 MSIOF3_SS2_A_MARK,
2391};
2392static const unsigned int msiof3_txd_a_pins[] = {
2393
2394 RCAR_GP_PIN(0, 3),
2395};
2396static const unsigned int msiof3_txd_a_mux[] = {
2397 MSIOF3_TXD_A_MARK,
2398};
2399static const unsigned int msiof3_rxd_a_pins[] = {
2400
2401 RCAR_GP_PIN(0, 2),
2402};
2403static const unsigned int msiof3_rxd_a_mux[] = {
2404 MSIOF3_RXD_A_MARK,
2405};
2406static const unsigned int msiof3_clk_b_pins[] = {
2407
2408 RCAR_GP_PIN(1, 2),
2409};
2410static const unsigned int msiof3_clk_b_mux[] = {
2411 MSIOF3_SCK_B_MARK,
2412};
2413static const unsigned int msiof3_sync_b_pins[] = {
2414
2415 RCAR_GP_PIN(1, 0),
2416};
2417static const unsigned int msiof3_sync_b_mux[] = {
2418 MSIOF3_SYNC_B_MARK,
2419};
2420static const unsigned int msiof3_ss1_b_pins[] = {
2421
2422 RCAR_GP_PIN(1, 4),
2423};
2424static const unsigned int msiof3_ss1_b_mux[] = {
2425 MSIOF3_SS1_B_MARK,
2426};
2427static const unsigned int msiof3_ss2_b_pins[] = {
2428
2429 RCAR_GP_PIN(1, 5),
2430};
2431static const unsigned int msiof3_ss2_b_mux[] = {
2432 MSIOF3_SS2_B_MARK,
2433};
2434static const unsigned int msiof3_txd_b_pins[] = {
2435
2436 RCAR_GP_PIN(1, 1),
2437};
2438static const unsigned int msiof3_txd_b_mux[] = {
2439 MSIOF3_TXD_B_MARK,
2440};
2441static const unsigned int msiof3_rxd_b_pins[] = {
2442
2443 RCAR_GP_PIN(1, 3),
2444};
2445static const unsigned int msiof3_rxd_b_mux[] = {
2446 MSIOF3_RXD_B_MARK,
2447};
2448static const unsigned int msiof3_clk_c_pins[] = {
2449
2450 RCAR_GP_PIN(1, 12),
2451};
2452static const unsigned int msiof3_clk_c_mux[] = {
2453 MSIOF3_SCK_C_MARK,
2454};
2455static const unsigned int msiof3_sync_c_pins[] = {
2456
2457 RCAR_GP_PIN(1, 13),
2458};
2459static const unsigned int msiof3_sync_c_mux[] = {
2460 MSIOF3_SYNC_C_MARK,
2461};
2462static const unsigned int msiof3_txd_c_pins[] = {
2463
2464 RCAR_GP_PIN(1, 15),
2465};
2466static const unsigned int msiof3_txd_c_mux[] = {
2467 MSIOF3_TXD_C_MARK,
2468};
2469static const unsigned int msiof3_rxd_c_pins[] = {
2470
2471 RCAR_GP_PIN(1, 14),
2472};
2473static const unsigned int msiof3_rxd_c_mux[] = {
2474 MSIOF3_RXD_C_MARK,
2475};
2476static const unsigned int msiof3_clk_d_pins[] = {
2477
2478 RCAR_GP_PIN(1, 22),
2479};
2480static const unsigned int msiof3_clk_d_mux[] = {
2481 MSIOF3_SCK_D_MARK,
2482};
2483static const unsigned int msiof3_sync_d_pins[] = {
2484
2485 RCAR_GP_PIN(1, 23),
2486};
2487static const unsigned int msiof3_sync_d_mux[] = {
2488 MSIOF3_SYNC_D_MARK,
2489};
2490static const unsigned int msiof3_ss1_d_pins[] = {
2491
2492 RCAR_GP_PIN(1, 26),
2493};
2494static const unsigned int msiof3_ss1_d_mux[] = {
2495 MSIOF3_SS1_D_MARK,
2496};
2497static const unsigned int msiof3_txd_d_pins[] = {
2498
2499 RCAR_GP_PIN(1, 25),
2500};
2501static const unsigned int msiof3_txd_d_mux[] = {
2502 MSIOF3_TXD_D_MARK,
2503};
2504static const unsigned int msiof3_rxd_d_pins[] = {
2505
2506 RCAR_GP_PIN(1, 24),
2507};
2508static const unsigned int msiof3_rxd_d_mux[] = {
2509 MSIOF3_RXD_D_MARK,
2510};
2511static const unsigned int msiof3_clk_e_pins[] = {
2512
2513 RCAR_GP_PIN(2, 3),
2514};
2515static const unsigned int msiof3_clk_e_mux[] = {
2516 MSIOF3_SCK_E_MARK,
2517};
2518static const unsigned int msiof3_sync_e_pins[] = {
2519
2520 RCAR_GP_PIN(2, 2),
2521};
2522static const unsigned int msiof3_sync_e_mux[] = {
2523 MSIOF3_SYNC_E_MARK,
2524};
2525static const unsigned int msiof3_ss1_e_pins[] = {
2526
2527 RCAR_GP_PIN(2, 1),
2528};
2529static const unsigned int msiof3_ss1_e_mux[] = {
2530 MSIOF3_SS1_E_MARK,
2531};
2532static const unsigned int msiof3_ss2_e_pins[] = {
2533
2534 RCAR_GP_PIN(2, 0),
2535};
2536static const unsigned int msiof3_ss2_e_mux[] = {
2537 MSIOF3_SS2_E_MARK,
2538};
2539static const unsigned int msiof3_txd_e_pins[] = {
2540
2541 RCAR_GP_PIN(2, 5),
2542};
2543static const unsigned int msiof3_txd_e_mux[] = {
2544 MSIOF3_TXD_E_MARK,
2545};
2546static const unsigned int msiof3_rxd_e_pins[] = {
2547
2548 RCAR_GP_PIN(2, 4),
2549};
2550static const unsigned int msiof3_rxd_e_mux[] = {
2551 MSIOF3_RXD_E_MARK,
2552};
2553
2554
2555static const unsigned int pwm0_pins[] = {
2556
2557 RCAR_GP_PIN(2, 6),
2558};
2559static const unsigned int pwm0_mux[] = {
2560 PWM0_MARK,
2561};
2562
2563static const unsigned int pwm1_a_pins[] = {
2564
2565 RCAR_GP_PIN(2, 7),
2566};
2567static const unsigned int pwm1_a_mux[] = {
2568 PWM1_A_MARK,
2569};
2570static const unsigned int pwm1_b_pins[] = {
2571
2572 RCAR_GP_PIN(1, 8),
2573};
2574static const unsigned int pwm1_b_mux[] = {
2575 PWM1_B_MARK,
2576};
2577
2578static const unsigned int pwm2_a_pins[] = {
2579
2580 RCAR_GP_PIN(2, 8),
2581};
2582static const unsigned int pwm2_a_mux[] = {
2583 PWM2_A_MARK,
2584};
2585static const unsigned int pwm2_b_pins[] = {
2586
2587 RCAR_GP_PIN(1, 11),
2588};
2589static const unsigned int pwm2_b_mux[] = {
2590 PWM2_B_MARK,
2591};
2592
2593static const unsigned int pwm3_a_pins[] = {
2594
2595 RCAR_GP_PIN(1, 0),
2596};
2597static const unsigned int pwm3_a_mux[] = {
2598 PWM3_A_MARK,
2599};
2600static const unsigned int pwm3_b_pins[] = {
2601
2602 RCAR_GP_PIN(2, 2),
2603};
2604static const unsigned int pwm3_b_mux[] = {
2605 PWM3_B_MARK,
2606};
2607
2608static const unsigned int pwm4_a_pins[] = {
2609
2610 RCAR_GP_PIN(1, 1),
2611};
2612static const unsigned int pwm4_a_mux[] = {
2613 PWM4_A_MARK,
2614};
2615static const unsigned int pwm4_b_pins[] = {
2616
2617 RCAR_GP_PIN(2, 3),
2618};
2619static const unsigned int pwm4_b_mux[] = {
2620 PWM4_B_MARK,
2621};
2622
2623static const unsigned int pwm5_a_pins[] = {
2624
2625 RCAR_GP_PIN(1, 2),
2626};
2627static const unsigned int pwm5_a_mux[] = {
2628 PWM5_A_MARK,
2629};
2630static const unsigned int pwm5_b_pins[] = {
2631
2632 RCAR_GP_PIN(2, 4),
2633};
2634static const unsigned int pwm5_b_mux[] = {
2635 PWM5_B_MARK,
2636};
2637
2638static const unsigned int pwm6_a_pins[] = {
2639
2640 RCAR_GP_PIN(1, 3),
2641};
2642static const unsigned int pwm6_a_mux[] = {
2643 PWM6_A_MARK,
2644};
2645static const unsigned int pwm6_b_pins[] = {
2646
2647 RCAR_GP_PIN(2, 5),
2648};
2649static const unsigned int pwm6_b_mux[] = {
2650 PWM6_B_MARK,
2651};
2652
2653
2654static const unsigned int scif0_data_pins[] = {
2655
2656 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2657};
2658static const unsigned int scif0_data_mux[] = {
2659 RX0_MARK, TX0_MARK,
2660};
2661static const unsigned int scif0_clk_pins[] = {
2662
2663 RCAR_GP_PIN(5, 0),
2664};
2665static const unsigned int scif0_clk_mux[] = {
2666 SCK0_MARK,
2667};
2668static const unsigned int scif0_ctrl_pins[] = {
2669
2670 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2671};
2672static const unsigned int scif0_ctrl_mux[] = {
2673 RTS0_N_MARK, CTS0_N_MARK,
2674};
2675
2676static const unsigned int scif1_data_a_pins[] = {
2677
2678 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2679};
2680static const unsigned int scif1_data_a_mux[] = {
2681 RX1_A_MARK, TX1_A_MARK,
2682};
2683static const unsigned int scif1_clk_pins[] = {
2684
2685 RCAR_GP_PIN(6, 21),
2686};
2687static const unsigned int scif1_clk_mux[] = {
2688 SCK1_MARK,
2689};
2690static const unsigned int scif1_ctrl_pins[] = {
2691
2692 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2693};
2694static const unsigned int scif1_ctrl_mux[] = {
2695 RTS1_N_MARK, CTS1_N_MARK,
2696};
2697static const unsigned int scif1_data_b_pins[] = {
2698
2699 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2700};
2701static const unsigned int scif1_data_b_mux[] = {
2702 RX1_B_MARK, TX1_B_MARK,
2703};
2704
2705static const unsigned int scif2_data_a_pins[] = {
2706
2707 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2708};
2709static const unsigned int scif2_data_a_mux[] = {
2710 RX2_A_MARK, TX2_A_MARK,
2711};
2712static const unsigned int scif2_clk_pins[] = {
2713
2714 RCAR_GP_PIN(5, 9),
2715};
2716static const unsigned int scif2_clk_mux[] = {
2717 SCK2_MARK,
2718};
2719static const unsigned int scif2_data_b_pins[] = {
2720
2721 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2722};
2723static const unsigned int scif2_data_b_mux[] = {
2724 RX2_B_MARK, TX2_B_MARK,
2725};
2726
2727static const unsigned int scif3_data_a_pins[] = {
2728
2729 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2730};
2731static const unsigned int scif3_data_a_mux[] = {
2732 RX3_A_MARK, TX3_A_MARK,
2733};
2734static const unsigned int scif3_clk_pins[] = {
2735
2736 RCAR_GP_PIN(1, 22),
2737};
2738static const unsigned int scif3_clk_mux[] = {
2739 SCK3_MARK,
2740};
2741static const unsigned int scif3_ctrl_pins[] = {
2742
2743 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2744};
2745static const unsigned int scif3_ctrl_mux[] = {
2746 RTS3_N_MARK, CTS3_N_MARK,
2747};
2748static const unsigned int scif3_data_b_pins[] = {
2749
2750 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2751};
2752static const unsigned int scif3_data_b_mux[] = {
2753 RX3_B_MARK, TX3_B_MARK,
2754};
2755
2756static const unsigned int scif4_data_a_pins[] = {
2757
2758 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2759};
2760static const unsigned int scif4_data_a_mux[] = {
2761 RX4_A_MARK, TX4_A_MARK,
2762};
2763static const unsigned int scif4_clk_a_pins[] = {
2764
2765 RCAR_GP_PIN(2, 10),
2766};
2767static const unsigned int scif4_clk_a_mux[] = {
2768 SCK4_A_MARK,
2769};
2770static const unsigned int scif4_ctrl_a_pins[] = {
2771
2772 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2773};
2774static const unsigned int scif4_ctrl_a_mux[] = {
2775 RTS4_N_A_MARK, CTS4_N_A_MARK,
2776};
2777static const unsigned int scif4_data_b_pins[] = {
2778
2779 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2780};
2781static const unsigned int scif4_data_b_mux[] = {
2782 RX4_B_MARK, TX4_B_MARK,
2783};
2784static const unsigned int scif4_clk_b_pins[] = {
2785
2786 RCAR_GP_PIN(1, 5),
2787};
2788static const unsigned int scif4_clk_b_mux[] = {
2789 SCK4_B_MARK,
2790};
2791static const unsigned int scif4_ctrl_b_pins[] = {
2792
2793 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2794};
2795static const unsigned int scif4_ctrl_b_mux[] = {
2796 RTS4_N_B_MARK, CTS4_N_B_MARK,
2797};
2798static const unsigned int scif4_data_c_pins[] = {
2799
2800 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2801};
2802static const unsigned int scif4_data_c_mux[] = {
2803 RX4_C_MARK, TX4_C_MARK,
2804};
2805static const unsigned int scif4_clk_c_pins[] = {
2806
2807 RCAR_GP_PIN(0, 8),
2808};
2809static const unsigned int scif4_clk_c_mux[] = {
2810 SCK4_C_MARK,
2811};
2812static const unsigned int scif4_ctrl_c_pins[] = {
2813
2814 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2815};
2816static const unsigned int scif4_ctrl_c_mux[] = {
2817 RTS4_N_C_MARK, CTS4_N_C_MARK,
2818};
2819
2820static const unsigned int scif5_data_a_pins[] = {
2821
2822 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2823};
2824static const unsigned int scif5_data_a_mux[] = {
2825 RX5_A_MARK, TX5_A_MARK,
2826};
2827static const unsigned int scif5_clk_a_pins[] = {
2828
2829 RCAR_GP_PIN(6, 21),
2830};
2831static const unsigned int scif5_clk_a_mux[] = {
2832 SCK5_A_MARK,
2833};
2834static const unsigned int scif5_data_b_pins[] = {
2835
2836 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2837};
2838static const unsigned int scif5_data_b_mux[] = {
2839 RX5_B_MARK, TX5_B_MARK,
2840};
2841static const unsigned int scif5_clk_b_pins[] = {
2842
2843 RCAR_GP_PIN(5, 0),
2844};
2845static const unsigned int scif5_clk_b_mux[] = {
2846 SCK5_B_MARK,
2847};
2848
2849static const unsigned int scif_clk_a_pins[] = {
2850
2851 RCAR_GP_PIN(6, 23),
2852};
2853static const unsigned int scif_clk_a_mux[] = {
2854 SCIF_CLK_A_MARK,
2855};
2856static const unsigned int scif_clk_b_pins[] = {
2857
2858 RCAR_GP_PIN(5, 9),
2859};
2860static const unsigned int scif_clk_b_mux[] = {
2861 SCIF_CLK_B_MARK,
2862};
2863
2864
2865static const unsigned int sdhi0_data1_pins[] = {
2866
2867 RCAR_GP_PIN(3, 2),
2868};
2869
2870static const unsigned int sdhi0_data1_mux[] = {
2871 SD0_DAT0_MARK,
2872};
2873
2874static const unsigned int sdhi0_data4_pins[] = {
2875
2876 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2877 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2878};
2879
2880static const unsigned int sdhi0_data4_mux[] = {
2881 SD0_DAT0_MARK, SD0_DAT1_MARK,
2882 SD0_DAT2_MARK, SD0_DAT3_MARK,
2883};
2884
2885static const unsigned int sdhi0_ctrl_pins[] = {
2886
2887 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2888};
2889
2890static const unsigned int sdhi0_ctrl_mux[] = {
2891 SD0_CLK_MARK, SD0_CMD_MARK,
2892};
2893
2894static const unsigned int sdhi0_cd_pins[] = {
2895
2896 RCAR_GP_PIN(3, 12),
2897};
2898
2899static const unsigned int sdhi0_cd_mux[] = {
2900 SD0_CD_MARK,
2901};
2902
2903static const unsigned int sdhi0_wp_pins[] = {
2904
2905 RCAR_GP_PIN(3, 13),
2906};
2907
2908static const unsigned int sdhi0_wp_mux[] = {
2909 SD0_WP_MARK,
2910};
2911
2912
2913static const unsigned int sdhi1_data1_pins[] = {
2914
2915 RCAR_GP_PIN(3, 8),
2916};
2917
2918static const unsigned int sdhi1_data1_mux[] = {
2919 SD1_DAT0_MARK,
2920};
2921
2922static const unsigned int sdhi1_data4_pins[] = {
2923
2924 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2925 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2926};
2927
2928static const unsigned int sdhi1_data4_mux[] = {
2929 SD1_DAT0_MARK, SD1_DAT1_MARK,
2930 SD1_DAT2_MARK, SD1_DAT3_MARK,
2931};
2932
2933static const unsigned int sdhi1_ctrl_pins[] = {
2934
2935 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2936};
2937
2938static const unsigned int sdhi1_ctrl_mux[] = {
2939 SD1_CLK_MARK, SD1_CMD_MARK,
2940};
2941
2942static const unsigned int sdhi1_cd_pins[] = {
2943
2944 RCAR_GP_PIN(3, 14),
2945};
2946
2947static const unsigned int sdhi1_cd_mux[] = {
2948 SD1_CD_MARK,
2949};
2950
2951static const unsigned int sdhi1_wp_pins[] = {
2952
2953 RCAR_GP_PIN(3, 15),
2954};
2955
2956static const unsigned int sdhi1_wp_mux[] = {
2957 SD1_WP_MARK,
2958};
2959
2960
2961static const unsigned int sdhi2_data1_pins[] = {
2962
2963 RCAR_GP_PIN(4, 2),
2964};
2965
2966static const unsigned int sdhi2_data1_mux[] = {
2967 SD2_DAT0_MARK,
2968};
2969
2970static const unsigned int sdhi2_data4_pins[] = {
2971
2972 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2973 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2974};
2975
2976static const unsigned int sdhi2_data4_mux[] = {
2977 SD2_DAT0_MARK, SD2_DAT1_MARK,
2978 SD2_DAT2_MARK, SD2_DAT3_MARK,
2979};
2980
2981static const unsigned int sdhi2_data8_pins[] = {
2982
2983 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2984 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2985 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2986 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2987};
2988
2989static const unsigned int sdhi2_data8_mux[] = {
2990 SD2_DAT0_MARK, SD2_DAT1_MARK,
2991 SD2_DAT2_MARK, SD2_DAT3_MARK,
2992 SD2_DAT4_MARK, SD2_DAT5_MARK,
2993 SD2_DAT6_MARK, SD2_DAT7_MARK,
2994};
2995
2996static const unsigned int sdhi2_ctrl_pins[] = {
2997
2998 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2999};
3000
3001static const unsigned int sdhi2_ctrl_mux[] = {
3002 SD2_CLK_MARK, SD2_CMD_MARK,
3003};
3004
3005static const unsigned int sdhi2_cd_a_pins[] = {
3006
3007 RCAR_GP_PIN(4, 13),
3008};
3009
3010static const unsigned int sdhi2_cd_a_mux[] = {
3011 SD2_CD_A_MARK,
3012};
3013
3014static const unsigned int sdhi2_cd_b_pins[] = {
3015
3016 RCAR_GP_PIN(5, 10),
3017};
3018
3019static const unsigned int sdhi2_cd_b_mux[] = {
3020 SD2_CD_B_MARK,
3021};
3022
3023static const unsigned int sdhi2_wp_a_pins[] = {
3024
3025 RCAR_GP_PIN(4, 14),
3026};
3027
3028static const unsigned int sdhi2_wp_a_mux[] = {
3029 SD2_WP_A_MARK,
3030};
3031
3032static const unsigned int sdhi2_wp_b_pins[] = {
3033
3034 RCAR_GP_PIN(5, 11),
3035};
3036
3037static const unsigned int sdhi2_wp_b_mux[] = {
3038 SD2_WP_B_MARK,
3039};
3040
3041static const unsigned int sdhi2_ds_pins[] = {
3042
3043 RCAR_GP_PIN(4, 6),
3044};
3045
3046static const unsigned int sdhi2_ds_mux[] = {
3047 SD2_DS_MARK,
3048};
3049
3050
3051static const unsigned int sdhi3_data1_pins[] = {
3052
3053 RCAR_GP_PIN(4, 9),
3054};
3055
3056static const unsigned int sdhi3_data1_mux[] = {
3057 SD3_DAT0_MARK,
3058};
3059
3060static const unsigned int sdhi3_data4_pins[] = {
3061
3062 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3063 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3064};
3065
3066static const unsigned int sdhi3_data4_mux[] = {
3067 SD3_DAT0_MARK, SD3_DAT1_MARK,
3068 SD3_DAT2_MARK, SD3_DAT3_MARK,
3069};
3070
3071static const unsigned int sdhi3_data8_pins[] = {
3072
3073 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3074 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3075 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3076 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3077};
3078
3079static const unsigned int sdhi3_data8_mux[] = {
3080 SD3_DAT0_MARK, SD3_DAT1_MARK,
3081 SD3_DAT2_MARK, SD3_DAT3_MARK,
3082 SD3_DAT4_MARK, SD3_DAT5_MARK,
3083 SD3_DAT6_MARK, SD3_DAT7_MARK,
3084};
3085
3086static const unsigned int sdhi3_ctrl_pins[] = {
3087
3088 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3089};
3090
3091static const unsigned int sdhi3_ctrl_mux[] = {
3092 SD3_CLK_MARK, SD3_CMD_MARK,
3093};
3094
3095static const unsigned int sdhi3_cd_pins[] = {
3096
3097 RCAR_GP_PIN(4, 15),
3098};
3099
3100static const unsigned int sdhi3_cd_mux[] = {
3101 SD3_CD_MARK,
3102};
3103
3104static const unsigned int sdhi3_wp_pins[] = {
3105
3106 RCAR_GP_PIN(4, 16),
3107};
3108
3109static const unsigned int sdhi3_wp_mux[] = {
3110 SD3_WP_MARK,
3111};
3112
3113static const unsigned int sdhi3_ds_pins[] = {
3114
3115 RCAR_GP_PIN(4, 17),
3116};
3117
3118static const unsigned int sdhi3_ds_mux[] = {
3119 SD3_DS_MARK,
3120};
3121
3122
3123static const unsigned int usb0_pins[] = {
3124
3125 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3126};
3127
3128static const unsigned int usb0_mux[] = {
3129 USB0_PWEN_MARK, USB0_OVC_MARK,
3130};
3131
3132
3133static const unsigned int usb1_pins[] = {
3134
3135 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3136};
3137
3138static const unsigned int usb1_mux[] = {
3139 USB1_PWEN_MARK, USB1_OVC_MARK,
3140};
3141
3142
3143static const unsigned int usb30_pins[] = {
3144
3145 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3146};
3147
3148static const unsigned int usb30_mux[] = {
3149 USB30_PWEN_MARK, USB30_OVC_MARK,
3150};
3151
3152static const struct sh_pfc_pin_group pinmux_groups[] = {
3153 SH_PFC_PIN_GROUP(avb_link),
3154 SH_PFC_PIN_GROUP(avb_magic),
3155 SH_PFC_PIN_GROUP(avb_phy_int),
3156 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),
3157 SH_PFC_PIN_GROUP(avb_mdio),
3158 SH_PFC_PIN_GROUP(avb_mii),
3159 SH_PFC_PIN_GROUP(avb_avtp_pps),
3160 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3161 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3162 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3163 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3164 SH_PFC_PIN_GROUP(du_rgb666),
3165 SH_PFC_PIN_GROUP(du_rgb888),
3166 SH_PFC_PIN_GROUP(du_clk_out_0),
3167 SH_PFC_PIN_GROUP(du_clk_out_1),
3168 SH_PFC_PIN_GROUP(du_sync),
3169 SH_PFC_PIN_GROUP(du_oddf),
3170 SH_PFC_PIN_GROUP(du_cde),
3171 SH_PFC_PIN_GROUP(du_disp),
3172 SH_PFC_PIN_GROUP(i2c1_a),
3173 SH_PFC_PIN_GROUP(i2c1_b),
3174 SH_PFC_PIN_GROUP(i2c2_a),
3175 SH_PFC_PIN_GROUP(i2c2_b),
3176 SH_PFC_PIN_GROUP(i2c6_a),
3177 SH_PFC_PIN_GROUP(i2c6_b),
3178 SH_PFC_PIN_GROUP(i2c6_c),
3179 SH_PFC_PIN_GROUP(intc_ex_irq0),
3180 SH_PFC_PIN_GROUP(intc_ex_irq1),
3181 SH_PFC_PIN_GROUP(intc_ex_irq2),
3182 SH_PFC_PIN_GROUP(intc_ex_irq3),
3183 SH_PFC_PIN_GROUP(intc_ex_irq4),
3184 SH_PFC_PIN_GROUP(intc_ex_irq5),
3185 SH_PFC_PIN_GROUP(msiof0_clk),
3186 SH_PFC_PIN_GROUP(msiof0_sync),
3187 SH_PFC_PIN_GROUP(msiof0_ss1),
3188 SH_PFC_PIN_GROUP(msiof0_ss2),
3189 SH_PFC_PIN_GROUP(msiof0_txd),
3190 SH_PFC_PIN_GROUP(msiof0_rxd),
3191 SH_PFC_PIN_GROUP(msiof1_clk_a),
3192 SH_PFC_PIN_GROUP(msiof1_sync_a),
3193 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3194 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3195 SH_PFC_PIN_GROUP(msiof1_txd_a),
3196 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3197 SH_PFC_PIN_GROUP(msiof1_clk_b),
3198 SH_PFC_PIN_GROUP(msiof1_sync_b),
3199 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3200 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3201 SH_PFC_PIN_GROUP(msiof1_txd_b),
3202 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3203 SH_PFC_PIN_GROUP(msiof1_clk_c),
3204 SH_PFC_PIN_GROUP(msiof1_sync_c),
3205 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3206 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3207 SH_PFC_PIN_GROUP(msiof1_txd_c),
3208 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3209 SH_PFC_PIN_GROUP(msiof1_clk_d),
3210 SH_PFC_PIN_GROUP(msiof1_sync_d),
3211 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3212 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3213 SH_PFC_PIN_GROUP(msiof1_txd_d),
3214 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3215 SH_PFC_PIN_GROUP(msiof1_clk_e),
3216 SH_PFC_PIN_GROUP(msiof1_sync_e),
3217 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3218 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3219 SH_PFC_PIN_GROUP(msiof1_txd_e),
3220 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3221 SH_PFC_PIN_GROUP(msiof1_clk_f),
3222 SH_PFC_PIN_GROUP(msiof1_sync_f),
3223 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3224 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3225 SH_PFC_PIN_GROUP(msiof1_txd_f),
3226 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3227 SH_PFC_PIN_GROUP(msiof1_clk_g),
3228 SH_PFC_PIN_GROUP(msiof1_sync_g),
3229 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3230 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3231 SH_PFC_PIN_GROUP(msiof1_txd_g),
3232 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3233 SH_PFC_PIN_GROUP(msiof2_clk_a),
3234 SH_PFC_PIN_GROUP(msiof2_sync_a),
3235 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3236 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3237 SH_PFC_PIN_GROUP(msiof2_txd_a),
3238 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3239 SH_PFC_PIN_GROUP(msiof2_clk_b),
3240 SH_PFC_PIN_GROUP(msiof2_sync_b),
3241 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3242 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3243 SH_PFC_PIN_GROUP(msiof2_txd_b),
3244 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3245 SH_PFC_PIN_GROUP(msiof2_clk_c),
3246 SH_PFC_PIN_GROUP(msiof2_sync_c),
3247 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3248 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3249 SH_PFC_PIN_GROUP(msiof2_txd_c),
3250 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3251 SH_PFC_PIN_GROUP(msiof2_clk_d),
3252 SH_PFC_PIN_GROUP(msiof2_sync_d),
3253 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3254 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3255 SH_PFC_PIN_GROUP(msiof2_txd_d),
3256 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3257 SH_PFC_PIN_GROUP(msiof3_clk_a),
3258 SH_PFC_PIN_GROUP(msiof3_sync_a),
3259 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3260 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3261 SH_PFC_PIN_GROUP(msiof3_txd_a),
3262 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3263 SH_PFC_PIN_GROUP(msiof3_clk_b),
3264 SH_PFC_PIN_GROUP(msiof3_sync_b),
3265 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3266 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3267 SH_PFC_PIN_GROUP(msiof3_txd_b),
3268 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3269 SH_PFC_PIN_GROUP(msiof3_clk_c),
3270 SH_PFC_PIN_GROUP(msiof3_sync_c),
3271 SH_PFC_PIN_GROUP(msiof3_txd_c),
3272 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3273 SH_PFC_PIN_GROUP(msiof3_clk_d),
3274 SH_PFC_PIN_GROUP(msiof3_sync_d),
3275 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3276 SH_PFC_PIN_GROUP(msiof3_txd_d),
3277 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3278 SH_PFC_PIN_GROUP(msiof3_clk_e),
3279 SH_PFC_PIN_GROUP(msiof3_sync_e),
3280 SH_PFC_PIN_GROUP(msiof3_ss1_e),
3281 SH_PFC_PIN_GROUP(msiof3_ss2_e),
3282 SH_PFC_PIN_GROUP(msiof3_txd_e),
3283 SH_PFC_PIN_GROUP(msiof3_rxd_e),
3284 SH_PFC_PIN_GROUP(pwm0),
3285 SH_PFC_PIN_GROUP(pwm1_a),
3286 SH_PFC_PIN_GROUP(pwm1_b),
3287 SH_PFC_PIN_GROUP(pwm2_a),
3288 SH_PFC_PIN_GROUP(pwm2_b),
3289 SH_PFC_PIN_GROUP(pwm3_a),
3290 SH_PFC_PIN_GROUP(pwm3_b),
3291 SH_PFC_PIN_GROUP(pwm4_a),
3292 SH_PFC_PIN_GROUP(pwm4_b),
3293 SH_PFC_PIN_GROUP(pwm5_a),
3294 SH_PFC_PIN_GROUP(pwm5_b),
3295 SH_PFC_PIN_GROUP(pwm6_a),
3296 SH_PFC_PIN_GROUP(pwm6_b),
3297 SH_PFC_PIN_GROUP(scif0_data),
3298 SH_PFC_PIN_GROUP(scif0_clk),
3299 SH_PFC_PIN_GROUP(scif0_ctrl),
3300 SH_PFC_PIN_GROUP(scif1_data_a),
3301 SH_PFC_PIN_GROUP(scif1_clk),
3302 SH_PFC_PIN_GROUP(scif1_ctrl),
3303 SH_PFC_PIN_GROUP(scif1_data_b),
3304 SH_PFC_PIN_GROUP(scif2_data_a),
3305 SH_PFC_PIN_GROUP(scif2_clk),
3306 SH_PFC_PIN_GROUP(scif2_data_b),
3307 SH_PFC_PIN_GROUP(scif3_data_a),
3308 SH_PFC_PIN_GROUP(scif3_clk),
3309 SH_PFC_PIN_GROUP(scif3_ctrl),
3310 SH_PFC_PIN_GROUP(scif3_data_b),
3311 SH_PFC_PIN_GROUP(scif4_data_a),
3312 SH_PFC_PIN_GROUP(scif4_clk_a),
3313 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3314 SH_PFC_PIN_GROUP(scif4_data_b),
3315 SH_PFC_PIN_GROUP(scif4_clk_b),
3316 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3317 SH_PFC_PIN_GROUP(scif4_data_c),
3318 SH_PFC_PIN_GROUP(scif4_clk_c),
3319 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3320 SH_PFC_PIN_GROUP(scif5_data_a),
3321 SH_PFC_PIN_GROUP(scif5_clk_a),
3322 SH_PFC_PIN_GROUP(scif5_data_b),
3323 SH_PFC_PIN_GROUP(scif5_clk_b),
3324 SH_PFC_PIN_GROUP(scif_clk_a),
3325 SH_PFC_PIN_GROUP(scif_clk_b),
3326 SH_PFC_PIN_GROUP(sdhi0_data1),
3327 SH_PFC_PIN_GROUP(sdhi0_data4),
3328 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3329 SH_PFC_PIN_GROUP(sdhi0_cd),
3330 SH_PFC_PIN_GROUP(sdhi0_wp),
3331 SH_PFC_PIN_GROUP(sdhi1_data1),
3332 SH_PFC_PIN_GROUP(sdhi1_data4),
3333 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3334 SH_PFC_PIN_GROUP(sdhi1_cd),
3335 SH_PFC_PIN_GROUP(sdhi1_wp),
3336 SH_PFC_PIN_GROUP(sdhi2_data1),
3337 SH_PFC_PIN_GROUP(sdhi2_data4),
3338 SH_PFC_PIN_GROUP(sdhi2_data8),
3339 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3340 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3341 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3342 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3343 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3344 SH_PFC_PIN_GROUP(sdhi2_ds),
3345 SH_PFC_PIN_GROUP(sdhi3_data1),
3346 SH_PFC_PIN_GROUP(sdhi3_data4),
3347 SH_PFC_PIN_GROUP(sdhi3_data8),
3348 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3349 SH_PFC_PIN_GROUP(sdhi3_cd),
3350 SH_PFC_PIN_GROUP(sdhi3_wp),
3351 SH_PFC_PIN_GROUP(sdhi3_ds),
3352 SH_PFC_PIN_GROUP(usb0),
3353 SH_PFC_PIN_GROUP(usb1),
3354 SH_PFC_PIN_GROUP(usb30),
3355};
3356
3357static const char * const avb_groups[] = {
3358 "avb_link",
3359 "avb_magic",
3360 "avb_phy_int",
3361 "avb_mdc",
3362 "avb_mdio",
3363 "avb_mii",
3364 "avb_avtp_pps",
3365 "avb_avtp_match_a",
3366 "avb_avtp_capture_a",
3367 "avb_avtp_match_b",
3368 "avb_avtp_capture_b",
3369};
3370
3371static const char * const du_groups[] = {
3372 "du_rgb666",
3373 "du_rgb888",
3374 "du_clk_out_0",
3375 "du_clk_out_1",
3376 "du_sync",
3377 "du_oddf",
3378 "du_cde",
3379 "du_disp",
3380};
3381
3382static const char * const i2c1_groups[] = {
3383 "i2c1_a",
3384 "i2c1_b",
3385};
3386
3387static const char * const i2c2_groups[] = {
3388 "i2c2_a",
3389 "i2c2_b",
3390};
3391
3392static const char * const i2c6_groups[] = {
3393 "i2c6_a",
3394 "i2c6_b",
3395 "i2c6_c",
3396};
3397
3398static const char * const intc_ex_groups[] = {
3399 "intc_ex_irq0",
3400 "intc_ex_irq1",
3401 "intc_ex_irq2",
3402 "intc_ex_irq3",
3403 "intc_ex_irq4",
3404 "intc_ex_irq5",
3405};
3406
3407static const char * const msiof0_groups[] = {
3408 "msiof0_clk",
3409 "msiof0_sync",
3410 "msiof0_ss1",
3411 "msiof0_ss2",
3412 "msiof0_txd",
3413 "msiof0_rxd",
3414};
3415
3416static const char * const msiof1_groups[] = {
3417 "msiof1_clk_a",
3418 "msiof1_sync_a",
3419 "msiof1_ss1_a",
3420 "msiof1_ss2_a",
3421 "msiof1_txd_a",
3422 "msiof1_rxd_a",
3423 "msiof1_clk_b",
3424 "msiof1_sync_b",
3425 "msiof1_ss1_b",
3426 "msiof1_ss2_b",
3427 "msiof1_txd_b",
3428 "msiof1_rxd_b",
3429 "msiof1_clk_c",
3430 "msiof1_sync_c",
3431 "msiof1_ss1_c",
3432 "msiof1_ss2_c",
3433 "msiof1_txd_c",
3434 "msiof1_rxd_c",
3435 "msiof1_clk_d",
3436 "msiof1_sync_d",
3437 "msiof1_ss1_d",
3438 "msiof1_ss2_d",
3439 "msiof1_txd_d",
3440 "msiof1_rxd_d",
3441 "msiof1_clk_e",
3442 "msiof1_sync_e",
3443 "msiof1_ss1_e",
3444 "msiof1_ss2_e",
3445 "msiof1_txd_e",
3446 "msiof1_rxd_e",
3447 "msiof1_clk_f",
3448 "msiof1_sync_f",
3449 "msiof1_ss1_f",
3450 "msiof1_ss2_f",
3451 "msiof1_txd_f",
3452 "msiof1_rxd_f",
3453 "msiof1_clk_g",
3454 "msiof1_sync_g",
3455 "msiof1_ss1_g",
3456 "msiof1_ss2_g",
3457 "msiof1_txd_g",
3458 "msiof1_rxd_g",
3459};
3460
3461static const char * const msiof2_groups[] = {
3462 "msiof2_clk_a",
3463 "msiof2_sync_a",
3464 "msiof2_ss1_a",
3465 "msiof2_ss2_a",
3466 "msiof2_txd_a",
3467 "msiof2_rxd_a",
3468 "msiof2_clk_b",
3469 "msiof2_sync_b",
3470 "msiof2_ss1_b",
3471 "msiof2_ss2_b",
3472 "msiof2_txd_b",
3473 "msiof2_rxd_b",
3474 "msiof2_clk_c",
3475 "msiof2_sync_c",
3476 "msiof2_ss1_c",
3477 "msiof2_ss2_c",
3478 "msiof2_txd_c",
3479 "msiof2_rxd_c",
3480 "msiof2_clk_d",
3481 "msiof2_sync_d",
3482 "msiof2_ss1_d",
3483 "msiof2_ss2_d",
3484 "msiof2_txd_d",
3485 "msiof2_rxd_d",
3486};
3487
3488static const char * const msiof3_groups[] = {
3489 "msiof3_clk_a",
3490 "msiof3_sync_a",
3491 "msiof3_ss1_a",
3492 "msiof3_ss2_a",
3493 "msiof3_txd_a",
3494 "msiof3_rxd_a",
3495 "msiof3_clk_b",
3496 "msiof3_sync_b",
3497 "msiof3_ss1_b",
3498 "msiof3_ss2_b",
3499 "msiof3_txd_b",
3500 "msiof3_rxd_b",
3501 "msiof3_clk_c",
3502 "msiof3_sync_c",
3503 "msiof3_txd_c",
3504 "msiof3_rxd_c",
3505 "msiof3_clk_d",
3506 "msiof3_sync_d",
3507 "msiof3_ss1_d",
3508 "msiof3_txd_d",
3509 "msiof3_rxd_d",
3510 "msiof3_clk_e",
3511 "msiof3_sync_e",
3512 "msiof3_ss1_e",
3513 "msiof3_ss2_e",
3514 "msiof3_txd_e",
3515 "msiof3_rxd_e",
3516};
3517
3518static const char * const pwm0_groups[] = {
3519 "pwm0",
3520};
3521
3522static const char * const pwm1_groups[] = {
3523 "pwm1_a",
3524 "pwm1_b",
3525};
3526
3527static const char * const pwm2_groups[] = {
3528 "pwm2_a",
3529 "pwm2_b",
3530};
3531
3532static const char * const pwm3_groups[] = {
3533 "pwm3_a",
3534 "pwm3_b",
3535};
3536
3537static const char * const pwm4_groups[] = {
3538 "pwm4_a",
3539 "pwm4_b",
3540};
3541
3542static const char * const pwm5_groups[] = {
3543 "pwm5_a",
3544 "pwm5_b",
3545};
3546
3547static const char * const pwm6_groups[] = {
3548 "pwm6_a",
3549 "pwm6_b",
3550};
3551
3552static const char * const scif0_groups[] = {
3553 "scif0_data",
3554 "scif0_clk",
3555 "scif0_ctrl",
3556};
3557
3558static const char * const scif1_groups[] = {
3559 "scif1_data_a",
3560 "scif1_clk",
3561 "scif1_ctrl",
3562 "scif1_data_b",
3563};
3564static const char * const scif2_groups[] = {
3565 "scif2_data_a",
3566 "scif2_clk",
3567 "scif2_data_b",
3568};
3569
3570static const char * const scif3_groups[] = {
3571 "scif3_data_a",
3572 "scif3_clk",
3573 "scif3_ctrl",
3574 "scif3_data_b",
3575};
3576
3577static const char * const scif4_groups[] = {
3578 "scif4_data_a",
3579 "scif4_clk_a",
3580 "scif4_ctrl_a",
3581 "scif4_data_b",
3582 "scif4_clk_b",
3583 "scif4_ctrl_b",
3584 "scif4_data_c",
3585 "scif4_clk_c",
3586 "scif4_ctrl_c",
3587};
3588
3589static const char * const scif5_groups[] = {
3590 "scif5_data_a",
3591 "scif5_clk_a",
3592 "scif5_data_b",
3593 "scif5_clk_b",
3594};
3595
3596static const char * const scif_clk_groups[] = {
3597 "scif_clk_a",
3598 "scif_clk_b",
3599};
3600
3601static const char * const sdhi0_groups[] = {
3602 "sdhi0_data1",
3603 "sdhi0_data4",
3604 "sdhi0_ctrl",
3605 "sdhi0_cd",
3606 "sdhi0_wp",
3607};
3608
3609static const char * const sdhi1_groups[] = {
3610 "sdhi1_data1",
3611 "sdhi1_data4",
3612 "sdhi1_ctrl",
3613 "sdhi1_cd",
3614 "sdhi1_wp",
3615};
3616
3617static const char * const sdhi2_groups[] = {
3618 "sdhi2_data1",
3619 "sdhi2_data4",
3620 "sdhi2_data8",
3621 "sdhi2_ctrl",
3622 "sdhi2_cd_a",
3623 "sdhi2_wp_a",
3624 "sdhi2_cd_b",
3625 "sdhi2_wp_b",
3626 "sdhi2_ds",
3627};
3628
3629static const char * const sdhi3_groups[] = {
3630 "sdhi3_data1",
3631 "sdhi3_data4",
3632 "sdhi3_data8",
3633 "sdhi3_ctrl",
3634 "sdhi3_cd",
3635 "sdhi3_wp",
3636 "sdhi3_ds",
3637};
3638
3639static const char * const usb0_groups[] = {
3640 "usb0",
3641};
3642
3643static const char * const usb1_groups[] = {
3644 "usb1",
3645};
3646
3647static const char * const usb30_groups[] = {
3648 "usb30",
3649};
3650
3651static const struct sh_pfc_function pinmux_functions[] = {
3652 SH_PFC_FUNCTION(avb),
3653 SH_PFC_FUNCTION(du),
3654 SH_PFC_FUNCTION(i2c1),
3655 SH_PFC_FUNCTION(i2c2),
3656 SH_PFC_FUNCTION(i2c6),
3657 SH_PFC_FUNCTION(intc_ex),
3658 SH_PFC_FUNCTION(msiof0),
3659 SH_PFC_FUNCTION(msiof1),
3660 SH_PFC_FUNCTION(msiof2),
3661 SH_PFC_FUNCTION(msiof3),
3662 SH_PFC_FUNCTION(pwm0),
3663 SH_PFC_FUNCTION(pwm1),
3664 SH_PFC_FUNCTION(pwm2),
3665 SH_PFC_FUNCTION(pwm3),
3666 SH_PFC_FUNCTION(pwm4),
3667 SH_PFC_FUNCTION(pwm5),
3668 SH_PFC_FUNCTION(pwm6),
3669 SH_PFC_FUNCTION(scif0),
3670 SH_PFC_FUNCTION(scif1),
3671 SH_PFC_FUNCTION(scif2),
3672 SH_PFC_FUNCTION(scif3),
3673 SH_PFC_FUNCTION(scif4),
3674 SH_PFC_FUNCTION(scif5),
3675 SH_PFC_FUNCTION(scif_clk),
3676 SH_PFC_FUNCTION(sdhi0),
3677 SH_PFC_FUNCTION(sdhi1),
3678 SH_PFC_FUNCTION(sdhi2),
3679 SH_PFC_FUNCTION(sdhi3),
3680 SH_PFC_FUNCTION(usb0),
3681 SH_PFC_FUNCTION(usb1),
3682 SH_PFC_FUNCTION(usb30),
3683};
3684
3685static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3686#define F_(x, y) FN_##y
3687#define FM(x) FN_##x
3688 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3689 0, 0,
3690 0, 0,
3691 0, 0,
3692 0, 0,
3693 0, 0,
3694 0, 0,
3695 0, 0,
3696 0, 0,
3697 0, 0,
3698 0, 0,
3699 0, 0,
3700 0, 0,
3701 0, 0,
3702 0, 0,
3703 0, 0,
3704 0, 0,
3705 GP_0_15_FN, GPSR0_15,
3706 GP_0_14_FN, GPSR0_14,
3707 GP_0_13_FN, GPSR0_13,
3708 GP_0_12_FN, GPSR0_12,
3709 GP_0_11_FN, GPSR0_11,
3710 GP_0_10_FN, GPSR0_10,
3711 GP_0_9_FN, GPSR0_9,
3712 GP_0_8_FN, GPSR0_8,
3713 GP_0_7_FN, GPSR0_7,
3714 GP_0_6_FN, GPSR0_6,
3715 GP_0_5_FN, GPSR0_5,
3716 GP_0_4_FN, GPSR0_4,
3717 GP_0_3_FN, GPSR0_3,
3718 GP_0_2_FN, GPSR0_2,
3719 GP_0_1_FN, GPSR0_1,
3720 GP_0_0_FN, GPSR0_0, }
3721 },
3722 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3723 0, 0,
3724 0, 0,
3725 0, 0,
3726 GP_1_28_FN, GPSR1_28,
3727 GP_1_27_FN, GPSR1_27,
3728 GP_1_26_FN, GPSR1_26,
3729 GP_1_25_FN, GPSR1_25,
3730 GP_1_24_FN, GPSR1_24,
3731 GP_1_23_FN, GPSR1_23,
3732 GP_1_22_FN, GPSR1_22,
3733 GP_1_21_FN, GPSR1_21,
3734 GP_1_20_FN, GPSR1_20,
3735 GP_1_19_FN, GPSR1_19,
3736 GP_1_18_FN, GPSR1_18,
3737 GP_1_17_FN, GPSR1_17,
3738 GP_1_16_FN, GPSR1_16,
3739 GP_1_15_FN, GPSR1_15,
3740 GP_1_14_FN, GPSR1_14,
3741 GP_1_13_FN, GPSR1_13,
3742 GP_1_12_FN, GPSR1_12,
3743 GP_1_11_FN, GPSR1_11,
3744 GP_1_10_FN, GPSR1_10,
3745 GP_1_9_FN, GPSR1_9,
3746 GP_1_8_FN, GPSR1_8,
3747 GP_1_7_FN, GPSR1_7,
3748 GP_1_6_FN, GPSR1_6,
3749 GP_1_5_FN, GPSR1_5,
3750 GP_1_4_FN, GPSR1_4,
3751 GP_1_3_FN, GPSR1_3,
3752 GP_1_2_FN, GPSR1_2,
3753 GP_1_1_FN, GPSR1_1,
3754 GP_1_0_FN, GPSR1_0, }
3755 },
3756 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3757 0, 0,
3758 0, 0,
3759 0, 0,
3760 0, 0,
3761 0, 0,
3762 0, 0,
3763 0, 0,
3764 0, 0,
3765 0, 0,
3766 0, 0,
3767 0, 0,
3768 0, 0,
3769 0, 0,
3770 0, 0,
3771 0, 0,
3772 0, 0,
3773 0, 0,
3774 GP_2_14_FN, GPSR2_14,
3775 GP_2_13_FN, GPSR2_13,
3776 GP_2_12_FN, GPSR2_12,
3777 GP_2_11_FN, GPSR2_11,
3778 GP_2_10_FN, GPSR2_10,
3779 GP_2_9_FN, GPSR2_9,
3780 GP_2_8_FN, GPSR2_8,
3781 GP_2_7_FN, GPSR2_7,
3782 GP_2_6_FN, GPSR2_6,
3783 GP_2_5_FN, GPSR2_5,
3784 GP_2_4_FN, GPSR2_4,
3785 GP_2_3_FN, GPSR2_3,
3786 GP_2_2_FN, GPSR2_2,
3787 GP_2_1_FN, GPSR2_1,
3788 GP_2_0_FN, GPSR2_0, }
3789 },
3790 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3791 0, 0,
3792 0, 0,
3793 0, 0,
3794 0, 0,
3795 0, 0,
3796 0, 0,
3797 0, 0,
3798 0, 0,
3799 0, 0,
3800 0, 0,
3801 0, 0,
3802 0, 0,
3803 0, 0,
3804 0, 0,
3805 0, 0,
3806 0, 0,
3807 GP_3_15_FN, GPSR3_15,
3808 GP_3_14_FN, GPSR3_14,
3809 GP_3_13_FN, GPSR3_13,
3810 GP_3_12_FN, GPSR3_12,
3811 GP_3_11_FN, GPSR3_11,
3812 GP_3_10_FN, GPSR3_10,
3813 GP_3_9_FN, GPSR3_9,
3814 GP_3_8_FN, GPSR3_8,
3815 GP_3_7_FN, GPSR3_7,
3816 GP_3_6_FN, GPSR3_6,
3817 GP_3_5_FN, GPSR3_5,
3818 GP_3_4_FN, GPSR3_4,
3819 GP_3_3_FN, GPSR3_3,
3820 GP_3_2_FN, GPSR3_2,
3821 GP_3_1_FN, GPSR3_1,
3822 GP_3_0_FN, GPSR3_0, }
3823 },
3824 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3825 0, 0,
3826 0, 0,
3827 0, 0,
3828 0, 0,
3829 0, 0,
3830 0, 0,
3831 0, 0,
3832 0, 0,
3833 0, 0,
3834 0, 0,
3835 0, 0,
3836 0, 0,
3837 0, 0,
3838 0, 0,
3839 GP_4_17_FN, GPSR4_17,
3840 GP_4_16_FN, GPSR4_16,
3841 GP_4_15_FN, GPSR4_15,
3842 GP_4_14_FN, GPSR4_14,
3843 GP_4_13_FN, GPSR4_13,
3844 GP_4_12_FN, GPSR4_12,
3845 GP_4_11_FN, GPSR4_11,
3846 GP_4_10_FN, GPSR4_10,
3847 GP_4_9_FN, GPSR4_9,
3848 GP_4_8_FN, GPSR4_8,
3849 GP_4_7_FN, GPSR4_7,
3850 GP_4_6_FN, GPSR4_6,
3851 GP_4_5_FN, GPSR4_5,
3852 GP_4_4_FN, GPSR4_4,
3853 GP_4_3_FN, GPSR4_3,
3854 GP_4_2_FN, GPSR4_2,
3855 GP_4_1_FN, GPSR4_1,
3856 GP_4_0_FN, GPSR4_0, }
3857 },
3858 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3859 0, 0,
3860 0, 0,
3861 0, 0,
3862 0, 0,
3863 0, 0,
3864 0, 0,
3865 GP_5_25_FN, GPSR5_25,
3866 GP_5_24_FN, GPSR5_24,
3867 GP_5_23_FN, GPSR5_23,
3868 GP_5_22_FN, GPSR5_22,
3869 GP_5_21_FN, GPSR5_21,
3870 GP_5_20_FN, GPSR5_20,
3871 GP_5_19_FN, GPSR5_19,
3872 GP_5_18_FN, GPSR5_18,
3873 GP_5_17_FN, GPSR5_17,
3874 GP_5_16_FN, GPSR5_16,
3875 GP_5_15_FN, GPSR5_15,
3876 GP_5_14_FN, GPSR5_14,
3877 GP_5_13_FN, GPSR5_13,
3878 GP_5_12_FN, GPSR5_12,
3879 GP_5_11_FN, GPSR5_11,
3880 GP_5_10_FN, GPSR5_10,
3881 GP_5_9_FN, GPSR5_9,
3882 GP_5_8_FN, GPSR5_8,
3883 GP_5_7_FN, GPSR5_7,
3884 GP_5_6_FN, GPSR5_6,
3885 GP_5_5_FN, GPSR5_5,
3886 GP_5_4_FN, GPSR5_4,
3887 GP_5_3_FN, GPSR5_3,
3888 GP_5_2_FN, GPSR5_2,
3889 GP_5_1_FN, GPSR5_1,
3890 GP_5_0_FN, GPSR5_0, }
3891 },
3892 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3893 GP_6_31_FN, GPSR6_31,
3894 GP_6_30_FN, GPSR6_30,
3895 GP_6_29_FN, GPSR6_29,
3896 GP_6_28_FN, GPSR6_28,
3897 GP_6_27_FN, GPSR6_27,
3898 GP_6_26_FN, GPSR6_26,
3899 GP_6_25_FN, GPSR6_25,
3900 GP_6_24_FN, GPSR6_24,
3901 GP_6_23_FN, GPSR6_23,
3902 GP_6_22_FN, GPSR6_22,
3903 GP_6_21_FN, GPSR6_21,
3904 GP_6_20_FN, GPSR6_20,
3905 GP_6_19_FN, GPSR6_19,
3906 GP_6_18_FN, GPSR6_18,
3907 GP_6_17_FN, GPSR6_17,
3908 GP_6_16_FN, GPSR6_16,
3909 GP_6_15_FN, GPSR6_15,
3910 GP_6_14_FN, GPSR6_14,
3911 GP_6_13_FN, GPSR6_13,
3912 GP_6_12_FN, GPSR6_12,
3913 GP_6_11_FN, GPSR6_11,
3914 GP_6_10_FN, GPSR6_10,
3915 GP_6_9_FN, GPSR6_9,
3916 GP_6_8_FN, GPSR6_8,
3917 GP_6_7_FN, GPSR6_7,
3918 GP_6_6_FN, GPSR6_6,
3919 GP_6_5_FN, GPSR6_5,
3920 GP_6_4_FN, GPSR6_4,
3921 GP_6_3_FN, GPSR6_3,
3922 GP_6_2_FN, GPSR6_2,
3923 GP_6_1_FN, GPSR6_1,
3924 GP_6_0_FN, GPSR6_0, }
3925 },
3926 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3927 0, 0,
3928 0, 0,
3929 0, 0,
3930 0, 0,
3931 0, 0,
3932 0, 0,
3933 0, 0,
3934 0, 0,
3935 0, 0,
3936 0, 0,
3937 0, 0,
3938 0, 0,
3939 0, 0,
3940 0, 0,
3941 0, 0,
3942 0, 0,
3943 0, 0,
3944 0, 0,
3945 0, 0,
3946 0, 0,
3947 0, 0,
3948 0, 0,
3949 0, 0,
3950 0, 0,
3951 0, 0,
3952 0, 0,
3953 0, 0,
3954 0, 0,
3955 GP_7_3_FN, GPSR7_3,
3956 GP_7_2_FN, GPSR7_2,
3957 GP_7_1_FN, GPSR7_1,
3958 GP_7_0_FN, GPSR7_0, }
3959 },
3960#undef F_
3961#undef FM
3962
3963#define F_(x, y) x,
3964#define FM(x) FN_##x,
3965 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3966 IP0_31_28
3967 IP0_27_24
3968 IP0_23_20
3969 IP0_19_16
3970 IP0_15_12
3971 IP0_11_8
3972 IP0_7_4
3973 IP0_3_0 }
3974 },
3975 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3976 IP1_31_28
3977 IP1_27_24
3978 IP1_23_20
3979 IP1_19_16
3980 IP1_15_12
3981 IP1_11_8
3982 IP1_7_4
3983 IP1_3_0 }
3984 },
3985 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3986 IP2_31_28
3987 IP2_27_24
3988 IP2_23_20
3989 IP2_19_16
3990 IP2_15_12
3991 IP2_11_8
3992 IP2_7_4
3993 IP2_3_0 }
3994 },
3995 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3996 IP3_31_28
3997 IP3_27_24
3998 IP3_23_20
3999 IP3_19_16
4000 IP3_15_12
4001 IP3_11_8
4002 IP3_7_4
4003 IP3_3_0 }
4004 },
4005 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4006 IP4_31_28
4007 IP4_27_24
4008 IP4_23_20
4009 IP4_19_16
4010 IP4_15_12
4011 IP4_11_8
4012 IP4_7_4
4013 IP4_3_0 }
4014 },
4015 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4016 IP5_31_28
4017 IP5_27_24
4018 IP5_23_20
4019 IP5_19_16
4020 IP5_15_12
4021 IP5_11_8
4022 IP5_7_4
4023 IP5_3_0 }
4024 },
4025 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4026 IP6_31_28
4027 IP6_27_24
4028 IP6_23_20
4029 IP6_19_16
4030 IP6_15_12
4031 IP6_11_8
4032 IP6_7_4
4033 IP6_3_0 }
4034 },
4035 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4036 IP7_31_28
4037 IP7_27_24
4038 IP7_23_20
4039 IP7_19_16
4040 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4041 IP7_11_8
4042 IP7_7_4
4043 IP7_3_0 }
4044 },
4045 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4046 IP8_31_28
4047 IP8_27_24
4048 IP8_23_20
4049 IP8_19_16
4050 IP8_15_12
4051 IP8_11_8
4052 IP8_7_4
4053 IP8_3_0 }
4054 },
4055 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4056 IP9_31_28
4057 IP9_27_24
4058 IP9_23_20
4059 IP9_19_16
4060 IP9_15_12
4061 IP9_11_8
4062 IP9_7_4
4063 IP9_3_0 }
4064 },
4065 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4066 IP10_31_28
4067 IP10_27_24
4068 IP10_23_20
4069 IP10_19_16
4070 IP10_15_12
4071 IP10_11_8
4072 IP10_7_4
4073 IP10_3_0 }
4074 },
4075 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4076 IP11_31_28
4077 IP11_27_24
4078 IP11_23_20
4079 IP11_19_16
4080 IP11_15_12
4081 IP11_11_8
4082 IP11_7_4
4083 IP11_3_0 }
4084 },
4085 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4086 IP12_31_28
4087 IP12_27_24
4088 IP12_23_20
4089 IP12_19_16
4090 IP12_15_12
4091 IP12_11_8
4092 IP12_7_4
4093 IP12_3_0 }
4094 },
4095 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4096 IP13_31_28
4097 IP13_27_24
4098 IP13_23_20
4099 IP13_19_16
4100 IP13_15_12
4101 IP13_11_8
4102 IP13_7_4
4103 IP13_3_0 }
4104 },
4105 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4106 IP14_31_28
4107 IP14_27_24
4108 IP14_23_20
4109 IP14_19_16
4110 IP14_15_12
4111 IP14_11_8
4112 IP14_7_4
4113 IP14_3_0 }
4114 },
4115 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4116 IP15_31_28
4117 IP15_27_24
4118 IP15_23_20
4119 IP15_19_16
4120 IP15_15_12
4121 IP15_11_8
4122 IP15_7_4
4123 IP15_3_0 }
4124 },
4125 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4126 IP16_31_28
4127 IP16_27_24
4128 IP16_23_20
4129 IP16_19_16
4130 IP16_15_12
4131 IP16_11_8
4132 IP16_7_4
4133 IP16_3_0 }
4134 },
4135 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4136 IP17_31_28
4137 IP17_27_24
4138 IP17_23_20
4139 IP17_19_16
4140 IP17_15_12
4141 IP17_11_8
4142 IP17_7_4
4143 IP17_3_0 }
4144 },
4145 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4147 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4148 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4149 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4151 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4152 IP18_7_4
4153 IP18_3_0 }
4154 },
4155#undef F_
4156#undef FM
4157
4158#define F_(x, y) x,
4159#define FM(x) FN_##x,
4160 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4161 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4162 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4163 MOD_SEL0_31_30_29
4164 MOD_SEL0_28_27
4165 MOD_SEL0_26_25_24
4166 MOD_SEL0_23
4167 MOD_SEL0_22
4168 MOD_SEL0_21
4169 MOD_SEL0_20
4170 MOD_SEL0_19
4171 MOD_SEL0_18_17
4172 MOD_SEL0_16
4173 0, 0,
4174 MOD_SEL0_14_13
4175 MOD_SEL0_12
4176 MOD_SEL0_11
4177 MOD_SEL0_10
4178 MOD_SEL0_9_8
4179 MOD_SEL0_7_6
4180 MOD_SEL0_5
4181 MOD_SEL0_4_3
4182
4183 0, 0, 0, 0, 0, 0, 0, 0 }
4184 },
4185 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4186 2, 3, 1, 2, 3, 1, 1, 2, 1,
4187 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4188 MOD_SEL1_31_30
4189 MOD_SEL1_29_28_27
4190 MOD_SEL1_26
4191 MOD_SEL1_25_24
4192 MOD_SEL1_23_22_21
4193 MOD_SEL1_20
4194 MOD_SEL1_19
4195 MOD_SEL1_18_17
4196 MOD_SEL1_16
4197 MOD_SEL1_15_14
4198 MOD_SEL1_13
4199 MOD_SEL1_12
4200 MOD_SEL1_11
4201 MOD_SEL1_10
4202 MOD_SEL1_9
4203 0, 0, 0, 0,
4204 MOD_SEL1_6
4205 MOD_SEL1_5
4206 MOD_SEL1_4
4207 MOD_SEL1_3
4208 MOD_SEL1_2
4209 MOD_SEL1_1
4210 MOD_SEL1_0 }
4211 },
4212 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4213 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4214 4, 4, 4, 3, 1) {
4215 MOD_SEL2_31
4216 MOD_SEL2_30
4217 MOD_SEL2_29
4218 MOD_SEL2_28_27
4219 MOD_SEL2_26
4220 MOD_SEL2_25_24_23
4221 MOD_SEL2_22
4222 MOD_SEL2_21
4223 MOD_SEL2_20
4224 MOD_SEL2_19
4225 MOD_SEL2_18
4226 MOD_SEL2_17
4227
4228 0, 0,
4229
4230 0, 0, 0, 0, 0, 0, 0, 0,
4231 0, 0, 0, 0, 0, 0, 0, 0,
4232
4233 0, 0, 0, 0, 0, 0, 0, 0,
4234 0, 0, 0, 0, 0, 0, 0, 0,
4235
4236 0, 0, 0, 0, 0, 0, 0, 0,
4237 0, 0, 0, 0, 0, 0, 0, 0,
4238
4239 0, 0, 0, 0, 0, 0, 0, 0,
4240 MOD_SEL2_0 }
4241 },
4242 { },
4243};
4244
4245static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4246 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4247 { PIN_NUMBER('W', 3), 28, 2 },
4248 { PIN_A_NUMBER('C', 5), 24, 2 },
4249 { PIN_A_NUMBER('B', 4), 20, 2 },
4250 { PIN_NUMBER('Y', 6), 16, 2 },
4251 { PIN_A_NUMBER('B', 6), 12, 2 },
4252 { PIN_NUMBER('Y', 3), 8, 2 },
4253 { PIN_NUMBER('V', 3), 4, 2 },
4254 { PIN_A_NUMBER('C', 7), 0, 2 },
4255 } },
4256 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4257 { PIN_A_NUMBER('E', 5), 28, 2 },
4258 { PIN_A_NUMBER('E', 4), 24, 2 },
4259 { PIN_A_NUMBER('C', 3), 20, 2 },
4260 { PIN_NUMBER('V', 5), 16, 2 },
4261 { PIN_NUMBER('Y', 7), 12, 2 },
4262 { PIN_NUMBER('V', 6), 8, 2 },
4263 { PIN_NUMBER('V', 7), 4, 2 },
4264 { PIN_NUMBER('A', 16), 0, 3 },
4265 } },
4266 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4267 { PIN_NUMBER('B', 19), 28, 3 },
4268 { PIN_NUMBER('A', 13), 24, 3 },
4269 { PIN_NUMBER('B', 13), 20, 3 },
4270 { PIN_NUMBER('A', 14), 16, 3 },
4271 { PIN_NUMBER('B', 14), 12, 3 },
4272 { PIN_NUMBER('A', 8), 8, 3 },
4273 { PIN_NUMBER('A', 19), 4, 3 },
4274 { PIN_NUMBER('A', 18), 0, 3 },
4275 } },
4276 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4277 { PIN_NUMBER('B', 18), 28, 3 },
4278 { PIN_NUMBER('A', 17), 24, 3 },
4279 { PIN_NUMBER('B', 17), 20, 3 },
4280 { PIN_NUMBER('A', 12), 16, 3 },
4281 { PIN_NUMBER('A', 9), 12, 3 },
4282 { RCAR_GP_PIN(2, 9), 8, 3 },
4283 { RCAR_GP_PIN(2, 10), 4, 3 },
4284 { RCAR_GP_PIN(2, 11), 0, 3 },
4285 } },
4286 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4287 { RCAR_GP_PIN(2, 12), 28, 3 },
4288 { RCAR_GP_PIN(2, 13), 24, 3 },
4289 { RCAR_GP_PIN(2, 14), 20, 3 },
4290 { RCAR_GP_PIN(2, 0), 16, 3 },
4291 { RCAR_GP_PIN(2, 1), 12, 3 },
4292 { RCAR_GP_PIN(2, 2), 8, 3 },
4293 { RCAR_GP_PIN(2, 3), 4, 3 },
4294 { RCAR_GP_PIN(2, 4), 0, 3 },
4295 } },
4296 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4297 { RCAR_GP_PIN(2, 5), 28, 3 },
4298 { RCAR_GP_PIN(2, 6), 24, 3 },
4299 { RCAR_GP_PIN(2, 7), 20, 3 },
4300 { RCAR_GP_PIN(2, 8), 16, 3 },
4301 { RCAR_GP_PIN(1, 0), 12, 3 },
4302 { RCAR_GP_PIN(1, 1), 8, 3 },
4303 { RCAR_GP_PIN(1, 2), 4, 3 },
4304 { RCAR_GP_PIN(1, 3), 0, 3 },
4305 } },
4306 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4307 { RCAR_GP_PIN(1, 4), 28, 3 },
4308 { RCAR_GP_PIN(1, 5), 24, 3 },
4309 { RCAR_GP_PIN(1, 6), 20, 3 },
4310 { RCAR_GP_PIN(1, 7), 16, 3 },
4311 { RCAR_GP_PIN(1, 8), 12, 3 },
4312 { RCAR_GP_PIN(1, 9), 8, 3 },
4313 { RCAR_GP_PIN(1, 10), 4, 3 },
4314 { RCAR_GP_PIN(1, 11), 0, 3 },
4315 } },
4316 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4317 { RCAR_GP_PIN(1, 12), 28, 3 },
4318 { RCAR_GP_PIN(1, 13), 24, 3 },
4319 { RCAR_GP_PIN(1, 14), 20, 3 },
4320 { RCAR_GP_PIN(1, 15), 16, 3 },
4321 { RCAR_GP_PIN(1, 16), 12, 3 },
4322 { RCAR_GP_PIN(1, 17), 8, 3 },
4323 { RCAR_GP_PIN(1, 18), 4, 3 },
4324 { RCAR_GP_PIN(1, 19), 0, 3 },
4325 } },
4326 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4327 { RCAR_GP_PIN(1, 28), 28, 3 },
4328 { RCAR_GP_PIN(1, 20), 24, 3 },
4329 { RCAR_GP_PIN(1, 21), 20, 3 },
4330 { RCAR_GP_PIN(1, 22), 16, 3 },
4331 { RCAR_GP_PIN(1, 23), 12, 3 },
4332 { RCAR_GP_PIN(1, 24), 8, 3 },
4333 { RCAR_GP_PIN(1, 25), 4, 3 },
4334 { RCAR_GP_PIN(1, 26), 0, 3 },
4335 } },
4336 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4337 { RCAR_GP_PIN(1, 27), 28, 3 },
4338 { PIN_NUMBER('C', 1), 24, 3 },
4339 { RCAR_GP_PIN(0, 0), 20, 3 },
4340 { RCAR_GP_PIN(0, 1), 16, 3 },
4341 { RCAR_GP_PIN(0, 2), 12, 3 },
4342 { RCAR_GP_PIN(0, 3), 8, 3 },
4343 { RCAR_GP_PIN(0, 4), 4, 3 },
4344 { RCAR_GP_PIN(0, 5), 0, 3 },
4345 } },
4346 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4347 { RCAR_GP_PIN(0, 6), 28, 3 },
4348 { RCAR_GP_PIN(0, 7), 24, 3 },
4349 { RCAR_GP_PIN(0, 8), 20, 3 },
4350 { RCAR_GP_PIN(0, 9), 16, 3 },
4351 { RCAR_GP_PIN(0, 10), 12, 3 },
4352 { RCAR_GP_PIN(0, 11), 8, 3 },
4353 { RCAR_GP_PIN(0, 12), 4, 3 },
4354 { RCAR_GP_PIN(0, 13), 0, 3 },
4355 } },
4356 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4357 { RCAR_GP_PIN(0, 14), 28, 3 },
4358 { RCAR_GP_PIN(0, 15), 24, 3 },
4359 { RCAR_GP_PIN(7, 0), 20, 3 },
4360 { RCAR_GP_PIN(7, 1), 16, 3 },
4361 { RCAR_GP_PIN(7, 2), 12, 3 },
4362 { RCAR_GP_PIN(7, 3), 8, 3 },
4363 { PIN_A_NUMBER('P', 7), 4, 2 },
4364 { PIN_A_NUMBER('P', 8), 0, 2 },
4365 } },
4366 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4367 { PIN_A_NUMBER('R', 8), 28, 2 },
4368 { PIN_A_NUMBER('D', 38), 20, 2 },
4369 { PIN_A_NUMBER('R', 30), 4, 2 },
4370 } },
4371 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4372 { PIN_A_NUMBER('T', 28), 28, 2 },
4373 { PIN_A_NUMBER('T', 30), 24, 2 },
4374 { RCAR_GP_PIN(3, 0), 20, 3 },
4375 { RCAR_GP_PIN(3, 1), 16, 3 },
4376 { RCAR_GP_PIN(3, 2), 12, 3 },
4377 { RCAR_GP_PIN(3, 3), 8, 3 },
4378 { RCAR_GP_PIN(3, 4), 4, 3 },
4379 { RCAR_GP_PIN(3, 5), 0, 3 },
4380 } },
4381 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4382 { RCAR_GP_PIN(3, 6), 28, 3 },
4383 { RCAR_GP_PIN(3, 7), 24, 3 },
4384 { RCAR_GP_PIN(3, 8), 20, 3 },
4385 { RCAR_GP_PIN(3, 9), 16, 3 },
4386 { RCAR_GP_PIN(3, 10), 12, 3 },
4387 { RCAR_GP_PIN(3, 11), 8, 3 },
4388 { RCAR_GP_PIN(4, 0), 4, 3 },
4389 { RCAR_GP_PIN(4, 1), 0, 3 },
4390 } },
4391 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4392 { RCAR_GP_PIN(4, 2), 28, 3 },
4393 { RCAR_GP_PIN(4, 3), 24, 3 },
4394 { RCAR_GP_PIN(4, 4), 20, 3 },
4395 { RCAR_GP_PIN(4, 5), 16, 3 },
4396 { RCAR_GP_PIN(4, 6), 12, 3 },
4397 { RCAR_GP_PIN(4, 7), 8, 3 },
4398 { RCAR_GP_PIN(4, 8), 4, 3 },
4399 { RCAR_GP_PIN(4, 9), 0, 3 },
4400 } },
4401 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4402 { RCAR_GP_PIN(4, 10), 28, 3 },
4403 { RCAR_GP_PIN(4, 11), 24, 3 },
4404 { RCAR_GP_PIN(4, 12), 20, 3 },
4405 { RCAR_GP_PIN(4, 13), 16, 3 },
4406 { RCAR_GP_PIN(4, 14), 12, 3 },
4407 { RCAR_GP_PIN(4, 15), 8, 3 },
4408 { RCAR_GP_PIN(4, 16), 4, 3 },
4409 { RCAR_GP_PIN(4, 17), 0, 3 },
4410 } },
4411 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4412 { RCAR_GP_PIN(3, 12), 28, 3 },
4413 { RCAR_GP_PIN(3, 13), 24, 3 },
4414 { RCAR_GP_PIN(3, 14), 20, 3 },
4415 { RCAR_GP_PIN(3, 15), 16, 3 },
4416 { RCAR_GP_PIN(5, 0), 12, 3 },
4417 { RCAR_GP_PIN(5, 1), 8, 3 },
4418 { RCAR_GP_PIN(5, 2), 4, 3 },
4419 { RCAR_GP_PIN(5, 3), 0, 3 },
4420 } },
4421 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4422 { RCAR_GP_PIN(5, 4), 28, 3 },
4423 { RCAR_GP_PIN(5, 5), 24, 3 },
4424 { RCAR_GP_PIN(5, 6), 20, 3 },
4425 { RCAR_GP_PIN(5, 7), 16, 3 },
4426 { RCAR_GP_PIN(5, 8), 12, 3 },
4427 { RCAR_GP_PIN(5, 9), 8, 3 },
4428 { RCAR_GP_PIN(5, 10), 4, 3 },
4429 { RCAR_GP_PIN(5, 11), 0, 3 },
4430 } },
4431 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4432 { RCAR_GP_PIN(5, 12), 28, 3 },
4433 { RCAR_GP_PIN(5, 13), 24, 3 },
4434 { RCAR_GP_PIN(5, 14), 20, 3 },
4435 { RCAR_GP_PIN(5, 15), 16, 3 },
4436 { RCAR_GP_PIN(5, 16), 12, 3 },
4437 { RCAR_GP_PIN(5, 17), 8, 3 },
4438 { RCAR_GP_PIN(5, 18), 4, 3 },
4439 { RCAR_GP_PIN(5, 19), 0, 3 },
4440 } },
4441 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4442 { RCAR_GP_PIN(5, 20), 28, 3 },
4443 { RCAR_GP_PIN(5, 21), 24, 3 },
4444 { RCAR_GP_PIN(5, 22), 20, 3 },
4445 { RCAR_GP_PIN(5, 23), 16, 3 },
4446 { RCAR_GP_PIN(5, 24), 12, 3 },
4447 { RCAR_GP_PIN(5, 25), 8, 3 },
4448 { PIN_NUMBER('H', 37), 4, 3 },
4449 { RCAR_GP_PIN(6, 0), 0, 3 },
4450 } },
4451 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4452 { RCAR_GP_PIN(6, 1), 28, 3 },
4453 { RCAR_GP_PIN(6, 2), 24, 3 },
4454 { RCAR_GP_PIN(6, 3), 20, 3 },
4455 { RCAR_GP_PIN(6, 4), 16, 3 },
4456 { RCAR_GP_PIN(6, 5), 12, 3 },
4457 { RCAR_GP_PIN(6, 6), 8, 3 },
4458 { RCAR_GP_PIN(6, 7), 4, 3 },
4459 { RCAR_GP_PIN(6, 8), 0, 3 },
4460 } },
4461 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4462 { RCAR_GP_PIN(6, 9), 28, 3 },
4463 { RCAR_GP_PIN(6, 10), 24, 3 },
4464 { RCAR_GP_PIN(6, 11), 20, 3 },
4465 { RCAR_GP_PIN(6, 12), 16, 3 },
4466 { RCAR_GP_PIN(6, 13), 12, 3 },
4467 { RCAR_GP_PIN(6, 14), 8, 3 },
4468 { RCAR_GP_PIN(6, 15), 4, 3 },
4469 { RCAR_GP_PIN(6, 16), 0, 3 },
4470 } },
4471 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4472 { RCAR_GP_PIN(6, 17), 28, 3 },
4473 { RCAR_GP_PIN(6, 18), 24, 3 },
4474 { RCAR_GP_PIN(6, 19), 20, 3 },
4475 { RCAR_GP_PIN(6, 20), 16, 3 },
4476 { RCAR_GP_PIN(6, 21), 12, 3 },
4477 { RCAR_GP_PIN(6, 22), 8, 3 },
4478 { RCAR_GP_PIN(6, 23), 4, 3 },
4479 { RCAR_GP_PIN(6, 24), 0, 3 },
4480 } },
4481 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4482 { RCAR_GP_PIN(6, 25), 28, 3 },
4483 { RCAR_GP_PIN(6, 26), 24, 3 },
4484 { RCAR_GP_PIN(6, 27), 20, 3 },
4485 { RCAR_GP_PIN(6, 28), 16, 3 },
4486 { RCAR_GP_PIN(6, 29), 12, 3 },
4487 { RCAR_GP_PIN(6, 30), 8, 3 },
4488 { RCAR_GP_PIN(6, 31), 4, 3 },
4489 } },
4490 { },
4491};
4492
4493enum ioctrl_regs {
4494 POCCTRL,
4495};
4496
4497static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
4498 [POCCTRL] = { 0xe6060380, },
4499 { },
4500};
4501
4502static int r8a77965_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4503{
4504 int bit = -EINVAL;
4505
4506 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
4507
4508 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4509 bit = pin & 0x1f;
4510
4511 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4512 bit = (pin & 0x1f) + 12;
4513
4514 return bit;
4515}
4516
4517static const struct pinmux_bias_reg pinmux_bias_regs[] = {
4518 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
4519 [ 0] = PIN_NUMBER('W', 3),
4520 [ 1] = PIN_A_NUMBER('C', 5),
4521 [ 2] = PIN_A_NUMBER('B', 4),
4522 [ 3] = PIN_NUMBER('Y', 6),
4523 [ 4] = PIN_A_NUMBER('B', 6),
4524 [ 5] = PIN_NUMBER('Y', 3),
4525 [ 6] = PIN_NUMBER('V', 3),
4526 [ 7] = PIN_A_NUMBER('C', 7),
4527 [ 8] = PIN_A_NUMBER('E', 5),
4528 [ 9] = PIN_A_NUMBER('E', 4),
4529 [10] = PIN_A_NUMBER('C', 3),
4530 [11] = PIN_NUMBER('V', 5),
4531 [12] = PIN_NUMBER('Y', 7),
4532 [13] = PIN_NUMBER('V', 6),
4533 [14] = PIN_NUMBER('V', 7),
4534 [15] = PIN_NUMBER('A', 16),
4535 [16] = PIN_NUMBER('B', 19),
4536 [17] = PIN_NUMBER('A', 13),
4537 [18] = PIN_NUMBER('B', 13),
4538 [19] = PIN_NUMBER('A', 14),
4539 [20] = PIN_NUMBER('B', 14),
4540 [21] = PIN_NUMBER('A', 8),
4541 [22] = PIN_NUMBER('A', 19),
4542 [23] = PIN_NUMBER('A', 18),
4543 [24] = PIN_NUMBER('B', 18),
4544 [25] = PIN_NUMBER('A', 17),
4545 [26] = PIN_NUMBER('B', 17),
4546 [27] = PIN_NUMBER('A', 12),
4547 [28] = PIN_NUMBER('A', 9),
4548 [29] = RCAR_GP_PIN(2, 9),
4549 [30] = RCAR_GP_PIN(2, 10),
4550 [31] = RCAR_GP_PIN(2, 11),
4551 } },
4552 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
4553 [ 0] = RCAR_GP_PIN(2, 12),
4554 [ 1] = RCAR_GP_PIN(2, 13),
4555 [ 2] = RCAR_GP_PIN(2, 14),
4556 [ 3] = RCAR_GP_PIN(2, 0),
4557 [ 4] = RCAR_GP_PIN(2, 1),
4558 [ 5] = RCAR_GP_PIN(2, 2),
4559 [ 6] = RCAR_GP_PIN(2, 3),
4560 [ 7] = RCAR_GP_PIN(2, 4),
4561 [ 8] = RCAR_GP_PIN(2, 5),
4562 [ 9] = RCAR_GP_PIN(2, 6),
4563 [10] = RCAR_GP_PIN(2, 7),
4564 [11] = RCAR_GP_PIN(2, 8),
4565 [12] = RCAR_GP_PIN(1, 0),
4566 [13] = RCAR_GP_PIN(1, 1),
4567 [14] = RCAR_GP_PIN(1, 2),
4568 [15] = RCAR_GP_PIN(1, 3),
4569 [16] = RCAR_GP_PIN(1, 4),
4570 [17] = RCAR_GP_PIN(1, 5),
4571 [18] = RCAR_GP_PIN(1, 6),
4572 [19] = RCAR_GP_PIN(1, 7),
4573 [20] = RCAR_GP_PIN(1, 8),
4574 [21] = RCAR_GP_PIN(1, 9),
4575 [22] = RCAR_GP_PIN(1, 10),
4576 [23] = RCAR_GP_PIN(1, 11),
4577 [24] = RCAR_GP_PIN(1, 12),
4578 [25] = RCAR_GP_PIN(1, 13),
4579 [26] = RCAR_GP_PIN(1, 14),
4580 [27] = RCAR_GP_PIN(1, 15),
4581 [28] = RCAR_GP_PIN(1, 16),
4582 [29] = RCAR_GP_PIN(1, 17),
4583 [30] = RCAR_GP_PIN(1, 18),
4584 [31] = RCAR_GP_PIN(1, 19),
4585 } },
4586 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
4587 [ 0] = RCAR_GP_PIN(1, 28),
4588 [ 1] = RCAR_GP_PIN(1, 20),
4589 [ 2] = RCAR_GP_PIN(1, 21),
4590 [ 3] = RCAR_GP_PIN(1, 22),
4591 [ 4] = RCAR_GP_PIN(1, 23),
4592 [ 5] = RCAR_GP_PIN(1, 24),
4593 [ 6] = RCAR_GP_PIN(1, 25),
4594 [ 7] = RCAR_GP_PIN(1, 26),
4595 [ 8] = RCAR_GP_PIN(1, 27),
4596 [ 9] = PIN_NUMBER('C', 1),
4597 [10] = RCAR_GP_PIN(0, 0),
4598 [11] = RCAR_GP_PIN(0, 1),
4599 [12] = RCAR_GP_PIN(0, 2),
4600 [13] = RCAR_GP_PIN(0, 3),
4601 [14] = RCAR_GP_PIN(0, 4),
4602 [15] = RCAR_GP_PIN(0, 5),
4603 [16] = RCAR_GP_PIN(0, 6),
4604 [17] = RCAR_GP_PIN(0, 7),
4605 [18] = RCAR_GP_PIN(0, 8),
4606 [19] = RCAR_GP_PIN(0, 9),
4607 [20] = RCAR_GP_PIN(0, 10),
4608 [21] = RCAR_GP_PIN(0, 11),
4609 [22] = RCAR_GP_PIN(0, 12),
4610 [23] = RCAR_GP_PIN(0, 13),
4611 [24] = RCAR_GP_PIN(0, 14),
4612 [25] = RCAR_GP_PIN(0, 15),
4613 [26] = RCAR_GP_PIN(7, 0),
4614 [27] = RCAR_GP_PIN(7, 1),
4615 [28] = RCAR_GP_PIN(7, 2),
4616 [29] = RCAR_GP_PIN(7, 3),
4617 [30] = PIN_A_NUMBER('P', 7),
4618 [31] = PIN_A_NUMBER('P', 8),
4619 } },
4620 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
4621 [ 0] = PIN_A_NUMBER('R', 8),
4622 [ 1] = PIN_NONE,
4623 [ 2] = PIN_A_NUMBER('D', 38),
4624 [ 3] = PIN_A_NUMBER('D', 39),
4625 [ 4] = PIN_A_NUMBER('R', 26),
4626 [ 5] = PIN_A_NUMBER('T', 27),
4627 [ 6] = PIN_A_NUMBER('R', 30),
4628 [ 7] = PIN_A_NUMBER('R', 29),
4629 [ 8] = PIN_NONE,
4630 [ 9] = PIN_A_NUMBER('T', 30),
4631 [10] = RCAR_GP_PIN(3, 0),
4632 [11] = RCAR_GP_PIN(3, 1),
4633 [12] = RCAR_GP_PIN(3, 2),
4634 [13] = RCAR_GP_PIN(3, 3),
4635 [14] = RCAR_GP_PIN(3, 4),
4636 [15] = RCAR_GP_PIN(3, 5),
4637 [16] = RCAR_GP_PIN(3, 6),
4638 [17] = RCAR_GP_PIN(3, 7),
4639 [18] = RCAR_GP_PIN(3, 8),
4640 [19] = RCAR_GP_PIN(3, 9),
4641 [20] = RCAR_GP_PIN(3, 10),
4642 [21] = RCAR_GP_PIN(3, 11),
4643 [22] = RCAR_GP_PIN(4, 0),
4644 [23] = RCAR_GP_PIN(4, 1),
4645 [24] = RCAR_GP_PIN(4, 2),
4646 [25] = RCAR_GP_PIN(4, 3),
4647 [26] = RCAR_GP_PIN(4, 4),
4648 [27] = RCAR_GP_PIN(4, 5),
4649 [28] = RCAR_GP_PIN(4, 6),
4650 [29] = RCAR_GP_PIN(4, 7),
4651 [30] = RCAR_GP_PIN(4, 8),
4652 [31] = RCAR_GP_PIN(4, 9),
4653 } },
4654 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
4655 [ 0] = RCAR_GP_PIN(4, 10),
4656 [ 1] = RCAR_GP_PIN(4, 11),
4657 [ 2] = RCAR_GP_PIN(4, 12),
4658 [ 3] = RCAR_GP_PIN(4, 13),
4659 [ 4] = RCAR_GP_PIN(4, 14),
4660 [ 5] = RCAR_GP_PIN(4, 15),
4661 [ 6] = RCAR_GP_PIN(4, 16),
4662 [ 7] = RCAR_GP_PIN(4, 17),
4663 [ 8] = RCAR_GP_PIN(3, 12),
4664 [ 9] = RCAR_GP_PIN(3, 13),
4665 [10] = RCAR_GP_PIN(3, 14),
4666 [11] = RCAR_GP_PIN(3, 15),
4667 [12] = RCAR_GP_PIN(5, 0),
4668 [13] = RCAR_GP_PIN(5, 1),
4669 [14] = RCAR_GP_PIN(5, 2),
4670 [15] = RCAR_GP_PIN(5, 3),
4671 [16] = RCAR_GP_PIN(5, 4),
4672 [17] = RCAR_GP_PIN(5, 5),
4673 [18] = RCAR_GP_PIN(5, 6),
4674 [19] = RCAR_GP_PIN(5, 7),
4675 [20] = RCAR_GP_PIN(5, 8),
4676 [21] = RCAR_GP_PIN(5, 9),
4677 [22] = RCAR_GP_PIN(5, 10),
4678 [23] = RCAR_GP_PIN(5, 11),
4679 [24] = RCAR_GP_PIN(5, 12),
4680 [25] = RCAR_GP_PIN(5, 13),
4681 [26] = RCAR_GP_PIN(5, 14),
4682 [27] = RCAR_GP_PIN(5, 15),
4683 [28] = RCAR_GP_PIN(5, 16),
4684 [29] = RCAR_GP_PIN(5, 17),
4685 [30] = RCAR_GP_PIN(5, 18),
4686 [31] = RCAR_GP_PIN(5, 19),
4687 } },
4688 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
4689 [ 0] = RCAR_GP_PIN(5, 20),
4690 [ 1] = RCAR_GP_PIN(5, 21),
4691 [ 2] = RCAR_GP_PIN(5, 22),
4692 [ 3] = RCAR_GP_PIN(5, 23),
4693 [ 4] = RCAR_GP_PIN(5, 24),
4694 [ 5] = RCAR_GP_PIN(5, 25),
4695 [ 6] = PIN_NUMBER('H', 37),
4696 [ 7] = RCAR_GP_PIN(6, 0),
4697 [ 8] = RCAR_GP_PIN(6, 1),
4698 [ 9] = RCAR_GP_PIN(6, 2),
4699 [10] = RCAR_GP_PIN(6, 3),
4700 [11] = RCAR_GP_PIN(6, 4),
4701 [12] = RCAR_GP_PIN(6, 5),
4702 [13] = RCAR_GP_PIN(6, 6),
4703 [14] = RCAR_GP_PIN(6, 7),
4704 [15] = RCAR_GP_PIN(6, 8),
4705 [16] = RCAR_GP_PIN(6, 9),
4706 [17] = RCAR_GP_PIN(6, 10),
4707 [18] = RCAR_GP_PIN(6, 11),
4708 [19] = RCAR_GP_PIN(6, 12),
4709 [20] = RCAR_GP_PIN(6, 13),
4710 [21] = RCAR_GP_PIN(6, 14),
4711 [22] = RCAR_GP_PIN(6, 15),
4712 [23] = RCAR_GP_PIN(6, 16),
4713 [24] = RCAR_GP_PIN(6, 17),
4714 [25] = RCAR_GP_PIN(6, 18),
4715 [26] = RCAR_GP_PIN(6, 19),
4716 [27] = RCAR_GP_PIN(6, 20),
4717 [28] = RCAR_GP_PIN(6, 21),
4718 [29] = RCAR_GP_PIN(6, 22),
4719 [30] = RCAR_GP_PIN(6, 23),
4720 [31] = RCAR_GP_PIN(6, 24),
4721 } },
4722 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
4723 [ 0] = RCAR_GP_PIN(6, 25),
4724 [ 1] = RCAR_GP_PIN(6, 26),
4725 [ 2] = RCAR_GP_PIN(6, 27),
4726 [ 3] = RCAR_GP_PIN(6, 28),
4727 [ 4] = RCAR_GP_PIN(6, 29),
4728 [ 5] = RCAR_GP_PIN(6, 30),
4729 [ 6] = RCAR_GP_PIN(6, 31),
4730 [ 7] = PIN_NONE,
4731 [ 8] = PIN_NONE,
4732 [ 9] = PIN_NONE,
4733 [10] = PIN_NONE,
4734 [11] = PIN_NONE,
4735 [12] = PIN_NONE,
4736 [13] = PIN_NONE,
4737 [14] = PIN_NONE,
4738 [15] = PIN_NONE,
4739 [16] = PIN_NONE,
4740 [17] = PIN_NONE,
4741 [18] = PIN_NONE,
4742 [19] = PIN_NONE,
4743 [20] = PIN_NONE,
4744 [21] = PIN_NONE,
4745 [22] = PIN_NONE,
4746 [23] = PIN_NONE,
4747 [24] = PIN_NONE,
4748 [25] = PIN_NONE,
4749 [26] = PIN_NONE,
4750 [27] = PIN_NONE,
4751 [28] = PIN_NONE,
4752 [29] = PIN_NONE,
4753 [30] = PIN_NONE,
4754 [31] = PIN_NONE,
4755 } },
4756 { },
4757};
4758
4759static unsigned int r8a77965_pinmux_get_bias(struct sh_pfc *pfc,
4760 unsigned int pin)
4761{
4762 const struct pinmux_bias_reg *reg;
4763 unsigned int bit;
4764
4765 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4766 if (!reg)
4767 return PIN_CONFIG_BIAS_DISABLE;
4768
4769 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
4770 return PIN_CONFIG_BIAS_DISABLE;
4771 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
4772 return PIN_CONFIG_BIAS_PULL_UP;
4773 else
4774 return PIN_CONFIG_BIAS_PULL_DOWN;
4775}
4776
4777static void r8a77965_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
4778 unsigned int bias)
4779{
4780 const struct pinmux_bias_reg *reg;
4781 u32 enable, updown;
4782 unsigned int bit;
4783
4784 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
4785 if (!reg)
4786 return;
4787
4788 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
4789 if (bias != PIN_CONFIG_BIAS_DISABLE)
4790 enable |= BIT(bit);
4791
4792 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
4793 if (bias == PIN_CONFIG_BIAS_PULL_UP)
4794 updown |= BIT(bit);
4795
4796 sh_pfc_write(pfc, reg->pud, updown);
4797 sh_pfc_write(pfc, reg->puen, enable);
4798}
4799
4800static const struct sh_pfc_soc_operations r8a77965_pinmux_ops = {
4801 .pin_to_pocctrl = r8a77965_pin_to_pocctrl,
4802 .get_bias = r8a77965_pinmux_get_bias,
4803 .set_bias = r8a77965_pinmux_set_bias,
4804};
4805
4806const struct sh_pfc_soc_info r8a77965_pinmux_info = {
4807 .name = "r8a77965_pfc",
4808 .ops = &r8a77965_pinmux_ops,
4809 .unlock_reg = 0xe6060000,
4810
4811 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4812
4813 .pins = pinmux_pins,
4814 .nr_pins = ARRAY_SIZE(pinmux_pins),
4815 .groups = pinmux_groups,
4816 .nr_groups = ARRAY_SIZE(pinmux_groups),
4817 .functions = pinmux_functions,
4818 .nr_functions = ARRAY_SIZE(pinmux_functions),
4819
4820 .cfg_regs = pinmux_config_regs,
4821 .drive_regs = pinmux_drive_regs,
4822 .bias_regs = pinmux_bias_regs,
4823 .ioctrl_regs = pinmux_ioctrl_regs,
4824
4825 .pinmux_data = pinmux_data,
4826 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4827};
4828
