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9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/io.h>
12#include <linux/irq.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/of_irq.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/pinctrl/machine.h>
21#include <linux/pinctrl/pinconf.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <linux/reset.h>
28#include <linux/slab.h>
29
30#include "../core.h"
31#include "../pinconf.h"
32#include "../pinctrl-utils.h"
33#include "pinctrl-stm32.h"
34
35#define STM32_GPIO_MODER 0x00
36#define STM32_GPIO_TYPER 0x04
37#define STM32_GPIO_SPEEDR 0x08
38#define STM32_GPIO_PUPDR 0x0c
39#define STM32_GPIO_IDR 0x10
40#define STM32_GPIO_ODR 0x14
41#define STM32_GPIO_BSRR 0x18
42#define STM32_GPIO_LCKR 0x1c
43#define STM32_GPIO_AFRL 0x20
44#define STM32_GPIO_AFRH 0x24
45
46#define STM32_GPIO_PINS_PER_BANK 16
47#define STM32_GPIO_IRQ_LINE 16
48
49#define gpio_range_to_bank(chip) \
50 container_of(chip, struct stm32_gpio_bank, range)
51
52static const char * const stm32_gpio_functions[] = {
53 "gpio", "af0", "af1",
54 "af2", "af3", "af4",
55 "af5", "af6", "af7",
56 "af8", "af9", "af10",
57 "af11", "af12", "af13",
58 "af14", "af15", "analog",
59};
60
61struct stm32_pinctrl_group {
62 const char *name;
63 unsigned long config;
64 unsigned pin;
65};
66
67struct stm32_gpio_bank {
68 void __iomem *base;
69 struct clk *clk;
70 spinlock_t lock;
71 struct gpio_chip gpio_chip;
72 struct pinctrl_gpio_range range;
73 struct fwnode_handle *fwnode;
74 struct irq_domain *domain;
75 u32 bank_nr;
76};
77
78struct stm32_pinctrl {
79 struct device *dev;
80 struct pinctrl_dev *pctl_dev;
81 struct pinctrl_desc pctl_desc;
82 struct stm32_pinctrl_group *groups;
83 unsigned ngroups;
84 const char **grp_names;
85 struct stm32_gpio_bank *banks;
86 unsigned nbanks;
87 const struct stm32_pinctrl_match_data *match_data;
88 struct irq_domain *domain;
89 struct regmap *regmap;
90 struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
91};
92
93static inline int stm32_gpio_pin(int gpio)
94{
95 return gpio % STM32_GPIO_PINS_PER_BANK;
96}
97
98static inline u32 stm32_gpio_get_mode(u32 function)
99{
100 switch (function) {
101 case STM32_PIN_GPIO:
102 return 0;
103 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
104 return 2;
105 case STM32_PIN_ANALOG:
106 return 3;
107 }
108
109 return 0;
110}
111
112static inline u32 stm32_gpio_get_alt(u32 function)
113{
114 switch (function) {
115 case STM32_PIN_GPIO:
116 return 0;
117 case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
118 return function - 1;
119 case STM32_PIN_ANALOG:
120 return 0;
121 }
122
123 return 0;
124}
125
126
127
128static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
129 unsigned offset, int value)
130{
131 if (!value)
132 offset += STM32_GPIO_PINS_PER_BANK;
133
134 clk_enable(bank->clk);
135
136 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
137
138 clk_disable(bank->clk);
139}
140
141static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
142{
143 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
144 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
145 struct pinctrl_gpio_range *range;
146 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
147
148 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
149 if (!range) {
150 dev_err(pctl->dev, "pin %d not in range.\n", pin);
151 return -EINVAL;
152 }
153
154 return pinctrl_gpio_request(chip->base + offset);
155}
156
157static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
158{
159 pinctrl_gpio_free(chip->base + offset);
160}
161
162static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
163{
164 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
165 int ret;
166
167 clk_enable(bank->clk);
168
169 ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
170
171 clk_disable(bank->clk);
172
173 return ret;
174}
175
176static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
177{
178 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
179
180 __stm32_gpio_set(bank, offset, value);
181}
182
183static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
184{
185 return pinctrl_gpio_direction_input(chip->base + offset);
186}
187
188static int stm32_gpio_direction_output(struct gpio_chip *chip,
189 unsigned offset, int value)
190{
191 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
192
193 __stm32_gpio_set(bank, offset, value);
194 pinctrl_gpio_direction_output(chip->base + offset);
195
196 return 0;
197}
198
199
200static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
201{
202 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
203 struct irq_fwspec fwspec;
204
205 fwspec.fwnode = bank->fwnode;
206 fwspec.param_count = 2;
207 fwspec.param[0] = offset;
208 fwspec.param[1] = IRQ_TYPE_NONE;
209
210 return irq_create_fwspec_mapping(&fwspec);
211}
212
213static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
214{
215 struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
216 int pin = stm32_gpio_pin(offset);
217 int ret;
218 u32 mode, alt;
219
220 stm32_pmx_get_mode(bank, pin, &mode, &alt);
221 if ((alt == 0) && (mode == 0))
222 ret = 1;
223 else if ((alt == 0) && (mode == 1))
224 ret = 0;
225 else
226 ret = -EINVAL;
227
228 return ret;
229}
230
231static const struct gpio_chip stm32_gpio_template = {
232 .request = stm32_gpio_request,
233 .free = stm32_gpio_free,
234 .get = stm32_gpio_get,
235 .set = stm32_gpio_set,
236 .direction_input = stm32_gpio_direction_input,
237 .direction_output = stm32_gpio_direction_output,
238 .to_irq = stm32_gpio_to_irq,
239 .get_direction = stm32_gpio_get_direction,
240};
241
242static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
243{
244 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
245 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
246 int ret;
247
248 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
249 if (ret)
250 return ret;
251
252 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
253 if (ret) {
254 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
255 irq_data->hwirq);
256 return ret;
257 }
258
259 return 0;
260}
261
262static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
263{
264 struct stm32_gpio_bank *bank = irq_data->domain->host_data;
265
266 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
267}
268
269static struct irq_chip stm32_gpio_irq_chip = {
270 .name = "stm32gpio",
271 .irq_eoi = irq_chip_eoi_parent,
272 .irq_ack = irq_chip_ack_parent,
273 .irq_mask = irq_chip_mask_parent,
274 .irq_unmask = irq_chip_unmask_parent,
275 .irq_set_type = irq_chip_set_type_parent,
276 .irq_set_wake = irq_chip_set_wake_parent,
277 .irq_request_resources = stm32_gpio_irq_request_resources,
278 .irq_release_resources = stm32_gpio_irq_release_resources,
279};
280
281static int stm32_gpio_domain_translate(struct irq_domain *d,
282 struct irq_fwspec *fwspec,
283 unsigned long *hwirq,
284 unsigned int *type)
285{
286 if ((fwspec->param_count != 2) ||
287 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
288 return -EINVAL;
289
290 *hwirq = fwspec->param[0];
291 *type = fwspec->param[1];
292 return 0;
293}
294
295static int stm32_gpio_domain_activate(struct irq_domain *d,
296 struct irq_data *irq_data, bool reserve)
297{
298 struct stm32_gpio_bank *bank = d->host_data;
299 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
300
301 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr);
302 return 0;
303}
304
305static int stm32_gpio_domain_alloc(struct irq_domain *d,
306 unsigned int virq,
307 unsigned int nr_irqs, void *data)
308{
309 struct stm32_gpio_bank *bank = d->host_data;
310 struct irq_fwspec *fwspec = data;
311 struct irq_fwspec parent_fwspec;
312 irq_hw_number_t hwirq;
313
314 hwirq = fwspec->param[0];
315 parent_fwspec.fwnode = d->parent->fwnode;
316 parent_fwspec.param_count = 2;
317 parent_fwspec.param[0] = fwspec->param[0];
318 parent_fwspec.param[1] = fwspec->param[1];
319
320 irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
321 bank);
322
323 return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
324}
325
326static const struct irq_domain_ops stm32_gpio_domain_ops = {
327 .translate = stm32_gpio_domain_translate,
328 .alloc = stm32_gpio_domain_alloc,
329 .free = irq_domain_free_irqs_common,
330 .activate = stm32_gpio_domain_activate,
331};
332
333
334static struct stm32_pinctrl_group *
335stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
336{
337 int i;
338
339 for (i = 0; i < pctl->ngroups; i++) {
340 struct stm32_pinctrl_group *grp = pctl->groups + i;
341
342 if (grp->pin == pin)
343 return grp;
344 }
345
346 return NULL;
347}
348
349static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
350 u32 pin_num, u32 fnum)
351{
352 int i;
353
354 for (i = 0; i < pctl->match_data->npins; i++) {
355 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
356 const struct stm32_desc_function *func = pin->functions;
357
358 if (pin->pin.number != pin_num)
359 continue;
360
361 while (func && func->name) {
362 if (func->num == fnum)
363 return true;
364 func++;
365 }
366
367 break;
368 }
369
370 return false;
371}
372
373static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
374 u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
375 struct pinctrl_map **map, unsigned *reserved_maps,
376 unsigned *num_maps)
377{
378 if (*num_maps == *reserved_maps)
379 return -ENOSPC;
380
381 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
382 (*map)[*num_maps].data.mux.group = grp->name;
383
384 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) {
385 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
386 fnum, pin);
387 return -EINVAL;
388 }
389
390 (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
391 (*num_maps)++;
392
393 return 0;
394}
395
396static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
397 struct device_node *node,
398 struct pinctrl_map **map,
399 unsigned *reserved_maps,
400 unsigned *num_maps)
401{
402 struct stm32_pinctrl *pctl;
403 struct stm32_pinctrl_group *grp;
404 struct property *pins;
405 u32 pinfunc, pin, func;
406 unsigned long *configs;
407 unsigned int num_configs;
408 bool has_config = 0;
409 unsigned reserve = 0;
410 int num_pins, num_funcs, maps_per_pin, i, err;
411
412 pctl = pinctrl_dev_get_drvdata(pctldev);
413
414 pins = of_find_property(node, "pinmux", NULL);
415 if (!pins) {
416 dev_err(pctl->dev, "missing pins property in node %s .\n",
417 node->name);
418 return -EINVAL;
419 }
420
421 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
422 &num_configs);
423 if (err)
424 return err;
425
426 if (num_configs)
427 has_config = 1;
428
429 num_pins = pins->length / sizeof(u32);
430 num_funcs = num_pins;
431 maps_per_pin = 0;
432 if (num_funcs)
433 maps_per_pin++;
434 if (has_config && num_pins >= 1)
435 maps_per_pin++;
436
437 if (!num_pins || !maps_per_pin)
438 return -EINVAL;
439
440 reserve = num_pins * maps_per_pin;
441
442 err = pinctrl_utils_reserve_map(pctldev, map,
443 reserved_maps, num_maps, reserve);
444 if (err)
445 return err;
446
447 for (i = 0; i < num_pins; i++) {
448 err = of_property_read_u32_index(node, "pinmux",
449 i, &pinfunc);
450 if (err)
451 return err;
452
453 pin = STM32_GET_PIN_NO(pinfunc);
454 func = STM32_GET_PIN_FUNC(pinfunc);
455
456 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
457 dev_err(pctl->dev, "invalid function.\n");
458 return -EINVAL;
459 }
460
461 grp = stm32_pctrl_find_group_by_pin(pctl, pin);
462 if (!grp) {
463 dev_err(pctl->dev, "unable to match pin %d to group\n",
464 pin);
465 return -EINVAL;
466 }
467
468 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
469 reserved_maps, num_maps);
470 if (err)
471 return err;
472
473 if (has_config) {
474 err = pinctrl_utils_add_map_configs(pctldev, map,
475 reserved_maps, num_maps, grp->name,
476 configs, num_configs,
477 PIN_MAP_TYPE_CONFIGS_GROUP);
478 if (err)
479 return err;
480 }
481 }
482
483 return 0;
484}
485
486static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np_config,
488 struct pinctrl_map **map, unsigned *num_maps)
489{
490 struct device_node *np;
491 unsigned reserved_maps;
492 int ret;
493
494 *map = NULL;
495 *num_maps = 0;
496 reserved_maps = 0;
497
498 for_each_child_of_node(np_config, np) {
499 ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
500 &reserved_maps, num_maps);
501 if (ret < 0) {
502 pinctrl_utils_free_map(pctldev, *map, *num_maps);
503 return ret;
504 }
505 }
506
507 return 0;
508}
509
510static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
511{
512 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
513
514 return pctl->ngroups;
515}
516
517static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
518 unsigned group)
519{
520 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
521
522 return pctl->groups[group].name;
523}
524
525static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
526 unsigned group,
527 const unsigned **pins,
528 unsigned *num_pins)
529{
530 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
531
532 *pins = (unsigned *)&pctl->groups[group].pin;
533 *num_pins = 1;
534
535 return 0;
536}
537
538static const struct pinctrl_ops stm32_pctrl_ops = {
539 .dt_node_to_map = stm32_pctrl_dt_node_to_map,
540 .dt_free_map = pinctrl_utils_free_map,
541 .get_groups_count = stm32_pctrl_get_groups_count,
542 .get_group_name = stm32_pctrl_get_group_name,
543 .get_group_pins = stm32_pctrl_get_group_pins,
544};
545
546
547
548
549static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
550{
551 return ARRAY_SIZE(stm32_gpio_functions);
552}
553
554static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
555 unsigned selector)
556{
557 return stm32_gpio_functions[selector];
558}
559
560static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
561 unsigned function,
562 const char * const **groups,
563 unsigned * const num_groups)
564{
565 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
566
567 *groups = pctl->grp_names;
568 *num_groups = pctl->ngroups;
569
570 return 0;
571}
572
573static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
574 int pin, u32 mode, u32 alt)
575{
576 u32 val;
577 int alt_shift = (pin % 8) * 4;
578 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
579 unsigned long flags;
580
581 clk_enable(bank->clk);
582 spin_lock_irqsave(&bank->lock, flags);
583
584 val = readl_relaxed(bank->base + alt_offset);
585 val &= ~GENMASK(alt_shift + 3, alt_shift);
586 val |= (alt << alt_shift);
587 writel_relaxed(val, bank->base + alt_offset);
588
589 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
590 val &= ~GENMASK(pin * 2 + 1, pin * 2);
591 val |= mode << (pin * 2);
592 writel_relaxed(val, bank->base + STM32_GPIO_MODER);
593
594 spin_unlock_irqrestore(&bank->lock, flags);
595 clk_disable(bank->clk);
596}
597
598void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
599 u32 *alt)
600{
601 u32 val;
602 int alt_shift = (pin % 8) * 4;
603 int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
604 unsigned long flags;
605
606 clk_enable(bank->clk);
607 spin_lock_irqsave(&bank->lock, flags);
608
609 val = readl_relaxed(bank->base + alt_offset);
610 val &= GENMASK(alt_shift + 3, alt_shift);
611 *alt = val >> alt_shift;
612
613 val = readl_relaxed(bank->base + STM32_GPIO_MODER);
614 val &= GENMASK(pin * 2 + 1, pin * 2);
615 *mode = val >> (pin * 2);
616
617 spin_unlock_irqrestore(&bank->lock, flags);
618 clk_disable(bank->clk);
619}
620
621static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
622 unsigned function,
623 unsigned group)
624{
625 bool ret;
626 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
627 struct stm32_pinctrl_group *g = pctl->groups + group;
628 struct pinctrl_gpio_range *range;
629 struct stm32_gpio_bank *bank;
630 u32 mode, alt;
631 int pin;
632
633 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
634 if (!ret) {
635 dev_err(pctl->dev, "invalid function %d on group %d .\n",
636 function, group);
637 return -EINVAL;
638 }
639
640 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
641 bank = gpiochip_get_data(range->gc);
642 pin = stm32_gpio_pin(g->pin);
643
644 mode = stm32_gpio_get_mode(function);
645 alt = stm32_gpio_get_alt(function);
646
647 stm32_pmx_set_mode(bank, pin, mode, alt);
648
649 return 0;
650}
651
652static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
653 struct pinctrl_gpio_range *range, unsigned gpio,
654 bool input)
655{
656 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
657 int pin = stm32_gpio_pin(gpio);
658
659 stm32_pmx_set_mode(bank, pin, !input, 0);
660
661 return 0;
662}
663
664static const struct pinmux_ops stm32_pmx_ops = {
665 .get_functions_count = stm32_pmx_get_funcs_cnt,
666 .get_function_name = stm32_pmx_get_func_name,
667 .get_function_groups = stm32_pmx_get_func_groups,
668 .set_mux = stm32_pmx_set_mux,
669 .gpio_set_direction = stm32_pmx_gpio_set_direction,
670 .strict = true,
671};
672
673
674
675static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
676 unsigned offset, u32 drive)
677{
678 unsigned long flags;
679 u32 val;
680
681 clk_enable(bank->clk);
682 spin_lock_irqsave(&bank->lock, flags);
683
684 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
685 val &= ~BIT(offset);
686 val |= drive << offset;
687 writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
688
689 spin_unlock_irqrestore(&bank->lock, flags);
690 clk_disable(bank->clk);
691}
692
693static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
694 unsigned int offset)
695{
696 unsigned long flags;
697 u32 val;
698
699 clk_enable(bank->clk);
700 spin_lock_irqsave(&bank->lock, flags);
701
702 val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
703 val &= BIT(offset);
704
705 spin_unlock_irqrestore(&bank->lock, flags);
706 clk_disable(bank->clk);
707
708 return (val >> offset);
709}
710
711static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
712 unsigned offset, u32 speed)
713{
714 unsigned long flags;
715 u32 val;
716
717 clk_enable(bank->clk);
718 spin_lock_irqsave(&bank->lock, flags);
719
720 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
721 val &= ~GENMASK(offset * 2 + 1, offset * 2);
722 val |= speed << (offset * 2);
723 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
724
725 spin_unlock_irqrestore(&bank->lock, flags);
726 clk_disable(bank->clk);
727}
728
729static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
730 unsigned int offset)
731{
732 unsigned long flags;
733 u32 val;
734
735 clk_enable(bank->clk);
736 spin_lock_irqsave(&bank->lock, flags);
737
738 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
739 val &= GENMASK(offset * 2 + 1, offset * 2);
740
741 spin_unlock_irqrestore(&bank->lock, flags);
742 clk_disable(bank->clk);
743
744 return (val >> (offset * 2));
745}
746
747static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
748 unsigned offset, u32 bias)
749{
750 unsigned long flags;
751 u32 val;
752
753 clk_enable(bank->clk);
754 spin_lock_irqsave(&bank->lock, flags);
755
756 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
757 val &= ~GENMASK(offset * 2 + 1, offset * 2);
758 val |= bias << (offset * 2);
759 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
760
761 spin_unlock_irqrestore(&bank->lock, flags);
762 clk_disable(bank->clk);
763}
764
765static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
766 unsigned int offset)
767{
768 unsigned long flags;
769 u32 val;
770
771 clk_enable(bank->clk);
772 spin_lock_irqsave(&bank->lock, flags);
773
774 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
775 val &= GENMASK(offset * 2 + 1, offset * 2);
776
777 spin_unlock_irqrestore(&bank->lock, flags);
778 clk_disable(bank->clk);
779
780 return (val >> (offset * 2));
781}
782
783static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
784 unsigned int offset, bool dir)
785{
786 unsigned long flags;
787 u32 val;
788
789 clk_enable(bank->clk);
790 spin_lock_irqsave(&bank->lock, flags);
791
792 if (dir)
793 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
794 BIT(offset));
795 else
796 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
797 BIT(offset));
798
799 spin_unlock_irqrestore(&bank->lock, flags);
800 clk_disable(bank->clk);
801
802 return val;
803}
804
805static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
806 unsigned int pin, enum pin_config_param param,
807 enum pin_config_param arg)
808{
809 struct pinctrl_gpio_range *range;
810 struct stm32_gpio_bank *bank;
811 int offset, ret = 0;
812
813 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
814 bank = gpiochip_get_data(range->gc);
815 offset = stm32_gpio_pin(pin);
816
817 switch (param) {
818 case PIN_CONFIG_DRIVE_PUSH_PULL:
819 stm32_pconf_set_driving(bank, offset, 0);
820 break;
821 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
822 stm32_pconf_set_driving(bank, offset, 1);
823 break;
824 case PIN_CONFIG_SLEW_RATE:
825 stm32_pconf_set_speed(bank, offset, arg);
826 break;
827 case PIN_CONFIG_BIAS_DISABLE:
828 stm32_pconf_set_bias(bank, offset, 0);
829 break;
830 case PIN_CONFIG_BIAS_PULL_UP:
831 stm32_pconf_set_bias(bank, offset, 1);
832 break;
833 case PIN_CONFIG_BIAS_PULL_DOWN:
834 stm32_pconf_set_bias(bank, offset, 2);
835 break;
836 case PIN_CONFIG_OUTPUT:
837 __stm32_gpio_set(bank, offset, arg);
838 ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
839 break;
840 default:
841 ret = -EINVAL;
842 }
843
844 return ret;
845}
846
847static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
848 unsigned group,
849 unsigned long *config)
850{
851 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
852
853 *config = pctl->groups[group].config;
854
855 return 0;
856}
857
858static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
859 unsigned long *configs, unsigned num_configs)
860{
861 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
862 struct stm32_pinctrl_group *g = &pctl->groups[group];
863 int i, ret;
864
865 for (i = 0; i < num_configs; i++) {
866 ret = stm32_pconf_parse_conf(pctldev, g->pin,
867 pinconf_to_config_param(configs[i]),
868 pinconf_to_config_argument(configs[i]));
869 if (ret < 0)
870 return ret;
871
872 g->config = configs[i];
873 }
874
875 return 0;
876}
877
878static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
879 struct seq_file *s,
880 unsigned int pin)
881{
882 struct pinctrl_gpio_range *range;
883 struct stm32_gpio_bank *bank;
884 int offset;
885 u32 mode, alt, drive, speed, bias;
886 static const char * const modes[] = {
887 "input", "output", "alternate", "analog" };
888 static const char * const speeds[] = {
889 "low", "medium", "high", "very high" };
890 static const char * const biasing[] = {
891 "floating", "pull up", "pull down", "" };
892 bool val;
893
894 range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
895 bank = gpiochip_get_data(range->gc);
896 offset = stm32_gpio_pin(pin);
897
898 stm32_pmx_get_mode(bank, offset, &mode, &alt);
899 bias = stm32_pconf_get_bias(bank, offset);
900
901 seq_printf(s, "%s ", modes[mode]);
902
903 switch (mode) {
904
905 case 0:
906 val = stm32_pconf_get(bank, offset, true);
907 seq_printf(s, "- %s - %s",
908 val ? "high" : "low",
909 biasing[bias]);
910 break;
911
912
913 case 1:
914 drive = stm32_pconf_get_driving(bank, offset);
915 speed = stm32_pconf_get_speed(bank, offset);
916 val = stm32_pconf_get(bank, offset, false);
917 seq_printf(s, "- %s - %s - %s - %s %s",
918 val ? "high" : "low",
919 drive ? "open drain" : "push pull",
920 biasing[bias],
921 speeds[speed], "speed");
922 break;
923
924
925 case 2:
926 drive = stm32_pconf_get_driving(bank, offset);
927 speed = stm32_pconf_get_speed(bank, offset);
928 seq_printf(s, "%d - %s - %s - %s %s", alt,
929 drive ? "open drain" : "push pull",
930 biasing[bias],
931 speeds[speed], "speed");
932 break;
933
934
935 case 3:
936 break;
937 }
938}
939
940
941static const struct pinconf_ops stm32_pconf_ops = {
942 .pin_config_group_get = stm32_pconf_group_get,
943 .pin_config_group_set = stm32_pconf_group_set,
944 .pin_config_dbg_show = stm32_pconf_dbg_show,
945};
946
947static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl,
948 struct device_node *np)
949{
950 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
951 struct pinctrl_gpio_range *range = &bank->range;
952 struct of_phandle_args args;
953 struct device *dev = pctl->dev;
954 struct resource res;
955 struct reset_control *rstc;
956 int npins = STM32_GPIO_PINS_PER_BANK;
957 int bank_nr, err;
958
959 rstc = of_reset_control_get_exclusive(np, NULL);
960 if (!IS_ERR(rstc))
961 reset_control_deassert(rstc);
962
963 if (of_address_to_resource(np, 0, &res))
964 return -ENODEV;
965
966 bank->base = devm_ioremap_resource(dev, &res);
967 if (IS_ERR(bank->base))
968 return PTR_ERR(bank->base);
969
970 bank->clk = of_clk_get_by_name(np, NULL);
971 if (IS_ERR(bank->clk)) {
972 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
973 return PTR_ERR(bank->clk);
974 }
975
976 err = clk_prepare(bank->clk);
977 if (err) {
978 dev_err(dev, "failed to prepare clk (%d)\n", err);
979 return err;
980 }
981
982 bank->gpio_chip = stm32_gpio_template;
983
984 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label);
985
986 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) {
987 bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
988 bank->gpio_chip.base = args.args[1];
989 } else {
990 bank_nr = pctl->nbanks;
991 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
992 range->name = bank->gpio_chip.label;
993 range->id = bank_nr;
994 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
995 range->base = range->id * STM32_GPIO_PINS_PER_BANK;
996 range->npins = npins;
997 range->gc = &bank->gpio_chip;
998 pinctrl_add_gpio_range(pctl->pctl_dev,
999 &pctl->banks[bank_nr].range);
1000 }
1001 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1002
1003 bank->gpio_chip.ngpio = npins;
1004 bank->gpio_chip.of_node = np;
1005 bank->gpio_chip.parent = dev;
1006 bank->bank_nr = bank_nr;
1007 spin_lock_init(&bank->lock);
1008
1009
1010 bank->fwnode = of_node_to_fwnode(np);
1011
1012 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0,
1013 STM32_GPIO_IRQ_LINE, bank->fwnode,
1014 &stm32_gpio_domain_ops, bank);
1015
1016 if (!bank->domain)
1017 return -ENODEV;
1018
1019 err = gpiochip_add_data(&bank->gpio_chip, bank);
1020 if (err) {
1021 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1022 return err;
1023 }
1024
1025 dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1026 return 0;
1027}
1028
1029static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1030 struct stm32_pinctrl *pctl)
1031{
1032 struct device_node *np = pdev->dev.of_node, *parent;
1033 struct device *dev = &pdev->dev;
1034 struct regmap *rm;
1035 int offset, ret, i;
1036
1037 parent = of_irq_find_parent(np);
1038 if (!parent)
1039 return -ENXIO;
1040
1041 pctl->domain = irq_find_host(parent);
1042 if (!pctl->domain)
1043 return -ENXIO;
1044
1045 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1046 if (IS_ERR(pctl->regmap))
1047 return PTR_ERR(pctl->regmap);
1048
1049 rm = pctl->regmap;
1050
1051 ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1052 if (ret)
1053 return ret;
1054
1055 for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1056 struct reg_field mux;
1057
1058 mux.reg = offset + (i / 4) * 4;
1059 mux.lsb = (i % 4) * 4;
1060 mux.msb = mux.lsb + 3;
1061
1062 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1063 if (IS_ERR(pctl->irqmux[i]))
1064 return PTR_ERR(pctl->irqmux[i]);
1065 }
1066
1067 return 0;
1068}
1069
1070static int stm32_pctrl_build_state(struct platform_device *pdev)
1071{
1072 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1073 int i;
1074
1075 pctl->ngroups = pctl->match_data->npins;
1076
1077
1078 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1079 sizeof(*pctl->groups), GFP_KERNEL);
1080 if (!pctl->groups)
1081 return -ENOMEM;
1082
1083
1084 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1085 sizeof(*pctl->grp_names), GFP_KERNEL);
1086 if (!pctl->grp_names)
1087 return -ENOMEM;
1088
1089 for (i = 0; i < pctl->match_data->npins; i++) {
1090 const struct stm32_desc_pin *pin = pctl->match_data->pins + i;
1091 struct stm32_pinctrl_group *group = pctl->groups + i;
1092
1093 group->name = pin->pin.name;
1094 group->pin = pin->pin.number;
1095
1096 pctl->grp_names[i] = pin->pin.name;
1097 }
1098
1099 return 0;
1100}
1101
1102int stm32_pctl_probe(struct platform_device *pdev)
1103{
1104 struct device_node *np = pdev->dev.of_node;
1105 struct device_node *child;
1106 const struct of_device_id *match;
1107 struct device *dev = &pdev->dev;
1108 struct stm32_pinctrl *pctl;
1109 struct pinctrl_pin_desc *pins;
1110 int i, ret, banks = 0;
1111
1112 if (!np)
1113 return -EINVAL;
1114
1115 match = of_match_device(dev->driver->of_match_table, dev);
1116 if (!match || !match->data)
1117 return -EINVAL;
1118
1119 if (!of_find_property(np, "pins-are-numbered", NULL)) {
1120 dev_err(dev, "only support pins-are-numbered format\n");
1121 return -EINVAL;
1122 }
1123
1124 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1125 if (!pctl)
1126 return -ENOMEM;
1127
1128 platform_set_drvdata(pdev, pctl);
1129
1130 pctl->dev = dev;
1131 pctl->match_data = match->data;
1132 ret = stm32_pctrl_build_state(pdev);
1133 if (ret) {
1134 dev_err(dev, "build state failed: %d\n", ret);
1135 return -EINVAL;
1136 }
1137
1138 if (of_find_property(np, "interrupt-parent", NULL)) {
1139 ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1140 if (ret)
1141 return ret;
1142 }
1143
1144 pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins),
1145 GFP_KERNEL);
1146 if (!pins)
1147 return -ENOMEM;
1148
1149 for (i = 0; i < pctl->match_data->npins; i++)
1150 pins[i] = pctl->match_data->pins[i].pin;
1151
1152 pctl->pctl_desc.name = dev_name(&pdev->dev);
1153 pctl->pctl_desc.owner = THIS_MODULE;
1154 pctl->pctl_desc.pins = pins;
1155 pctl->pctl_desc.npins = pctl->match_data->npins;
1156 pctl->pctl_desc.confops = &stm32_pconf_ops;
1157 pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1158 pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1159 pctl->dev = &pdev->dev;
1160
1161 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1162 pctl);
1163
1164 if (IS_ERR(pctl->pctl_dev)) {
1165 dev_err(&pdev->dev, "Failed pinctrl registration\n");
1166 return PTR_ERR(pctl->pctl_dev);
1167 }
1168
1169 for_each_child_of_node(np, child)
1170 if (of_property_read_bool(child, "gpio-controller"))
1171 banks++;
1172
1173 if (!banks) {
1174 dev_err(dev, "at least one GPIO bank is required\n");
1175 return -EINVAL;
1176 }
1177 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1178 GFP_KERNEL);
1179 if (!pctl->banks)
1180 return -ENOMEM;
1181
1182 for_each_child_of_node(np, child) {
1183 if (of_property_read_bool(child, "gpio-controller")) {
1184 ret = stm32_gpiolib_register_bank(pctl, child);
1185 if (ret)
1186 return ret;
1187
1188 pctl->nbanks++;
1189 }
1190 }
1191
1192 dev_info(dev, "Pinctrl STM32 initialized\n");
1193
1194 return 0;
1195}
1196
1197
