LXR linux/drivers/spi/spi-pxa2xx.h

   1/*
   2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3 * Copyright (C) 2013, Intel Corporation
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 as
   7 * published by the Free Software Foundation.
   8 */
   9
  10#ifndef SPI_PXA2XX_H
  11#define SPI_PXA2XX_H
  12
  13#include <linux/atomic.h>
  14#include <linux/dmaengine.h>
  15#include <linux/errno.h>
  16#include <linux/io.h>
  17#include <linux/interrupt.h>
  18#include <linux/platform_device.h>
  19#include <linux/pxa2xx_ssp.h>
  20#include <linux/scatterlist.h>
  21#include <linux/sizes.h>
  22#include <linux/spi/spi.h>
  23#include <linux/spi/pxa2xx_spi.h>
  24
  25struct driver_data {
  26        /* Driver model hookup */
  27        struct platform_device *pdev;
  28
  29        /* SSP Info */
  30        struct ssp_device *ssp;
  31
  32        /* SPI framework hookup */
  33        enum pxa_ssp_type ssp_type;
  34        struct spi_controller *master;
  35
  36        /* PXA hookup */
  37        struct pxa2xx_spi_master *master_info;
  38
  39        /* SSP register addresses */
  40        void __iomem *ioaddr;
  41        phys_addr_t ssdr_physical;
  42
  43        /* SSP masks*/
  44        u32 dma_cr1;
  45        u32 int_cr1;
  46        u32 clear_sr;
  47        u32 mask_sr;
  48
  49        /* DMA engine support */
  50        atomic_t dma_running;
  51
  52        /* Current transfer state info */
  53        void *tx;
  54        void *tx_end;
  55        void *rx;
  56        void *rx_end;
  57        u8 n_bytes;
  58        int (*write)(struct driver_data *drv_data);
  59        int (*read)(struct driver_data *drv_data);
  60        irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
  61        void (*cs_control)(u32 command);
  62
  63        void __iomem *lpss_base;
  64
  65        /* GPIOs for chip selects */
  66        struct gpio_desc **cs_gpiods;
  67};
  68
  69struct chip_data {
  70        u32 cr1;
  71        u32 dds_rate;
  72        u32 timeout;
  73        u8 n_bytes;
  74        u32 dma_burst_size;
  75        u32 threshold;
  76        u32 dma_threshold;
  77        u16 lpss_rx_threshold;
  78        u16 lpss_tx_threshold;
  79        u8 enable_dma;
  80        union {
  81                struct gpio_desc *gpiod_cs;
  82                unsigned int frm;
  83        };
  84        int gpio_cs_inverted;
  85        int (*write)(struct driver_data *drv_data);
  86        int (*read)(struct driver_data *drv_data);
  87        void (*cs_control)(u32 command);
  88};
  89
  90static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
  91                                  unsigned reg)
  92{
  93        return __raw_readl(drv_data->ioaddr + reg);
  94}
  95
  96static  inline void pxa2xx_spi_write(const struct driver_data *drv_data,
  97                                     unsigned reg, u32 val)
  98{
  99        __raw_writel(val, drv_data->ioaddr + reg);
 100}
 101
 102#define DMA_ALIGNMENT           8
 103
 104static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
 105{
 106        switch (drv_data->ssp_type) {
 107        case PXA25x_SSP:
 108        case CE4100_SSP:
 109        case QUARK_X1000_SSP:
 110                return 1;
 111        default:
 112                return 0;
 113        }
 114}
 115
 116static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
 117{
 118        if (drv_data->ssp_type == CE4100_SSP ||
 119            drv_data->ssp_type == QUARK_X1000_SSP)
 120                val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
 121
 122        pxa2xx_spi_write(drv_data, SSSR, val);
 123}
 124
 125extern int pxa2xx_spi_flush(struct driver_data *drv_data);
 126
 127#define MAX_DMA_LEN             SZ_64K
 128#define DEFAULT_DMA_CR1         (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
 129
 130extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data);
 131extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data,
 132                                  struct spi_transfer *xfer);
 133extern void pxa2xx_spi_dma_start(struct driver_data *drv_data);
 134extern void pxa2xx_spi_dma_stop(struct driver_data *drv_data);
 135extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data);
 136extern void pxa2xx_spi_dma_release(struct driver_data *drv_data);
 137extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
 138                                                  struct spi_device *spi,
 139                                                  u8 bits_per_word,
 140                                                  u32 *burst_code,
 141                                                  u32 *threshold);
 142
 143#endif /* SPI_PXA2XX_H */
 144