1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _R819XU_PHYREG_H 3#define _R819XU_PHYREG_H 4 5 6#define RF_DATA 0x1d4 /* FW will write RF data in the register.*/ 7 8/* Register duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF 9 * page 1 10 */ 11#define rPMAC_Reset 0x100 12#define rPMAC_TxStart 0x104 13#define rPMAC_TxLegacySIG 0x108 14#define rPMAC_TxHTSIG1 0x10c 15#define rPMAC_TxHTSIG2 0x110 16#define rPMAC_PHYDebug 0x114 17#define rPMAC_TxPacketNum 0x118 18#define rPMAC_TxIdle 0x11c 19#define rPMAC_TxMACHeader0 0x120 20#define rPMAC_TxMACHeader1 0x124 21#define rPMAC_TxMACHeader2 0x128 22#define rPMAC_TxMACHeader3 0x12c 23#define rPMAC_TxMACHeader4 0x130 24#define rPMAC_TxMACHeader5 0x134 25#define rPMAC_TxDataType 0x138 26#define rPMAC_TxRandomSeed 0x13c 27#define rPMAC_CCKPLCPPreamble 0x140 28#define rPMAC_CCKPLCPHeader 0x144 29#define rPMAC_CCKCRC16 0x148 30#define rPMAC_OFDMRxCRC32OK 0x170 31#define rPMAC_OFDMRxCRC32Er 0x174 32#define rPMAC_OFDMRxParityEr 0x178 33#define rPMAC_OFDMRxCRC8Er 0x17c 34#define rPMAC_CCKCRxRC16Er 0x180 35#define rPMAC_CCKCRxRC32Er 0x184 36#define rPMAC_CCKCRxRC32OK 0x188 37#define rPMAC_TxStatus 0x18c 38 39/* page8 */ 40#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ 41#define rFPGA0_TxInfo 0x804 42#define rFPGA0_PSDFunction 0x808 43#define rFPGA0_TxGainStage 0x80c 44#define rFPGA0_RFTiming1 0x810 45#define rFPGA0_RFTiming2 0x814 46/* #define rFPGA0_XC_RFTiming 0x818 47 * #define rFPGA0_XD_RFTiming 0x81c 48 */ 49#define rFPGA0_XA_HSSIParameter1 0x820 50#define rFPGA0_XA_HSSIParameter2 0x824 51#define rFPGA0_XB_HSSIParameter1 0x828 52#define rFPGA0_XB_HSSIParameter2 0x82c 53#define rFPGA0_XC_HSSIParameter1 0x830 54#define rFPGA0_XC_HSSIParameter2 0x834 55#define rFPGA0_XD_HSSIParameter1 0x838 56#define rFPGA0_XD_HSSIParameter2 0x83c 57#define rFPGA0_XA_LSSIParameter 0x840 58#define rFPGA0_XB_LSSIParameter 0x844 59#define rFPGA0_XC_LSSIParameter 0x848 60#define rFPGA0_XD_LSSIParameter 0x84c 61#define rFPGA0_RFWakeUpParameter 0x850 62#define rFPGA0_RFSleepUpParameter 0x854 63#define rFPGA0_XAB_SwitchControl 0x858 64#define rFPGA0_XCD_SwitchControl 0x85c 65#define rFPGA0_XA_RFInterfaceOE 0x860 66#define rFPGA0_XB_RFInterfaceOE 0x864 67#define rFPGA0_XC_RFInterfaceOE 0x868 68#define rFPGA0_XD_RFInterfaceOE 0x86c 69#define rFPGA0_XAB_RFInterfaceSW 0x870 70#define rFPGA0_XCD_RFInterfaceSW 0x874 71#define rFPGA0_XAB_RFParameter 0x878 72#define rFPGA0_XCD_RFParameter 0x87c 73#define rFPGA0_AnalogParameter1 0x880 74#define rFPGA0_AnalogParameter2 0x884 75#define rFPGA0_AnalogParameter3 0x888 76#define rFPGA0_AnalogParameter4 0x88c 77#define rFPGA0_XA_LSSIReadBack 0x8a0 78#define rFPGA0_XB_LSSIReadBack 0x8a4 79#define rFPGA0_XC_LSSIReadBack 0x8a8 80#define rFPGA0_XD_LSSIReadBack 0x8ac 81#define rFPGA0_PSDReport 0x8b4 82#define rFPGA0_XAB_RFInterfaceRB 0x8e0 83#define rFPGA0_XCD_RFInterfaceRB 0x8e4 84 85/* page 9 */ 86#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ 87#define rFPGA1_TxBlock 0x904 88#define rFPGA1_DebugSelect 0x908 89#define rFPGA1_TxInfo 0x90c 90 91/* page a */ 92#define rCCK0_System 0xa00 93#define rCCK0_AFESetting 0xa04 94#define rCCK0_CCA 0xa08 95#define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level */ 96#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 97#define rCCK0_RxHP 0xa14 98#define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 99#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 100#define rCCK0_TxFilter1 0xa20 101#define rCCK0_TxFilter2 0xa24 102#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 103#define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d */ 104#define rCCK0_TRSSIReport 0xa50 105#define rCCK0_RxReport 0xa54 /* 0xa57 */ 106#define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 107#define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 108 109/* page c */ 110#define rOFDM0_LSTF 0xc00 111#define rOFDM0_TRxPathEnable 0xc04 112#define rOFDM0_TRMuxPar 0xc08 113#define rOFDM0_TRSWIsolation 0xc0c 114#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 115#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 116#define rOFDM0_XBRxAFE 0xc18 117#define rOFDM0_XBRxIQImbalance 0xc1c 118#define rOFDM0_XCRxAFE 0xc20 119#define rOFDM0_XCRxIQImbalance 0xc24 120#define rOFDM0_XDRxAFE 0xc28 121#define rOFDM0_XDRxIQImbalance 0xc2c 122#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */ 123#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/ 124#define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/ 125#define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 126#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 127#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 128#define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 129#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 130#define rOFDM0_XAAGCCore1 0xc50 131#define rOFDM0_XAAGCCore2 0xc54 132#define rOFDM0_XBAGCCore1 0xc58 133#define rOFDM0_XBAGCCore2 0xc5c 134#define rOFDM0_XCAGCCore1 0xc60 135#define rOFDM0_XCAGCCore2 0xc64 136#define rOFDM0_XDAGCCore1 0xc68 137#define rOFDM0_XDAGCCore2 0xc6c 138#define rOFDM0_AGCParameter1 0xc70 139#define rOFDM0_AGCParameter2 0xc74 140#define rOFDM0_AGCRSSITable 0xc78 141#define rOFDM0_HTSTFAGC 0xc7c 142#define rOFDM0_XATxIQImbalance 0xc80 143#define rOFDM0_XATxAFE 0xc84 144#define rOFDM0_XBTxIQImbalance 0xc88 145#define rOFDM0_XBTxAFE 0xc8c 146#define rOFDM0_XCTxIQImbalance 0xc90 147#define rOFDM0_XCTxAFE 0xc94 148#define rOFDM0_XDTxIQImbalance 0xc98 149#define rOFDM0_XDTxAFE 0xc9c 150#define rOFDM0_RxHPParameter 0xce0 151#define rOFDM0_TxPseudoNoiseWgt 0xce4 152#define rOFDM0_FrameSync 0xcf0 153#define rOFDM0_DFSReport 0xcf4 154#define rOFDM0_TxCoeff1 0xca4 155#define rOFDM0_TxCoeff2 0xca8 156#define rOFDM0_TxCoeff3 0xcac 157#define rOFDM0_TxCoeff4 0xcb0 158#define rOFDM0_TxCoeff5 0xcb4 159#define rOFDM0_TxCoeff6 0xcb8 160 161 162/* page d */ 163#define rOFDM1_LSTF 0xd00 164#define rOFDM1_TRxPathEnable 0xd04 165#define rOFDM1_CFO 0xd08 166#define rOFDM1_CSI1 0xd10 167#define rOFDM1_SBD 0xd14 168#define rOFDM1_CSI2 0xd18 169#define rOFDM1_CFOTracking 0xd2c 170#define rOFDM1_TRxMesaure1 0xd34 171#define rOFDM1_IntfDet 0xd3c 172#define rOFDM1_PseudoNoiseStateAB 0xd50 173#define rOFDM1_PseudoNoiseStateCD 0xd54 174#define rOFDM1_RxPseudoNoiseWgt 0xd58 175#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 176#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 177 178#define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 179#define rOFDM_ShortCFOAB 0xdac 180#define rOFDM_ShortCFOCD 0xdb0 181#define rOFDM_LongCFOAB 0xdb4 182#define rOFDM_LongCFOCD 0xdb8 183#define rOFDM_TailCFOAB 0xdbc 184#define rOFDM_TailCFOCD 0xdc0 185#define rOFDM_PWMeasure1 0xdc4 186#define rOFDM_PWMeasure2 0xdc8 187#define rOFDM_BWReport 0xdcc 188#define rOFDM_AGCReport 0xdd0 189#define rOFDM_RxSNR 0xdd4 190#define rOFDM_RxEVMCSI 0xdd8 191#define rOFDM_SIGReport 0xddc 192 193/* page e */ 194#define rTxAGC_Rate18_06 0xe00 195#define rTxAGC_Rate54_24 0xe04 196#define rTxAGC_CCK_Mcs32 0xe08 197#define rTxAGC_Mcs03_Mcs00 0xe10 198#define rTxAGC_Mcs07_Mcs04 0xe14 199#define rTxAGC_Mcs11_Mcs08 0xe18 200#define rTxAGC_Mcs15_Mcs12 0xe1c 201 202 203/* RF 204 * Zebra1 205 */ 206#define rZebra1_HSSIEnable 0x0 207#define rZebra1_TRxEnable1 0x1 208#define rZebra1_TRxEnable2 0x2 209#define rZebra1_AGC 0x4 210#define rZebra1_ChargePump 0x5 211#define rZebra1_Channel 0x7 212#define rZebra1_TxGain 0x8 213#define rZebra1_TxLPF 0x9 214#define rZebra1_RxLPF 0xb 215#define rZebra1_RxHPFCorner 0xc 216 217/* Zebra4 */ 218#define rGlobalCtrl 0 219#define rRTL8256_TxLPF 19 220#define rRTL8256_RxLPF 11 221 222/* RTL8258 */ 223#define rRTL8258_TxLPF 0x11 224#define rRTL8258_RxLPF 0x13 225#define rRTL8258_RSSILPF 0xa 226 227/* Bit Mask 228 * page-1 229 */ 230#define bBBResetB 0x100 231#define bGlobalResetB 0x200 232#define bOFDMTxStart 0x4 233#define bCCKTxStart 0x8 234#define bCRC32Debug 0x100 235#define bPMACLoopback 0x10 236#define bTxLSIG 0xffffff 237#define bOFDMTxRate 0xf 238#define bOFDMTxReserved 0x10 239#define bOFDMTxLength 0x1ffe0 240#define bOFDMTxParity 0x20000 241#define bTxHTSIG1 0xffffff 242#define bTxHTMCSRate 0x7f 243#define bTxHTBW 0x80 244#define bTxHTLength 0xffff00 245#define bTxHTSIG2 0xffffff 246#define bTxHTSmoothing 0x1 247#define bTxHTSounding 0x2 248#define bTxHTReserved 0x4 249#define bTxHTAggreation 0x8 250#define bTxHTSTBC 0x30 251#define bTxHTAdvanceCoding 0x40 252#define bTxHTShortGI 0x80 253#define bTxHTNumberHT_LTF 0x300 254#define bTxHTCRC8 0x3fc00 255#define bCounterReset 0x10000 256#define bNumOfOFDMTx 0xffff 257#define bNumOfCCKTx 0xffff0000 258#define bTxIdleInterval 0xffff 259#define bOFDMService 0xffff0000 260#define bTxMACHeader 0xffffffff 261#define bTxDataInit 0xff 262#define bTxHTMode 0x100 263#define bTxDataType 0x30000 264#define bTxRandomSeed 0xffffffff 265#define bCCKTxPreamble 0x1 266#define bCCKTxSFD 0xffff0000 267#define bCCKTxSIG 0xff 268#define bCCKTxService 0xff00 269#define bCCKLengthExt 0x8000 270#define bCCKTxLength 0xffff0000 271#define bCCKTxCRC16 0xffff 272#define bCCKTxStatus 0x1 273#define bOFDMTxStatus 0x2 274 275/* page-8 */ 276#define bRFMOD 0x1 277#define bJapanMode 0x2 278#define bCCKTxSC 0x30 279#define bCCKEn 0x1000000 280#define bOFDMEn 0x2000000 281#define bOFDMRxADCPhase 0x10000 282#define bOFDMTxDACPhase 0x40000 283#define bXATxAGC 0x3f 284#define bXBTxAGC 0xf00 285#define bXCTxAGC 0xf000 286#define bXDTxAGC 0xf0000 287#define bPAStart 0xf0000000 288#define bTRStart 0x00f00000 289#define bRFStart 0x0000f000 290#define bBBStart 0x000000f0 291#define bBBCCKStart 0x0000000f 292#define bPAEnd 0xf /* Reg0x814 */ 293#define bTREnd 0x0f000000 294#define bRFEnd 0x000f0000 295#define bCCAMask 0x000000f0 /* T2R */ 296#define bR2RCCAMask 0x00000f00 297#define bHSSI_R2TDelay 0xf8000000 298#define bHSSI_T2RDelay 0xf80000 299#define bContTxHSSI 0x400 /* chane gain at continue Tx */ 300#define bIGFromCCK 0x200 301#define bAGCAddress 0x3f 302#define bRxHPTx 0x7000 303#define bRxHPT2R 0x38000 304#define bRxHPCCKIni 0xc0000 305#define bAGCTxCode 0xc00000 306#define bAGCRxCode 0x300000 307#define b3WireDataLength 0x800 308#define b3WireAddressLength 0x400 309#define b3WireRFPowerDown 0x1 310/* #define bHWSISelect 0x8 */ 311#define b5GPAPEPolarity 0x40000000 312#define b2GPAPEPolarity 0x80000000 313#define bRFSW_TxDefaultAnt 0x3 314#define bRFSW_TxOptionAnt 0x30 315#define bRFSW_RxDefaultAnt 0x300 316#define bRFSW_RxOptionAnt 0x3000 317#define bRFSI_3WireData 0x1 318#define bRFSI_3WireClock 0x2 319#define bRFSI_3WireLoad 0x4 320#define bRFSI_3WireRW 0x8 321#define bRFSI_3Wire 0xf /* 3-wire total control */ 322#define bRFSI_RFENV 0x10 323#define bRFSI_TRSW 0x20 324#define bRFSI_TRSWB 0x40 325#define bRFSI_ANTSW 0x100 326#define bRFSI_ANTSWB 0x200 327#define bRFSI_PAPE 0x400 328#define bRFSI_PAPE5G 0x800 329#define bBandSelect 0x1 330#define bHTSIG2_GI 0x80 331#define bHTSIG2_Smoothing 0x01 332#define bHTSIG2_Sounding 0x02 333#define bHTSIG2_Aggreaton 0x08 334#define bHTSIG2_STBC 0x30 335#define bHTSIG2_AdvCoding 0x40 336#define bHTSIG2_NumOfHTLTF 0x300 337#define bHTSIG2_CRC8 0x3fc 338#define bHTSIG1_MCS 0x7f 339#define bHTSIG1_BandWidth 0x80 340#define bHTSIG1_HTLength 0xffff 341#define bLSIG_Rate 0xf 342#define bLSIG_Reserved 0x10 343#define bLSIG_Length 0x1fffe 344#define bLSIG_Parity 0x20 345#define bCCKRxPhase 0x4 346#define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */ 347#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 348#define bLSSIReadBackData 0xfff 349#define bLSSIReadOKFlag 0x1000 350#define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 351#define bRegulator0Standby 0x1 352#define bRegulatorPLLStandby 0x2 353#define bRegulator1Standby 0x4 354#define bPLLPowerUp 0x8 355#define bDPLLPowerUp 0x10 356#define bDA10PowerUp 0x20 357#define bAD7PowerUp 0x200 358#define bDA6PowerUp 0x2000 359#define bXtalPowerUp 0x4000 360#define b40MDClkPowerUP 0x8000 361#define bDA6DebugMode 0x20000 362#define bDA6Swing 0x380000 363#define bADClkPhase 0x4000000 364#define b80MClkDelay 0x18000000 365#define bAFEWatchDogEnable 0x20000000 366#define bXtalCap 0x0f000000 367#define bIntDifClkEnable 0x400 368#define bExtSigClkEnable 0x800 369#define bBandgapMbiasPowerUp 0x10000 370#define bAD11SHGain 0xc0000 371#define bAD11InputRange 0x700000 372#define bAD11OPCurrent 0x3800000 373#define bIPathLoopback 0x4000000 374#define bQPathLoopback 0x8000000 375#define bAFELoopback 0x10000000 376#define bDA10Swing 0x7e0 377#define bDA10Reverse 0x800 378#define bDAClkSource 0x1000 379#define bAD7InputRange 0x6000 380#define bAD7Gain 0x38000 381#define bAD7OutputCMMode 0x40000 382#define bAD7InputCMMode 0x380000 383#define bAD7Current 0xc00000 384#define bRegulatorAdjust 0x7000000 385#define bAD11PowerUpAtTx 0x1 386#define bDA10PSAtTx 0x10 387#define bAD11PowerUpAtRx 0x100 388#define bDA10PSAtRx 0x1000 389 390#define bCCKRxAGCFormat 0x200 391 392#define bPSDFFTSamplepPoint 0xc000 393#define bPSDAverageNum 0x3000 394#define bIQPathControl 0xc00 395#define bPSDFreq 0x3ff 396#define bPSDAntennaPath 0x30 397#define bPSDIQSwitch 0x40 398#define bPSDRxTrigger 0x400000 399#define bPSDTxTrigger 0x80000000 400#define bPSDSineToneScale 0x7f000000 401#define bPSDReport 0xffff 402 403/* page-9 */ 404#define bOFDMTxSC 0x30000000 405#define bCCKTxOn 0x1 406#define bOFDMTxOn 0x2 407#define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 408#define bDebugItem 0xff /* reset debug page and LWord */ 409#define bAntL 0x10 410#define bAntNonHT 0x100 411#define bAntHT1 0x1000 412#define bAntHT2 0x10000 413#define bAntHT1S1 0x100000 414#define bAntNonHTS1 0x1000000 415 416/* page-a */ 417#define bCCKBBMode 0x3 418#define bCCKTxPowerSaving 0x80 419#define bCCKRxPowerSaving 0x40 420#define bCCKSideBand 0x10 421#define bCCKScramble 0x8 422#define bCCKAntDiversity 0x8000 423#define bCCKCarrierRecovery 0x4000 424#define bCCKTxRate 0x3000 425#define bCCKDCCancel 0x0800 426#define bCCKISICancel 0x0400 427#define bCCKMatchFilter 0x0200 428#define bCCKEqualizer 0x0100 429#define bCCKPreambleDetect 0x800000 430#define bCCKFastFalseCCA 0x400000 431#define bCCKChEstStart 0x300000 432#define bCCKCCACount 0x080000 433#define bCCKcs_lim 0x070000 434#define bCCKBistMode 0x80000000 435#define bCCKCCAMask 0x40000000 436#define bCCKTxDACPhase 0x4 437#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 438#define bCCKr_cp_mode0 0x0100 439#define bCCKTxDCOffset 0xf0 440#define bCCKRxDCOffset 0xf 441#define bCCKCCAMode 0xc000 442#define bCCKFalseCS_lim 0x3f00 443#define bCCKCS_ratio 0xc00000 444#define bCCKCorgBit_sel 0x300000 445#define bCCKPD_lim 0x0f0000 446#define bCCKNewCCA 0x80000000 447#define bCCKRxHPofIG 0x8000 448#define bCCKRxIG 0x7f00 449#define bCCKLNAPolarity 0x800000 450#define bCCKRx1stGain 0x7f0000 451#define bCCKRFExtend 0x20000000 /* CCK Rx initial gain polarity */ 452#define bCCKRxAGCSatLevel 0x1f000000 453#define bCCKRxAGCSatCount 0xe0 454#define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 455#define bCCKFixedRxAGC 0x8000 456/* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */ 457#define bCCKAntennaPolarity 0x2000 458#define bCCKTxFilterType 0x0c00 459#define bCCKRxAGCReportType 0x0300 460#define bCCKRxDAGCEn 0x80000000 461#define bCCKRxDAGCPeriod 0x20000000 462#define bCCKRxDAGCSatLevel 0x1f000000 463#define bCCKTimingRecovery 0x800000 464#define bCCKTxC0 0x3f0000 465#define bCCKTxC1 0x3f000000 466#define bCCKTxC2 0x3f 467#define bCCKTxC3 0x3f00 468#define bCCKTxC4 0x3f0000 469#define bCCKTxC5 0x3f000000 470#define bCCKTxC6 0x3f 471#define bCCKTxC7 0x3f00 472#define bCCKDebugPort 0xff0000 473#define bCCKDACDebug 0x0f000000 474#define bCCKFalseAlarmEnable 0x8000 475#define bCCKFalseAlarmRead 0x4000 476#define bCCKTRSSI 0x7f 477#define bCCKRxAGCReport 0xfe 478#define bCCKRxReport_AntSel 0x80000000 479#define bCCKRxReport_MFOff 0x40000000 480#define bCCKRxRxReport_SQLoss 0x20000000 481#define bCCKRxReport_Pktloss 0x10000000 482#define bCCKRxReport_Lockedbit 0x08000000 483#define bCCKRxReport_RateError 0x04000000 484#define bCCKRxReport_RxRate 0x03000000 485#define bCCKRxFACounterLower 0xff 486#define bCCKRxFACounterUpper 0xff000000 487#define bCCKRxHPAGCStart 0xe000 488#define bCCKRxHPAGCFinal 0x1c00 489 490#define bCCKRxFalseAlarmEnable 0x8000 491#define bCCKFACounterFreeze 0x4000 492 493#define bCCKTxPathSel 0x10000000 494#define bCCKDefaultRxPath 0xc000000 495#define bCCKOptionRxPath 0x3000000 496 497/* page c */ 498#define bNumOfSTF 0x3 499#define bShift_L 0xc0 500#define bGI_TH 0xc 501#define bRxPathA 0x1 502#define bRxPathB 0x2 503#define bRxPathC 0x4 504#define bRxPathD 0x8 505#define bTxPathA 0x1 506#define bTxPathB 0x2 507#define bTxPathC 0x4 508#define bTxPathD 0x8 509#define bTRSSIFreq 0x200 510#define bADCBackoff 0x3000 511#define bDFIRBackoff 0xc000 512#define bTRSSILatchPhase 0x10000 513#define bRxIDCOffset 0xff 514#define bRxQDCOffset 0xff00 515#define bRxDFIRMode 0x1800000 516#define bRxDCNFType 0xe000000 517#define bRXIQImb_A 0x3ff 518#define bRXIQImb_B 0xfc00 519#define bRXIQImb_C 0x3f0000 520#define bRXIQImb_D 0xffc00000 521#define bDC_dc_Notch 0x60000 522#define bRxNBINotch 0x1f000000 523#define bPD_TH 0xf 524#define bPD_TH_Opt2 0xc000 525#define bPWED_TH 0x700 526#define bIfMF_Win_L 0x800 527#define bPD_Option 0x1000 528#define bMF_Win_L 0xe000 529#define bBW_Search_L 0x30000 530#define bwin_enh_L 0xc0000 531#define bBW_TH 0x700000 532#define bED_TH2 0x3800000 533#define bBW_option 0x4000000 534#define bRatio_TH 0x18000000 535#define bWindow_L 0xe0000000 536#define bSBD_Option 0x1 537#define bFrame_TH 0x1c 538#define bFS_Option 0x60 539#define bDC_Slope_check 0x80 540#define bFGuard_Counter_DC_L 0xe00 541#define bFrame_Weight_Short 0x7000 542#define bSub_Tune 0xe00000 543#define bFrame_DC_Length 0xe000000 544#define bSBD_start_offset 0x30000000 545#define bFrame_TH_2 0x7 546#define bFrame_GI2_TH 0x38 547#define bGI2_Sync_en 0x40 548#define bSarch_Short_Early 0x300 549#define bSarch_Short_Late 0xc00 550#define bSarch_GI2_Late 0x70000 551#define bCFOAntSum 0x1 552#define bCFOAcc 0x2 553#define bCFOStartOffset 0xc 554#define bCFOLookBack 0x70 555#define bCFOSumWeight 0x80 556#define bDAGCEnable 0x10000 557#define bTXIQImb_A 0x3ff 558#define bTXIQImb_B 0xfc00 559#define bTXIQImb_C 0x3f0000 560#define bTXIQImb_D 0xffc00000 561#define bTxIDCOffset 0xff 562#define bTxQDCOffset 0xff00 563#define bTxDFIRMode 0x10000 564#define bTxPesudoNoiseOn 0x4000000 565#define bTxPesudoNoise_A 0xff 566#define bTxPesudoNoise_B 0xff00 567#define bTxPesudoNoise_C 0xff0000 568#define bTxPesudoNoise_D 0xff000000 569#define bCCADropOption 0x20000 570#define bCCADropThres 0xfff00000 571#define bEDCCA_H 0xf 572#define bEDCCA_L 0xf0 573#define bLambda_ED 0x300 574#define bRxInitialGain 0x7f 575#define bRxAntDivEn 0x80 576#define bRxAGCAddressForLNA 0x7f00 577#define bRxHighPowerFlow 0x8000 578#define bRxAGCFreezeThres 0xc0000 579#define bRxFreezeStep_AGC1 0x300000 580#define bRxFreezeStep_AGC2 0xc00000 581#define bRxFreezeStep_AGC3 0x3000000 582#define bRxFreezeStep_AGC0 0xc000000 583#define bRxRssi_Cmp_En 0x10000000 584#define bRxQuickAGCEn 0x20000000 585#define bRxAGCFreezeThresMode 0x40000000 586#define bRxOverFlowCheckType 0x80000000 587#define bRxAGCShift 0x7f 588#define bTRSW_Tri_Only 0x80 589#define bPowerThres 0x300 590#define bRxAGCEn 0x1 591#define bRxAGCTogetherEn 0x2 592#define bRxAGCMin 0x4 593#define bRxHP_Ini 0x7 594#define bRxHP_TRLNA 0x70 595#define bRxHP_RSSI 0x700 596#define bRxHP_BBP1 0x7000 597#define bRxHP_BBP2 0x70000 598#define bRxHP_BBP3 0x700000 599#define bRSSI_H 0x7f0000 /* the threshold for high power */ 600#define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 601#define bRxSettle_TRSW 0x7 602#define bRxSettle_LNA 0x38 603#define bRxSettle_RSSI 0x1c0 604#define bRxSettle_BBP 0xe00 605#define bRxSettle_RxHP 0x7000 606#define bRxSettle_AntSW_RSSI 0x38000 607#define bRxSettle_AntSW 0xc0000 608#define bRxProcessTime_DAGC 0x300000 609#define bRxSettle_HSSI 0x400000 610#define bRxProcessTime_BBPPW 0x800000 611#define bRxAntennaPowerShift 0x3000000 612#define bRSSITableSelect 0xc000000 613#define bRxHP_Final 0x7000000 614#define bRxHTSettle_BBP 0x7 615#define bRxHTSettle_HSSI 0x8 616#define bRxHTSettle_RxHP 0x70 617#define bRxHTSettle_BBPPW 0x80 618#define bRxHTSettle_Idle 0x300 619#define bRxHTSettle_Reserved 0x1c00 620#define bRxHTRxHPEn 0x8000 621#define bRxHTAGCFreezeThres 0x30000 622#define bRxHTAGCTogetherEn 0x40000 623#define bRxHTAGCMin 0x80000 624#define bRxHTAGCEn 0x100000 625#define bRxHTDAGCEn 0x200000 626#define bRxHTRxHP_BBP 0x1c00000 627#define bRxHTRxHP_Final 0xe0000000 628#define bRxPWRatioTH 0x3 629#define bRxPWRatioEn 0x4 630#define bRxMFHold 0x3800 631#define bRxPD_Delay_TH1 0x38 632#define bRxPD_Delay_TH2 0x1c0 633#define bRxPD_DC_COUNT_MAX 0x600 634/* #define bRxMF_Hold 0x3800 */ 635#define bRxPD_Delay_TH 0x8000 636#define bRxProcess_Delay 0xf0000 637#define bRxSearchrange_GI2_Early 0x700000 638#define bRxFrame_Guard_Counter_L 0x3800000 639#define bRxSGI_Guard_L 0xc000000 640#define bRxSGI_Search_L 0x30000000 641#define bRxSGI_TH 0xc0000000 642#define bDFSCnt0 0xff 643#define bDFSCnt1 0xff00 644#define bDFSFlag 0xf0000 645 646#define bMFWeightSum 0x300000 647#define bMinIdxTH 0x7f000000 648 649#define bDAFormat 0x40000 650 651#define bTxChEmuEnable 0x01000000 652 653#define bTRSWIsolation_A 0x7f 654#define bTRSWIsolation_B 0x7f00 655#define bTRSWIsolation_C 0x7f0000 656#define bTRSWIsolation_D 0x7f000000 657 658#define bExtLNAGain 0x7c00 659 660/* page d */ 661#define bSTBCEn 0x4 662#define bAntennaMapping 0x10 663#define bNss 0x20 664#define bCFOAntSumD 0x200 665#define bPHYCounterReset 0x8000000 666#define bCFOReportGet 0x4000000 667#define bOFDMContinueTx 0x10000000 668#define bOFDMSingleCarrier 0x20000000 669#define bOFDMSingleTone 0x40000000 670/* #define bRxPath1 0x01 671 * #define bRxPath2 0x02 672 * #define bRxPath3 0x04 673 * #define bRxPath4 0x08 674 * #define bTxPath1 0x10 675 * #define bTxPath2 0x20 676 */ 677#define bHTDetect 0x100 678#define bCFOEn 0x10000 679#define bCFOValue 0xfff00000 680#define bSigTone_Re 0x3f 681#define bSigTone_Im 0x7f00 682#define bCounter_CCA 0xffff 683#define bCounter_ParityFail 0xffff0000 684#define bCounter_RateIllegal 0xffff 685#define bCounter_CRC8Fail 0xffff0000 686#define bCounter_MCSNoSupport 0xffff 687#define bCounter_FastSync 0xffff 688#define bShortCFO 0xfff 689#define bShortCFOTLength 12 /* total */ 690#define bShortCFOFLength 11 /* fraction */ 691#define bLongCFO 0x7ff 692#define bLongCFOTLength 11 693#define bLongCFOFLength 11 694#define bTailCFO 0x1fff 695#define bTailCFOTLength 13 696#define bTailCFOFLength 12 697 698#define bmax_en_pwdB 0xffff 699#define bCC_power_dB 0xffff0000 700#define bnoise_pwdB 0xffff 701#define bPowerMeasTLength 10 702#define bPowerMeasFLength 3 703#define bRx_HT_BW 0x1 704#define bRxSC 0x6 705#define bRx_HT 0x8 706 707#define bNB_intf_det_on 0x1 708#define bIntf_win_len_cfg 0x30 709#define bNB_Intf_TH_cfg 0x1c0 710 711#define bRFGain 0x3f 712#define bTableSel 0x40 713#define bTRSW 0x80 714 715#define bRxSNR_A 0xff 716#define bRxSNR_B 0xff00 717#define bRxSNR_C 0xff0000 718#define bRxSNR_D 0xff000000 719#define bSNREVMTLength 8 720#define bSNREVMFLength 1 721 722#define bCSI1st 0xff 723#define bCSI2nd 0xff00 724#define bRxEVM1st 0xff0000 725#define bRxEVM2nd 0xff000000 726 727#define bSIGEVM 0xff 728#define bPWDB 0xff00 729#define bSGIEN 0x10000 730 731#define bSFactorQAM1 0xf 732#define bSFactorQAM2 0xf0 733#define bSFactorQAM3 0xf00 734#define bSFactorQAM4 0xf000 735#define bSFactorQAM5 0xf0000 736#define bSFactorQAM6 0xf0000 737#define bSFactorQAM7 0xf00000 738#define bSFactorQAM8 0xf000000 739#define bSFactorQAM9 0xf0000000 740#define bCSIScheme 0x100000 741 742#define bNoiseLvlTopSet 0x3 743#define bChSmooth 0x4 744#define bChSmoothCfg1 0x38 745#define bChSmoothCfg2 0x1c0 746#define bChSmoothCfg3 0xe00 747#define bChSmoothCfg4 0x7000 748#define bMRCMode 0x800000 749#define bTHEVMCfg 0x7000000 750 751#define bLoopFitType 0x1 752#define bUpdCFO 0x40 753#define bUpdCFOOffData 0x80 754#define bAdvUpdCFO 0x100 755#define bAdvTimeCtrl 0x800 756#define bUpdClko 0x1000 757#define bFC 0x6000 758#define bTrackingMode 0x8000 759#define bPhCmpEnable 0x10000 760#define bUpdClkoLTF 0x20000 761#define bComChCFO 0x40000 762#define bCSIEstiMode 0x80000 763#define bAdvUpdEqz 0x100000 764#define bUChCfg 0x7000000 765#define bUpdEqz 0x8000000 766 767/* page e */ 768#define bTxAGCRate18_06 0x7f7f7f7f 769#define bTxAGCRate54_24 0x7f7f7f7f 770#define bTxAGCRateMCS32 0x7f 771#define bTxAGCRateCCK 0x7f00 772#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f 773#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f 774#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f 775#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f 776 777 778/* Rx Pseduo noise */ 779#define bRxPesudoNoiseOn 0x20000000 780#define bRxPesudoNoise_A 0xff 781#define bRxPesudoNoise_B 0xff00 782#define bRxPesudoNoise_C 0xff0000 783#define bRxPesudoNoise_D 0xff000000 784#define bPesudoNoiseState_A 0xffff 785#define bPesudoNoiseState_B 0xffff0000 786#define bPesudoNoiseState_C 0xffff 787#define bPesudoNoiseState_D 0xffff0000 788 789/* RF 790 * Zebra1 791 */ 792#define bZebra1_HSSIEnable 0x8 793#define bZebra1_TRxControl 0xc00 794#define bZebra1_TRxGainSetting 0x07f 795#define bZebra1_RxCorner 0xc00 796#define bZebra1_TxChargePump 0x38 797#define bZebra1_RxChargePump 0x7 798#define bZebra1_ChannelNum 0xf80 799#define bZebra1_TxLPFBW 0x400 800#define bZebra1_RxLPFBW 0x600 801 802/* Zebra4 */ 803#define bRTL8256RegModeCtrl1 0x100 804#define bRTL8256RegModeCtrl0 0x40 805#define bRTL8256_TxLPFBW 0x18 806#define bRTL8256_RxLPFBW 0x600 807 808/* RTL8258 */ 809#define bRTL8258_TxLPFBW 0xc 810#define bRTL8258_RxLPFBW 0xc00 811#define bRTL8258_RSSILPFBW 0xc0 812 813/* byte endable for sb_write */ 814#define bByte0 0x1 815#define bByte1 0x2 816#define bByte2 0x4 817#define bByte3 0x8 818#define bWord0 0x3 819#define bWord1 0xc 820#define bDWord 0xf 821 822/* for PutRegsetting & GetRegSetting BitMask */ 823#define bMaskByte0 0xff 824#define bMaskByte1 0xff00 825#define bMaskByte2 0xff0000 826#define bMaskByte3 0xff000000 827#define bMaskHWord 0xffff0000 828#define bMaskLWord 0x0000ffff 829#define bMaskDWord 0xffffffff 830 831/* for PutRFRegsetting & GetRFRegSetting BitMask */ 832#define bMask12Bits 0xfff 833 834#define bEnable 0x1 835#define bDisable 0x0 836 837#define LeftAntenna 0x0 838#define RightAntenna 0x1 839 840#define tCheckTxStatus 500 /* 500ms */ 841#define tUpdateRxCounter 100 /* 100ms */ 842 843#define rateCCK 0 844#define rateOFDM 1 845#define rateHT 2 846 847/* define Register-End */ 848#define bPMAC_End 0x1ff 849#define bFPGAPHY0_End 0x8ff 850#define bFPGAPHY1_End 0x9ff 851#define bCCKPHY0_End 0xaff 852#define bOFDMPHY0_End 0xcff 853#define bOFDMPHY1_End 0xdff 854 855/* define max debug item in each debug page 856 * #define bMaxItem_FPGA_PHY0 0x9 857 * #define bMaxItem_FPGA_PHY1 0x3 858 * #define bMaxItem_PHY_11B 0x16 859 * #define bMaxItem_OFDM_PHY0 0x29 860 * #define bMaxItem_OFDM_PHY1 0x0 861 */ 862 863#define bPMACControl 0x0 864#define bWMACControl 0x1 865#define bWNICControl 0x2 866 867#define PathA 0x0 868#define PathB 0x1 869#define PathC 0x2 870#define PathD 0x3 871 872#define rRTL8256RxMixerPole 0xb 873#define bZebraRxMixerPole 0x6 874#define rRTL8256TxBBOPBias 0x9 875#define bRTL8256TxBBOPBias 0x400 876#define rRTL8256TxBBBW 19 877#define bRTL8256TxBBBW 0x18 878 879#endif /* __INC_HAL8190PCIPHYREG_H */ 880