linux/drivers/staging/rtlwifi/halmac/halmac_88xx/halmac_8822b/halmac_8822b_pwr_seq.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2016  Realtek Corporation.
   5 *
   6 * Contact Information:
   7 * wlanfae <wlanfae@realtek.com>
   8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9 * Hsinchu 300, Taiwan.
  10 *
  11 * Larry Finger <Larry.Finger@lwfinger.net>
  12 *
  13 *****************************************************************************/
  14#include "../halmac_88xx_cfg.h"
  15#include "halmac_8822b_cfg.h"
  16
  17static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT[] = {
  18        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
  19        {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  20         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  21         BIT(1), 0}, /*SWR OCP = SWR OCP = 010 1382.40*/
  22        {0x0012, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  23         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  24         BIT(0), BIT(0)}, /*SWR OCP = 010 1382.40 */
  25        {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  26         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
  27         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(0),
  28         BIT(0)}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/
  29        {0x0001, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  30         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
  31         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY, 1,
  32         HALMAC_PWRSEQ_DELAY_MS}, /*Delay 1ms*/
  33        {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  34         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
  35         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
  36         0}, /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/
  37        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  38         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  39         (BIT(4) | BIT(3) | BIT(2)),
  40         0}, /* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/
  41        {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  42         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  43         BIT(0), BIT(0)}, /* Disable USB suspend */
  44        {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  45         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
  46         HALMAC_PWR_CMD_POLLING, BIT(1),
  47         BIT(1)}, /* wait till 0x04[17] = 1    power ready*/
  48        {0x0075, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  49         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  50         BIT(0), 0}, /* Enable USB suspend */
  51        {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  52         HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  53         0xFF, 0}, /*0xFF1A = 0 to release resume signals*/
  54        {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  55         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  56         BIT(0), BIT(0)}, /* release WLON reset  0x04[16]=1*/
  57        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  58         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  59         BIT(7), 0}, /* disable HWPDN 0x04[15]=0*/
  60        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  61         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  62         (BIT(4) | BIT(3)), 0}, /* disable WL suspend*/
  63        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  64         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  65         BIT(0), BIT(0)}, /* polling until return 0*/
  66        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  67         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
  68         HALMAC_PWR_CMD_POLLING, BIT(0), 0},
  69        {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  70         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  71         BIT(3), BIT(3)}, /*Enable XTAL_CLK*/
  72        {0x10A8, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
  73         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  74         0xFF, 0}, /*NFC pad enabled*/
  75        {0x10A9, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
  76         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  77         0xFF, 0xef}, /*NFC pad enabled*/
  78        {0x10AA, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
  79         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  80         0xFF, 0x0c}, /*NFC pad enabled*/
  81        {0x0068, HALMAC_PWR_CUT_C_MSK, HALMAC_PWR_FAB_ALL_MSK,
  82         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
  83         HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /*SDIO pad power down disabled*/
  84        {0x0029, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  85         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  86         0xFF, 0xF9}, /*PLL seting*/
  87        {0x0024, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  88         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  89         BIT(2), 0}, /*Improve TX EVM of CH13 and some 5G channles */
  90        {0x0074, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  91         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
  92         BIT(5), BIT(5)}, /*PCIE WAKE# enabled*/
  93        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
  94         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
  95};
  96
  97static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU[] = {
  98        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
  99        {0x0003, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 100         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 101         HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /*0x02[10] = 0 Disable MCU Core*/
 102        {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 103         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 104         BIT(3), 0}, /*LPS option 0x93[3]=0 , SWR PFM*/
 105        {0x001F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 106         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 107         0xFF, 0}, /*0x1F[7:0] = 0 turn off RF*/
 108        {0x00EF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 109         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 110         0xFF, 0}, /*0xEF[7:0] = 0 turn off RF*/
 111        {0xFF1A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 112         HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 113         0xFF, 0x30}, /*0xFF1A = 0x30 to block resume signals*/
 114        {0x0049, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 115         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 116         BIT(1), 0}, /*Enable rising edge triggering interrupt*/
 117        {0x0006, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 118         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 119         BIT(0), BIT(0)}, /* release WLON reset  0x04[16]=1*/
 120        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 121         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 122         BIT(1), 0}, /* Whole BB is reset */
 123        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 124         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 125         BIT(1), BIT(1)}, /*0x04[9] = 1 turn off MAC by HW state machine*/
 126        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 127         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 128         HALMAC_PWR_CMD_POLLING, BIT(1),
 129         0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/
 130        {0x0020, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 131         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 132         BIT(3), 0}, /* XTAL_CLK gated*/
 133        {0x0000, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 134         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
 135         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(5),
 136         BIT(5)}, /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/
 137        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 138         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 139};
 140
 141static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS[] = {
 142        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 143        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 144         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 145         BIT(4) | BIT(3),
 146         (BIT(4) | BIT(3))}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
 147        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 148         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
 149         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
 150         BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
 151        {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 152         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 153         HALMAC_PWR_CMD_WRITE, 0xFF,
 154         0x20}, /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/
 155        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 156         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 157         BIT(3) | BIT(4),
 158         BIT(3) | BIT(4)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/
 159        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 160         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 161         HALMAC_PWR_CMD_WRITE, BIT(0),
 162         BIT(0)}, /*Set SDIO suspend local register*/
 163        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 164         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 165         HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
 166        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 167         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 168};
 169
 170static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU[] = {
 171        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 172        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 173         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 174         BIT(3) | BIT(7), 0}, /*clear suspend enable and power down enable*/
 175        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 176         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 177         HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
 178        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 179         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 180         HALMAC_PWR_CMD_POLLING, BIT(1),
 181         BIT(1)}, /*wait power state to suspend*/
 182        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 183         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 184         BIT(3) | BIT(4), 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
 185        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 186         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 187};
 188
 189static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS[] = {
 190        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 191        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 192         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 193         HALMAC_PWR_CMD_WRITE, BIT(7),
 194         BIT(7)}, /*suspend enable and power down enable*/
 195        {0x0007, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 196         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
 197         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, 0xFF,
 198         0x20}, /*0x07=0x20 , SOP option to disable BG/MB*/
 199        {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 200         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 201         BIT(5), 0}, /*0x67[5]=0 , BIT_PAPE_WLBT_SEL*/
 202        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 203         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_SDIO_MSK,
 204         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(3) | BIT(4),
 205         BIT(3)}, /*0x04[12:11] = 2b'01 enable WL suspend*/
 206        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 207         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 208         BIT(2), BIT(2)}, /*0x04[10] = 1, enable SW LPS*/
 209        {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 210         HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 211         BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
 212        {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 213         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 214         HALMAC_PWR_CMD_WRITE, BIT(5),
 215         0}, /* 0: BT PAPE control ; 1: WL BB LNAON control*/
 216        {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 217         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 218         HALMAC_PWR_CMD_WRITE, BIT(4),
 219         0}, /* 0: BT GPIO[11:10] control  ; 1: WL BB LNAON control*/
 220        {0x004F, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 221         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 222         HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /* 0: BT Control*/
 223        {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 224         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 225         HALMAC_PWR_CMD_WRITE, BIT(1),
 226         0}, /* turn off BT_3DD_SYNC_B and BT_GPIO[18] */
 227        {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 228         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 229         HALMAC_PWR_CMD_WRITE, BIT(6), BIT(6)}, /* GPIO[6] : Output mode*/
 230        {0x0067, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 231         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 232         HALMAC_PWR_CMD_WRITE, BIT(2), 0}, /* turn off BT_GPIO[16] */
 233        {0x0046, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 234         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 235         HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /* GPIO[7] : Output mode*/
 236        {0x0062, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 237         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_MAC,
 238         HALMAC_PWR_CMD_WRITE, BIT(4), BIT(4)}, /* GPIO[12] : Output mode */
 239        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 240         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 241         HALMAC_PWR_CMD_WRITE, BIT(0),
 242         BIT(0)}, /*Set SDIO suspend local register*/
 243        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 244         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 245         HALMAC_PWR_CMD_POLLING, BIT(1), 0}, /*wait power state to suspend*/
 246        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 247         HALMAC_PWR_INTF_USB_MSK | HALMAC_PWR_INTF_PCI_MSK,
 248         HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE, BIT(1),
 249         0}, /*0x90[1]=0 , disable 32k clock*/
 250        {0x0044, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 251         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 252         HALMAC_PWR_CMD_WRITE, 0xFF,
 253         0}, /*0x90[1]=0 , disable 32k clock by indirect access*/
 254        {0x0040, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 255         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 256         HALMAC_PWR_CMD_WRITE, 0xFF,
 257         0x90}, /*0x90[1]=0 , disable 32k clock by indirect access*/
 258        {0x0041, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 259         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 260         HALMAC_PWR_CMD_WRITE, 0xFF,
 261         0x00}, /*0x90[1]=0 , disable 32k clock by indirect access*/
 262        {0x0042, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 263         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 264         HALMAC_PWR_CMD_WRITE, 0xFF,
 265         0x04}, /*0x90[1]=0 , disable 32k clock by indirect access*/
 266        {0x0081, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 267         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 268         BIT(7), 0}, /*0x80[15]clean fw init ready bit*/
 269        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 270         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 271};
 272
 273static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU[] = {
 274        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 275        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 276         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 277         HALMAC_PWR_CMD_WRITE, BIT(0), 0}, /*Set SDIO suspend local register*/
 278        {0x0086, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 279         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 280         HALMAC_PWR_CMD_POLLING, BIT(1),
 281         BIT(1)}, /*wait power state to suspend*/
 282        {0x004A, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 283         HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 284         BIT(0), 0}, /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
 285        {0x0005, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 286         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 287         BIT(3) | BIT(4) | BIT(7),
 288         0}, /*clear suspend enable and power down enable*/
 289        {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 290         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 291         0xFF, 0},
 292        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 293         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 294};
 295
 296static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_LPS[] = {
 297        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 298        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 299         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 300         BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
 301        {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 302         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 303         BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
 304        {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 305         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 306         BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
 307        {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 308         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 309         BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
 310        {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 311         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 312         BIT(0), BIT(0)}, /* enable 32K CLK*/
 313        {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 314         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 315         0xFF, 0x42}, /* LPS Option MAC OFF enable*/
 316        {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 317         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 318         0xFF, 0x20}, /* LPS Option  Enable memory to deep sleep mode*/
 319        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 320         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 321         BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
 322        {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 323         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 324         0xFF, 0xFF}, /*PCIe DMA stop*/
 325        {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 326         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 327         0xFF, 0xFF}, /*Tx Pause*/
 328        {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 329         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 330         HALMAC_PWR_CMD_POLLING, 0xFF,
 331         0}, /*Should be zero if no packet is transmitting*/
 332        {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 333         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 334         HALMAC_PWR_CMD_POLLING, 0xFF,
 335         0}, /*Should be zero if no packet is transmitting*/
 336        {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 337         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 338         HALMAC_PWR_CMD_POLLING, 0xFF,
 339         0}, /*Should be zero if no packet is transmitting*/
 340        {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 341         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 342         HALMAC_PWR_CMD_POLLING, 0xFF,
 343         0}, /*Should be zero if no packet is transmitting*/
 344        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 345         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 346         BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
 347        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 348         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
 349         0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
 350        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 351         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 352         BIT(1), 0}, /*Whole BB is reset*/
 353        {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 354         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 355         0xFF, 0x3F}, /*Reset MAC TRX*/
 356        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 357         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 358         BIT(1), 0}, /*check if removed later*/
 359        {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 360         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 361         BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
 362        {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 363         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 364         BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
 365        {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 366         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 367         HALMAC_PWR_CMD_POLLING, BIT(7),
 368         BIT(7)}, /*Polling 0x109[7]=0  TSF in 40M*/
 369        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 370         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 371         BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
 372        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 373         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 374};
 375
 376static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS[] = {
 377        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 378        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 379         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 380         BIT(2), BIT(2)}, /*Enable 32k calibration and thermal meter*/
 381        {0x0199, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 382         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 383         BIT(3), BIT(3)}, /*Register write data of 32K calibration*/
 384        {0x019B, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 385         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 386         BIT(7), BIT(7)}, /*Enable 32k calibration reg write*/
 387        {0x1138, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 388         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 389         BIT(0) | BIT(1), BIT(0) | BIT(1)}, /*set RPWM IMR*/
 390        {0x0194, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 391         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 392         BIT(0), BIT(0)}, /* enable 32K CLK*/
 393        {0x0093, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 394         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 395         0xFF, 0x40}, /* LPS Option MAC OFF enable*/
 396        {0x0092, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 397         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 398         0xFF, 0x20}, /* LPS Option  Enable memory to deep sleep mode*/
 399        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 400         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 401         BIT(1), BIT(1)}, /* enable reg use 32K CLK*/
 402        {0x0301, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 403         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 404         0xFF, 0xFF}, /*PCIe DMA stop*/
 405        {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 406         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 407         0xFF, 0xFF}, /*Tx Pause*/
 408        {0x05F8, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 409         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 410         HALMAC_PWR_CMD_POLLING, 0xFF,
 411         0}, /*Should be zero if no packet is transmitting*/
 412        {0x05F9, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 413         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 414         HALMAC_PWR_CMD_POLLING, 0xFF,
 415         0}, /*Should be zero if no packet is transmitting*/
 416        {0x05FA, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 417         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 418         HALMAC_PWR_CMD_POLLING, 0xFF,
 419         0}, /*Should be zero if no packet is transmitting*/
 420        {0x05FB, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 421         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 422         HALMAC_PWR_CMD_POLLING, 0xFF,
 423         0}, /*Should be zero if no packet is transmitting*/
 424        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 425         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 426         BIT(0), 0}, /*CCK and OFDM are disabled,and clock are gated*/
 427        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 428         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
 429         0, HALMAC_PWRSEQ_DELAY_US}, /*Delay 1us*/
 430        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 431         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 432         BIT(1), 0}, /*Whole BB is reset*/
 433        {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 434         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 435         0xFF, 0x3F}, /*Reset MAC TRX*/
 436        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 437         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 438         BIT(1), 0}, /*check if removed later*/
 439        {0x0553, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 440         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 441         BIT(5), BIT(5)}, /*Respond TxOK to scheduler*/
 442        {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 443         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 444         BIT(4), BIT(4)}, /* switch TSF clock to 32K*/
 445        {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 446         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 447         HALMAC_PWR_CMD_POLLING, BIT(7),
 448         BIT(7)}, /*Polling 0x109[7]=1  TSF in 32K*/
 449        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 450         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 451         BIT(0), BIT(0)}, /* enable WL_LPS_EN*/
 452        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 453         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 454};
 455
 456static struct halmac_wl_pwr_cfg_ HALMAC_RTL8822B_TRANS_LPS_TO_ACT[] = {
 457        /* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value } */
 458        {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 459         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 460         HALMAC_PWR_CMD_WRITE, BIT(7), BIT(7)}, /*SDIO RPWM*/
 461        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 462         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
 463         0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
 464        {0x0080, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 465         HALMAC_PWR_INTF_SDIO_MSK, HALMAC_PWR_BASEADDR_SDIO,
 466         HALMAC_PWR_CMD_WRITE, BIT(7), 0}, /*SDIO RPWM*/
 467        {0xFE58, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 468         HALMAC_PWR_INTF_USB_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 469         0xFF, 0x84}, /*USB RPWM*/
 470        {0x0361, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 471         HALMAC_PWR_INTF_PCI_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 472         0xFF, 0x84}, /*PCIe RPWM*/
 473        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 474         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_DELAY,
 475         0, HALMAC_PWRSEQ_DELAY_MS}, /*Delay*/
 476        {0x0008, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 477         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 478         BIT(4), 0}, /* switch TSF to 40M*/
 479        {0x0109, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 480         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC,
 481         HALMAC_PWR_CMD_POLLING, BIT(7), 0}, /*Polling 0x109[7]=0  TSF in 40M*/
 482        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 483         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 484         BIT(1), BIT(1)},
 485        {0x0100, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 486         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 487         0xFF, 0xFF}, /*nable WMAC TRX*/
 488        {0x0002, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 489         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 490         BIT(1) | BIT(0), BIT(1) | BIT(0)}, /*nable BB macro*/
 491        {0x0522, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 492         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 493         0xFF, 0},
 494        {0x113C, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 495         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 496         0xFF, 0x03}, /*clear RPWM INT*/
 497        {0x0124, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 498         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 499         0xFF, 0xFF}, /*clear FW INT*/
 500        {0x0125, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 501         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 502         0xFF, 0xFF}, /*clear FW INT*/
 503        {0x0126, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 504         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 505         0xFF, 0xFF}, /*clear FW INT*/
 506        {0x0127, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 507         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 508         0xFF, 0xFF}, /*clear FW INT*/
 509        {0x0090, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 510         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 511         BIT(1), 0}, /* disable reg use 32K CLK*/
 512        {0x0101, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 513         HALMAC_PWR_INTF_ALL_MSK, HALMAC_PWR_BASEADDR_MAC, HALMAC_PWR_CMD_WRITE,
 514         BIT(2), 0}, /*disable 32k calibration and thermal meter*/
 515        {0xFFFF, HALMAC_PWR_CUT_ALL_MSK, HALMAC_PWR_FAB_ALL_MSK,
 516         HALMAC_PWR_INTF_ALL_MSK, 0, HALMAC_PWR_CMD_END, 0, 0},
 517};
 518
 519/* Card Enable Array */
 520struct halmac_wl_pwr_cfg_ *halmac_8822b_card_enable_flow[] = {
 521        HALMAC_RTL8822B_TRANS_CARDDIS_TO_CARDEMU,
 522        HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
 523
 524/* Card Disable Array */
 525struct halmac_wl_pwr_cfg_ *halmac_8822b_card_disable_flow[] = {
 526        HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
 527        HALMAC_RTL8822B_TRANS_CARDEMU_TO_CARDDIS, NULL};
 528
 529/* Suspend Array */
 530struct halmac_wl_pwr_cfg_ *halmac_8822b_suspend_flow[] = {
 531        HALMAC_RTL8822B_TRANS_ACT_TO_CARDEMU,
 532        HALMAC_RTL8822B_TRANS_CARDEMU_TO_SUS, NULL};
 533
 534/* Resume Array */
 535struct halmac_wl_pwr_cfg_ *halmac_8822b_resume_flow[] = {
 536        HALMAC_RTL8822B_TRANS_SUS_TO_CARDEMU,
 537        HALMAC_RTL8822B_TRANS_CARDEMU_TO_ACT, NULL};
 538
 539/* HWPDN Array - HW behavior */
 540struct halmac_wl_pwr_cfg_ *halmac_8822b_hwpdn_flow[] = {NULL};
 541
 542/* Enter LPS - FW behavior */
 543struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_lps_flow[] = {
 544        HALMAC_RTL8822B_TRANS_ACT_TO_LPS, NULL};
 545
 546/* Enter Deep LPS - FW behavior */
 547struct halmac_wl_pwr_cfg_ *halmac_8822b_enter_deep_lps_flow[] = {
 548        HALMAC_RTL8822B_TRANS_ACT_TO_DEEP_LPS, NULL};
 549
 550/* Leave LPS -FW behavior */
 551struct halmac_wl_pwr_cfg_ *halmac_8822b_leave_lps_flow[] = {
 552        HALMAC_RTL8822B_TRANS_LPS_TO_ACT, NULL};
 553
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.