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15#if defined(CONFIG_SERIAL_TXX9_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16#define SUPPORT_SYSRQ
17#endif
18
19#include <linux/module.h>
20#include <linux/ioport.h>
21#include <linux/init.h>
22#include <linux/console.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/pci.h>
26#include <linux/serial_core.h>
27#include <linux/serial.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30
31#include <asm/io.h>
32
33static char *serial_version = "1.11";
34static char *serial_name = "TX39/49 Serial driver";
35
36#define PASS_LIMIT 256
37
38#if !defined(CONFIG_SERIAL_TXX9_STDSERIAL)
39
40#define TXX9_TTY_NAME "ttyTX"
41#define TXX9_TTY_MINOR_START 196
42#define TXX9_TTY_MAJOR 204
43#else
44
45#define TXX9_TTY_NAME "ttyS"
46#define TXX9_TTY_MINOR_START 64
47#define TXX9_TTY_MAJOR TTY_MAJOR
48#endif
49
50
51#define UPF_TXX9_HAVE_CTS_LINE UPF_BUGGY_UART
52#define UPF_TXX9_USE_SCLK UPF_MAGIC_MULTIPLIER
53
54#ifdef CONFIG_PCI
55
56#define ENABLE_SERIAL_TXX9_PCI
57#endif
58
59
60
61
62#define UART_NR CONFIG_SERIAL_TXX9_NR_UARTS
63
64struct uart_txx9_port {
65 struct uart_port port;
66
67};
68
69#define TXX9_REGION_SIZE 0x24
70
71
72#define TXX9_SILCR 0x00
73#define TXX9_SIDICR 0x04
74#define TXX9_SIDISR 0x08
75#define TXX9_SICISR 0x0c
76#define TXX9_SIFCR 0x10
77#define TXX9_SIFLCR 0x14
78#define TXX9_SIBGR 0x18
79#define TXX9_SITFIFO 0x1c
80#define TXX9_SIRFIFO 0x20
81
82
83#define TXX9_SILCR_SCS_MASK 0x00000060
84#define TXX9_SILCR_SCS_IMCLK 0x00000000
85#define TXX9_SILCR_SCS_IMCLK_BG 0x00000020
86#define TXX9_SILCR_SCS_SCLK 0x00000040
87#define TXX9_SILCR_SCS_SCLK_BG 0x00000060
88#define TXX9_SILCR_UEPS 0x00000010
89#define TXX9_SILCR_UPEN 0x00000008
90#define TXX9_SILCR_USBL_MASK 0x00000004
91#define TXX9_SILCR_USBL_1BIT 0x00000000
92#define TXX9_SILCR_USBL_2BIT 0x00000004
93#define TXX9_SILCR_UMODE_MASK 0x00000003
94#define TXX9_SILCR_UMODE_8BIT 0x00000000
95#define TXX9_SILCR_UMODE_7BIT 0x00000001
96
97
98#define TXX9_SIDICR_TDE 0x00008000
99#define TXX9_SIDICR_RDE 0x00004000
100#define TXX9_SIDICR_TIE 0x00002000
101#define TXX9_SIDICR_RIE 0x00001000
102#define TXX9_SIDICR_SPIE 0x00000800
103#define TXX9_SIDICR_CTSAC 0x00000600
104#define TXX9_SIDICR_STIE_MASK 0x0000003f
105#define TXX9_SIDICR_STIE_OERS 0x00000020
106#define TXX9_SIDICR_STIE_CTSS 0x00000010
107#define TXX9_SIDICR_STIE_RBRKD 0x00000008
108#define TXX9_SIDICR_STIE_TRDY 0x00000004
109#define TXX9_SIDICR_STIE_TXALS 0x00000002
110#define TXX9_SIDICR_STIE_UBRKD 0x00000001
111
112
113#define TXX9_SIDISR_UBRK 0x00008000
114#define TXX9_SIDISR_UVALID 0x00004000
115#define TXX9_SIDISR_UFER 0x00002000
116#define TXX9_SIDISR_UPER 0x00001000
117#define TXX9_SIDISR_UOER 0x00000800
118#define TXX9_SIDISR_ERI 0x00000400
119#define TXX9_SIDISR_TOUT 0x00000200
120#define TXX9_SIDISR_TDIS 0x00000100
121#define TXX9_SIDISR_RDIS 0x00000080
122#define TXX9_SIDISR_STIS 0x00000040
123#define TXX9_SIDISR_RFDN_MASK 0x0000001f
124
125
126#define TXX9_SICISR_OERS 0x00000020
127#define TXX9_SICISR_CTSS 0x00000010
128#define TXX9_SICISR_RBRKD 0x00000008
129#define TXX9_SICISR_TRDY 0x00000004
130#define TXX9_SICISR_TXALS 0x00000002
131#define TXX9_SICISR_UBRKD 0x00000001
132
133
134#define TXX9_SIFCR_SWRST 0x00008000
135#define TXX9_SIFCR_RDIL_MASK 0x00000180
136#define TXX9_SIFCR_RDIL_1 0x00000000
137#define TXX9_SIFCR_RDIL_4 0x00000080
138#define TXX9_SIFCR_RDIL_8 0x00000100
139#define TXX9_SIFCR_RDIL_12 0x00000180
140#define TXX9_SIFCR_RDIL_MAX 0x00000180
141#define TXX9_SIFCR_TDIL_MASK 0x00000018
142#define TXX9_SIFCR_TDIL_1 0x00000000
143#define TXX9_SIFCR_TDIL_4 0x00000001
144#define TXX9_SIFCR_TDIL_8 0x00000010
145#define TXX9_SIFCR_TDIL_MAX 0x00000010
146#define TXX9_SIFCR_TFRST 0x00000004
147#define TXX9_SIFCR_RFRST 0x00000002
148#define TXX9_SIFCR_FRSTE 0x00000001
149#define TXX9_SIO_TX_FIFO 8
150#define TXX9_SIO_RX_FIFO 16
151
152
153#define TXX9_SIFLCR_RCS 0x00001000
154#define TXX9_SIFLCR_TES 0x00000800
155#define TXX9_SIFLCR_RTSSC 0x00000200
156#define TXX9_SIFLCR_RSDE 0x00000100
157#define TXX9_SIFLCR_TSDE 0x00000080
158#define TXX9_SIFLCR_RTSTL_MASK 0x0000001e
159#define TXX9_SIFLCR_RTSTL_MAX 0x0000001e
160#define TXX9_SIFLCR_TBRK 0x00000001
161
162
163#define TXX9_SIBGR_BCLK_MASK 0x00000300
164#define TXX9_SIBGR_BCLK_T0 0x00000000
165#define TXX9_SIBGR_BCLK_T2 0x00000100
166#define TXX9_SIBGR_BCLK_T4 0x00000200
167#define TXX9_SIBGR_BCLK_T6 0x00000300
168#define TXX9_SIBGR_BRD_MASK 0x000000ff
169
170static inline unsigned int sio_in(struct uart_txx9_port *up, int offset)
171{
172 switch (up->port.iotype) {
173 default:
174 return __raw_readl(up->port.membase + offset);
175 case UPIO_PORT:
176 return inl(up->port.iobase + offset);
177 }
178}
179
180static inline void
181sio_out(struct uart_txx9_port *up, int offset, int value)
182{
183 switch (up->port.iotype) {
184 default:
185 __raw_writel(value, up->port.membase + offset);
186 break;
187 case UPIO_PORT:
188 outl(value, up->port.iobase + offset);
189 break;
190 }
191}
192
193static inline void
194sio_mask(struct uart_txx9_port *up, int offset, unsigned int value)
195{
196 sio_out(up, offset, sio_in(up, offset) & ~value);
197}
198static inline void
199sio_set(struct uart_txx9_port *up, int offset, unsigned int value)
200{
201 sio_out(up, offset, sio_in(up, offset) | value);
202}
203
204static inline void
205sio_quot_set(struct uart_txx9_port *up, int quot)
206{
207 quot >>= 1;
208 if (quot < 256)
209 sio_out(up, TXX9_SIBGR, quot | TXX9_SIBGR_BCLK_T0);
210 else if (quot < (256 << 2))
211 sio_out(up, TXX9_SIBGR, (quot >> 2) | TXX9_SIBGR_BCLK_T2);
212 else if (quot < (256 << 4))
213 sio_out(up, TXX9_SIBGR, (quot >> 4) | TXX9_SIBGR_BCLK_T4);
214 else if (quot < (256 << 6))
215 sio_out(up, TXX9_SIBGR, (quot >> 6) | TXX9_SIBGR_BCLK_T6);
216 else
217 sio_out(up, TXX9_SIBGR, 0xff | TXX9_SIBGR_BCLK_T6);
218}
219
220static struct uart_txx9_port *to_uart_txx9_port(struct uart_port *port)
221{
222 return container_of(port, struct uart_txx9_port, port);
223}
224
225static void serial_txx9_stop_tx(struct uart_port *port)
226{
227 struct uart_txx9_port *up = to_uart_txx9_port(port);
228 sio_mask(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
229}
230
231static void serial_txx9_start_tx(struct uart_port *port)
232{
233 struct uart_txx9_port *up = to_uart_txx9_port(port);
234 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_TIE);
235}
236
237static void serial_txx9_stop_rx(struct uart_port *port)
238{
239 struct uart_txx9_port *up = to_uart_txx9_port(port);
240 up->port.read_status_mask &= ~TXX9_SIDISR_RDIS;
241}
242
243static void serial_txx9_initialize(struct uart_port *port)
244{
245 struct uart_txx9_port *up = to_uart_txx9_port(port);
246 unsigned int tmout = 10000;
247
248 sio_out(up, TXX9_SIFCR, TXX9_SIFCR_SWRST);
249
250
251 mmiowb();
252 udelay(1);
253 while ((sio_in(up, TXX9_SIFCR) & TXX9_SIFCR_SWRST) && --tmout)
254 udelay(1);
255
256 sio_set(up, TXX9_SIFCR,
257 TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1);
258
259 sio_out(up, TXX9_SILCR,
260 TXX9_SILCR_UMODE_8BIT | TXX9_SILCR_USBL_1BIT |
261 ((up->port.flags & UPF_TXX9_USE_SCLK) ?
262 TXX9_SILCR_SCS_SCLK_BG : TXX9_SILCR_SCS_IMCLK_BG));
263 sio_quot_set(up, uart_get_divisor(port, 9600));
264 sio_out(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSTL_MAX );
265 sio_out(up, TXX9_SIDICR, 0);
266}
267
268static inline void
269receive_chars(struct uart_txx9_port *up, unsigned int *status)
270{
271 unsigned char ch;
272 unsigned int disr = *status;
273 int max_count = 256;
274 char flag;
275 unsigned int next_ignore_status_mask;
276
277 do {
278 ch = sio_in(up, TXX9_SIRFIFO);
279 flag = TTY_NORMAL;
280 up->port.icount.rx++;
281
282
283 next_ignore_status_mask =
284 up->port.ignore_status_mask & ~TXX9_SIDISR_RFDN_MASK;
285 if (unlikely(disr & (TXX9_SIDISR_UBRK | TXX9_SIDISR_UPER |
286 TXX9_SIDISR_UFER | TXX9_SIDISR_UOER))) {
287
288
289
290 if (disr & TXX9_SIDISR_UBRK) {
291 disr &= ~(TXX9_SIDISR_UFER | TXX9_SIDISR_UPER);
292 up->port.icount.brk++;
293
294
295
296
297
298
299 if (uart_handle_break(&up->port))
300 goto ignore_char;
301 } else if (disr & TXX9_SIDISR_UPER)
302 up->port.icount.parity++;
303 else if (disr & TXX9_SIDISR_UFER)
304 up->port.icount.frame++;
305 if (disr & TXX9_SIDISR_UOER) {
306 up->port.icount.overrun++;
307
308
309
310
311
312
313 next_ignore_status_mask |=
314 TXX9_SIDISR_RFDN_MASK;
315 }
316
317
318
319
320 disr &= up->port.read_status_mask;
321
322 if (disr & TXX9_SIDISR_UBRK) {
323 flag = TTY_BREAK;
324 } else if (disr & TXX9_SIDISR_UPER)
325 flag = TTY_PARITY;
326 else if (disr & TXX9_SIDISR_UFER)
327 flag = TTY_FRAME;
328 }
329 if (uart_handle_sysrq_char(&up->port, ch))
330 goto ignore_char;
331
332 uart_insert_char(&up->port, disr, TXX9_SIDISR_UOER, ch, flag);
333
334 ignore_char:
335 up->port.ignore_status_mask = next_ignore_status_mask;
336 disr = sio_in(up, TXX9_SIDISR);
337 } while (!(disr & TXX9_SIDISR_UVALID) && (max_count-- > 0));
338 spin_unlock(&up->port.lock);
339 tty_flip_buffer_push(&up->port.state->port);
340 spin_lock(&up->port.lock);
341 *status = disr;
342}
343
344static inline void transmit_chars(struct uart_txx9_port *up)
345{
346 struct circ_buf *xmit = &up->port.state->xmit;
347 int count;
348
349 if (up->port.x_char) {
350 sio_out(up, TXX9_SITFIFO, up->port.x_char);
351 up->port.icount.tx++;
352 up->port.x_char = 0;
353 return;
354 }
355 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
356 serial_txx9_stop_tx(&up->port);
357 return;
358 }
359
360 count = TXX9_SIO_TX_FIFO;
361 do {
362 sio_out(up, TXX9_SITFIFO, xmit->buf[xmit->tail]);
363 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
364 up->port.icount.tx++;
365 if (uart_circ_empty(xmit))
366 break;
367 } while (--count > 0);
368
369 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
370 uart_write_wakeup(&up->port);
371
372 if (uart_circ_empty(xmit))
373 serial_txx9_stop_tx(&up->port);
374}
375
376static irqreturn_t serial_txx9_interrupt(int irq, void *dev_id)
377{
378 int pass_counter = 0;
379 struct uart_txx9_port *up = dev_id;
380 unsigned int status;
381
382 while (1) {
383 spin_lock(&up->port.lock);
384 status = sio_in(up, TXX9_SIDISR);
385 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE))
386 status &= ~TXX9_SIDISR_TDIS;
387 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
388 TXX9_SIDISR_TOUT))) {
389 spin_unlock(&up->port.lock);
390 break;
391 }
392
393 if (status & TXX9_SIDISR_RDIS)
394 receive_chars(up, &status);
395 if (status & TXX9_SIDISR_TDIS)
396 transmit_chars(up);
397
398 sio_mask(up, TXX9_SIDISR,
399 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS |
400 TXX9_SIDISR_TOUT);
401 spin_unlock(&up->port.lock);
402
403 if (pass_counter++ > PASS_LIMIT)
404 break;
405 }
406
407 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
408}
409
410static unsigned int serial_txx9_tx_empty(struct uart_port *port)
411{
412 struct uart_txx9_port *up = to_uart_txx9_port(port);
413 unsigned long flags;
414 unsigned int ret;
415
416 spin_lock_irqsave(&up->port.lock, flags);
417 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0;
418 spin_unlock_irqrestore(&up->port.lock, flags);
419
420 return ret;
421}
422
423static unsigned int serial_txx9_get_mctrl(struct uart_port *port)
424{
425 struct uart_txx9_port *up = to_uart_txx9_port(port);
426 unsigned int ret;
427
428
429 ret = TIOCM_CAR | TIOCM_DSR;
430 ret |= (sio_in(up, TXX9_SIFLCR) & TXX9_SIFLCR_RTSSC) ? 0 : TIOCM_RTS;
431 ret |= (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS) ? 0 : TIOCM_CTS;
432
433 return ret;
434}
435
436static void serial_txx9_set_mctrl(struct uart_port *port, unsigned int mctrl)
437{
438 struct uart_txx9_port *up = to_uart_txx9_port(port);
439
440 if (mctrl & TIOCM_RTS)
441 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
442 else
443 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RTSSC);
444}
445
446static void serial_txx9_break_ctl(struct uart_port *port, int break_state)
447{
448 struct uart_txx9_port *up = to_uart_txx9_port(port);
449 unsigned long flags;
450
451 spin_lock_irqsave(&up->port.lock, flags);
452 if (break_state == -1)
453 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
454 else
455 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
456 spin_unlock_irqrestore(&up->port.lock, flags);
457}
458
459#if defined(CONFIG_SERIAL_TXX9_CONSOLE) || defined(CONFIG_CONSOLE_POLL)
460
461
462
463static void wait_for_xmitr(struct uart_txx9_port *up)
464{
465 unsigned int tmout = 10000;
466
467
468 while (--tmout &&
469 !(sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS))
470 udelay(1);
471
472
473 if (up->port.flags & UPF_CONS_FLOW) {
474 tmout = 1000000;
475 while (--tmout &&
476 (sio_in(up, TXX9_SICISR) & TXX9_SICISR_CTSS))
477 udelay(1);
478 }
479}
480#endif
481
482#ifdef CONFIG_CONSOLE_POLL
483
484
485
486
487
488static int serial_txx9_get_poll_char(struct uart_port *port)
489{
490 unsigned int ier;
491 unsigned char c;
492 struct uart_txx9_port *up = to_uart_txx9_port(port);
493
494
495
496
497 ier = sio_in(up, TXX9_SIDICR);
498 sio_out(up, TXX9_SIDICR, 0);
499
500 while (sio_in(up, TXX9_SIDISR) & TXX9_SIDISR_UVALID)
501 ;
502
503 c = sio_in(up, TXX9_SIRFIFO);
504
505
506
507
508
509 sio_mask(up, TXX9_SIDISR, TXX9_SIDISR_RDIS);
510 sio_out(up, TXX9_SIDICR, ier);
511 return c;
512}
513
514
515static void serial_txx9_put_poll_char(struct uart_port *port, unsigned char c)
516{
517 unsigned int ier;
518 struct uart_txx9_port *up = to_uart_txx9_port(port);
519
520
521
522
523 ier = sio_in(up, TXX9_SIDICR);
524 sio_out(up, TXX9_SIDICR, 0);
525
526 wait_for_xmitr(up);
527
528
529
530 sio_out(up, TXX9_SITFIFO, c);
531
532
533
534
535
536 wait_for_xmitr(up);
537 sio_out(up, TXX9_SIDICR, ier);
538}
539
540#endif
541
542static int serial_txx9_startup(struct uart_port *port)
543{
544 struct uart_txx9_port *up = to_uart_txx9_port(port);
545 unsigned long flags;
546 int retval;
547
548
549
550
551
552 sio_set(up, TXX9_SIFCR,
553 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
554
555 sio_mask(up, TXX9_SIFCR,
556 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
557 sio_out(up, TXX9_SIDICR, 0);
558
559
560
561
562 sio_out(up, TXX9_SIDISR, 0);
563
564 retval = request_irq(up->port.irq, serial_txx9_interrupt,
565 IRQF_SHARED, "serial_txx9", up);
566 if (retval)
567 return retval;
568
569
570
571
572 spin_lock_irqsave(&up->port.lock, flags);
573 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
574 spin_unlock_irqrestore(&up->port.lock, flags);
575
576
577 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
578
579
580
581
582 sio_set(up, TXX9_SIDICR, TXX9_SIDICR_RIE);
583
584 return 0;
585}
586
587static void serial_txx9_shutdown(struct uart_port *port)
588{
589 struct uart_txx9_port *up = to_uart_txx9_port(port);
590 unsigned long flags;
591
592
593
594
595 sio_out(up, TXX9_SIDICR, 0);
596
597 spin_lock_irqsave(&up->port.lock, flags);
598 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
599 spin_unlock_irqrestore(&up->port.lock, flags);
600
601
602
603
604 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK);
605
606#ifdef CONFIG_SERIAL_TXX9_CONSOLE
607 if (up->port.cons && up->port.line == up->port.cons->index) {
608 free_irq(up->port.irq, up);
609 return;
610 }
611#endif
612
613 sio_set(up, TXX9_SIFCR,
614 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
615
616 sio_mask(up, TXX9_SIFCR,
617 TXX9_SIFCR_TFRST | TXX9_SIFCR_RFRST | TXX9_SIFCR_FRSTE);
618
619
620 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE);
621
622 free_irq(up->port.irq, up);
623}
624
625static void
626serial_txx9_set_termios(struct uart_port *port, struct ktermios *termios,
627 struct ktermios *old)
628{
629 struct uart_txx9_port *up = to_uart_txx9_port(port);
630 unsigned int cval, fcr = 0;
631 unsigned long flags;
632 unsigned int baud, quot;
633
634
635
636
637 termios->c_cflag &= ~(HUPCL | CMSPAR);
638 termios->c_cflag |= CLOCAL;
639
640 cval = sio_in(up, TXX9_SILCR);
641
642 cval &= ~TXX9_SILCR_UMODE_MASK;
643 switch (termios->c_cflag & CSIZE) {
644 case CS7:
645 cval |= TXX9_SILCR_UMODE_7BIT;
646 break;
647 default:
648 case CS5:
649 case CS6:
650 case CS8:
651 cval |= TXX9_SILCR_UMODE_8BIT;
652 break;
653 }
654
655 cval &= ~TXX9_SILCR_USBL_MASK;
656 if (termios->c_cflag & CSTOPB)
657 cval |= TXX9_SILCR_USBL_2BIT;
658 else
659 cval |= TXX9_SILCR_USBL_1BIT;
660 cval &= ~(TXX9_SILCR_UPEN | TXX9_SILCR_UEPS);
661 if (termios->c_cflag & PARENB)
662 cval |= TXX9_SILCR_UPEN;
663 if (!(termios->c_cflag & PARODD))
664 cval |= TXX9_SILCR_UEPS;
665
666
667
668
669 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16/2);
670 quot = uart_get_divisor(port, baud);
671
672
673
674 fcr = TXX9_SIFCR_TDIL_MAX | TXX9_SIFCR_RDIL_1;
675
676
677
678
679
680 spin_lock_irqsave(&up->port.lock, flags);
681
682
683
684
685 uart_update_timeout(port, termios->c_cflag, baud);
686
687 up->port.read_status_mask = TXX9_SIDISR_UOER |
688 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS;
689 if (termios->c_iflag & INPCK)
690 up->port.read_status_mask |= TXX9_SIDISR_UFER | TXX9_SIDISR_UPER;
691 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
692 up->port.read_status_mask |= TXX9_SIDISR_UBRK;
693
694
695
696
697 up->port.ignore_status_mask = 0;
698 if (termios->c_iflag & IGNPAR)
699 up->port.ignore_status_mask |= TXX9_SIDISR_UPER | TXX9_SIDISR_UFER;
700 if (termios->c_iflag & IGNBRK) {
701 up->port.ignore_status_mask |= TXX9_SIDISR_UBRK;
702
703
704
705
706 if (termios->c_iflag & IGNPAR)
707 up->port.ignore_status_mask |= TXX9_SIDISR_UOER;
708 }
709
710
711
712
713 if ((termios->c_cflag & CREAD) == 0)
714 up->port.ignore_status_mask |= TXX9_SIDISR_RDIS;
715
716
717 if ((termios->c_cflag & CRTSCTS) &&
718 (up->port.flags & UPF_TXX9_HAVE_CTS_LINE)) {
719 sio_set(up, TXX9_SIFLCR,
720 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
721 } else {
722 sio_mask(up, TXX9_SIFLCR,
723 TXX9_SIFLCR_RCS | TXX9_SIFLCR_TES);
724 }
725
726 sio_out(up, TXX9_SILCR, cval);
727 sio_quot_set(up, quot);
728 sio_out(up, TXX9_SIFCR, fcr);
729
730 serial_txx9_set_mctrl(&up->port, up->port.mctrl);
731 spin_unlock_irqrestore(&up->port.lock, flags);
732}
733
734static void
735serial_txx9_pm(struct uart_port *port, unsigned int state,
736 unsigned int oldstate)
737{
738
739
740
741
742
743
744
745
746 if (state == 0 && oldstate != -1)
747 serial_txx9_initialize(port);
748}
749
750static int serial_txx9_request_resource(struct uart_txx9_port *up)
751{
752 unsigned int size = TXX9_REGION_SIZE;
753 int ret = 0;
754
755 switch (up->port.iotype) {
756 default:
757 if (!up->port.mapbase)
758 break;
759
760 if (!request_mem_region(up->port.mapbase, size, "serial_txx9")) {
761 ret = -EBUSY;
762 break;
763 }
764
765 if (up->port.flags & UPF_IOREMAP) {
766 up->port.membase = ioremap(up->port.mapbase, size);
767 if (!up->port.membase) {
768 release_mem_region(up->port.mapbase, size);
769 ret = -ENOMEM;
770 }
771 }
772 break;
773
774 case UPIO_PORT:
775 if (!request_region(up->port.iobase, size, "serial_txx9"))
776 ret = -EBUSY;
777 break;
778 }
779 return ret;
780}
781
782static void serial_txx9_release_resource(struct uart_txx9_port *up)
783{
784 unsigned int size = TXX9_REGION_SIZE;
785
786 switch (up->port.iotype) {
787 default:
788 if (!up->port.mapbase)
789 break;
790
791 if (up->port.flags & UPF_IOREMAP) {
792 iounmap(up->port.membase);
793 up->port.membase = NULL;
794 }
795
796 release_mem_region(up->port.mapbase, size);
797 break;
798
799 case UPIO_PORT:
800 release_region(up->port.iobase, size);
801 break;
802 }
803}
804
805static void serial_txx9_release_port(struct uart_port *port)
806{
807 struct uart_txx9_port *up = to_uart_txx9_port(port);
808 serial_txx9_release_resource(up);
809}
810
811static int serial_txx9_request_port(struct uart_port *port)
812{
813 struct uart_txx9_port *up = to_uart_txx9_port(port);
814 return serial_txx9_request_resource(up);
815}
816
817static void serial_txx9_config_port(struct uart_port *port, int uflags)
818{
819 struct uart_txx9_port *up = to_uart_txx9_port(port);
820 int ret;
821
822
823
824
825
826 ret = serial_txx9_request_resource(up);
827 if (ret < 0)
828 return;
829 port->type = PORT_TXX9;
830 up->port.fifosize = TXX9_SIO_TX_FIFO;
831
832#ifdef CONFIG_SERIAL_TXX9_CONSOLE
833 if (up->port.line == up->port.cons->index)
834 return;
835#endif
836 serial_txx9_initialize(port);
837}
838
839static const char *
840serial_txx9_type(struct uart_port *port)
841{
842 return "txx9";
843}
844
845static const struct uart_ops serial_txx9_pops = {
846 .tx_empty = serial_txx9_tx_empty,
847 .set_mctrl = serial_txx9_set_mctrl,
848 .get_mctrl = serial_txx9_get_mctrl,
849 .stop_tx = serial_txx9_stop_tx,
850 .start_tx = serial_txx9_start_tx,
851 .stop_rx = serial_txx9_stop_rx,
852 .break_ctl = serial_txx9_break_ctl,
853 .startup = serial_txx9_startup,
854 .shutdown = serial_txx9_shutdown,
855 .set_termios = serial_txx9_set_termios,
856 .pm = serial_txx9_pm,
857 .type = serial_txx9_type,
858 .release_port = serial_txx9_release_port,
859 .request_port = serial_txx9_request_port,
860 .config_port = serial_txx9_config_port,
861#ifdef CONFIG_CONSOLE_POLL
862 .poll_get_char = serial_txx9_get_poll_char,
863 .poll_put_char = serial_txx9_put_poll_char,
864#endif
865};
866
867static struct uart_txx9_port serial_txx9_ports[UART_NR];
868
869static void __init serial_txx9_register_ports(struct uart_driver *drv,
870 struct device *dev)
871{
872 int i;
873
874 for (i = 0; i < UART_NR; i++) {
875 struct uart_txx9_port *up = &serial_txx9_ports[i];
876
877 up->port.line = i;
878 up->port.ops = &serial_txx9_pops;
879 up->port.dev = dev;
880 if (up->port.iobase || up->port.mapbase)
881 uart_add_one_port(drv, &up->port);
882 }
883}
884
885#ifdef CONFIG_SERIAL_TXX9_CONSOLE
886
887static void serial_txx9_console_putchar(struct uart_port *port, int ch)
888{
889 struct uart_txx9_port *up = to_uart_txx9_port(port);
890
891 wait_for_xmitr(up);
892 sio_out(up, TXX9_SITFIFO, ch);
893}
894
895
896
897
898
899
900
901static void
902serial_txx9_console_write(struct console *co, const char *s, unsigned int count)
903{
904 struct uart_txx9_port *up = &serial_txx9_ports[co->index];
905 unsigned int ier, flcr;
906
907
908
909
910 ier = sio_in(up, TXX9_SIDICR);
911 sio_out(up, TXX9_SIDICR, 0);
912
913
914
915 flcr = sio_in(up, TXX9_SIFLCR);
916 if (!(up->port.flags & UPF_CONS_FLOW) && (flcr & TXX9_SIFLCR_TES))
917 sio_out(up, TXX9_SIFLCR, flcr & ~TXX9_SIFLCR_TES);
918
919 uart_console_write(&up->port, s, count, serial_txx9_console_putchar);
920
921
922
923
924
925 wait_for_xmitr(up);
926 sio_out(up, TXX9_SIFLCR, flcr);
927 sio_out(up, TXX9_SIDICR, ier);
928}
929
930static int __init serial_txx9_console_setup(struct console *co, char *options)
931{
932 struct uart_port *port;
933 struct uart_txx9_port *up;
934 int baud = 9600;
935 int bits = 8;
936 int parity = 'n';
937 int flow = 'n';
938
939
940
941
942
943
944 if (co->index >= UART_NR)
945 co->index = 0;
946 up = &serial_txx9_ports[co->index];
947 port = &up->port;
948 if (!port->ops)
949 return -ENODEV;
950
951 serial_txx9_initialize(&up->port);
952
953 if (options)
954 uart_parse_options(options, &baud, &parity, &bits, &flow);
955
956 return uart_set_options(port, co, baud, parity, bits, flow);
957}
958
959static struct uart_driver serial_txx9_reg;
960static struct console serial_txx9_console = {
961 .name = TXX9_TTY_NAME,
962 .write = serial_txx9_console_write,
963 .device = uart_console_device,
964 .setup = serial_txx9_console_setup,
965 .flags = CON_PRINTBUFFER,
966 .index = -1,
967 .data = &serial_txx9_reg,
968};
969
970static int __init serial_txx9_console_init(void)
971{
972 register_console(&serial_txx9_console);
973 return 0;
974}
975console_initcall(serial_txx9_console_init);
976
977#define SERIAL_TXX9_CONSOLE &serial_txx9_console
978#else
979#define SERIAL_TXX9_CONSOLE NULL
980#endif
981
982static struct uart_driver serial_txx9_reg = {
983 .owner = THIS_MODULE,
984 .driver_name = "serial_txx9",
985 .dev_name = TXX9_TTY_NAME,
986 .major = TXX9_TTY_MAJOR,
987 .minor = TXX9_TTY_MINOR_START,
988 .nr = UART_NR,
989 .cons = SERIAL_TXX9_CONSOLE,
990};
991
992int __init early_serial_txx9_setup(struct uart_port *port)
993{
994 if (port->line >= ARRAY_SIZE(serial_txx9_ports))
995 return -ENODEV;
996
997 serial_txx9_ports[port->line].port = *port;
998 serial_txx9_ports[port->line].port.ops = &serial_txx9_pops;
999 serial_txx9_ports[port->line].port.flags |=
1000 UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1001 return 0;
1002}
1003
1004static DEFINE_MUTEX(serial_txx9_mutex);
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017static int serial_txx9_register_port(struct uart_port *port)
1018{
1019 int i;
1020 struct uart_txx9_port *uart;
1021 int ret = -ENOSPC;
1022
1023 mutex_lock(&serial_txx9_mutex);
1024 for (i = 0; i < UART_NR; i++) {
1025 uart = &serial_txx9_ports[i];
1026 if (uart_match_port(&uart->port, port)) {
1027 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1028 break;
1029 }
1030 }
1031 if (i == UART_NR) {
1032
1033 for (i = 0; i < UART_NR; i++) {
1034 uart = &serial_txx9_ports[i];
1035 if (!(uart->port.iobase || uart->port.mapbase))
1036 break;
1037 }
1038 }
1039 if (i < UART_NR) {
1040 uart->port.iobase = port->iobase;
1041 uart->port.membase = port->membase;
1042 uart->port.irq = port->irq;
1043 uart->port.uartclk = port->uartclk;
1044 uart->port.iotype = port->iotype;
1045 uart->port.flags = port->flags
1046 | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
1047 uart->port.mapbase = port->mapbase;
1048 if (port->dev)
1049 uart->port.dev = port->dev;
1050 ret = uart_add_one_port(&serial_txx9_reg, &uart->port);
1051 if (ret == 0)
1052 ret = uart->port.line;
1053 }
1054 mutex_unlock(&serial_txx9_mutex);
1055 return ret;
1056}
1057
1058
1059
1060
1061
1062
1063
1064
1065static void serial_txx9_unregister_port(int line)
1066{
1067 struct uart_txx9_port *uart = &serial_txx9_ports[line];
1068
1069 mutex_lock(&serial_txx9_mutex);
1070 uart_remove_one_port(&serial_txx9_reg, &uart->port);
1071 uart->port.flags = 0;
1072 uart->port.type = PORT_UNKNOWN;
1073 uart->port.iobase = 0;
1074 uart->port.mapbase = 0;
1075 uart->port.membase = NULL;
1076 uart->port.dev = NULL;
1077 mutex_unlock(&serial_txx9_mutex);
1078}
1079
1080
1081
1082
1083static int serial_txx9_probe(struct platform_device *dev)
1084{
1085 struct uart_port *p = dev_get_platdata(&dev->dev);
1086 struct uart_port port;
1087 int ret, i;
1088
1089 memset(&port, 0, sizeof(struct uart_port));
1090 for (i = 0; p && p->uartclk != 0; p++, i++) {
1091 port.iobase = p->iobase;
1092 port.membase = p->membase;
1093 port.irq = p->irq;
1094 port.uartclk = p->uartclk;
1095 port.iotype = p->iotype;
1096 port.flags = p->flags;
1097 port.mapbase = p->mapbase;
1098 port.dev = &dev->dev;
1099 ret = serial_txx9_register_port(&port);
1100 if (ret < 0) {
1101 dev_err(&dev->dev, "unable to register port at index %d "
1102 "(IO%lx MEM%llx IRQ%d): %d\n", i,
1103 p->iobase, (unsigned long long)p->mapbase,
1104 p->irq, ret);
1105 }
1106 }
1107 return 0;
1108}
1109
1110
1111
1112
1113static int serial_txx9_remove(struct platform_device *dev)
1114{
1115 int i;
1116
1117 for (i = 0; i < UART_NR; i++) {
1118 struct uart_txx9_port *up = &serial_txx9_ports[i];
1119
1120 if (up->port.dev == &dev->dev)
1121 serial_txx9_unregister_port(i);
1122 }
1123 return 0;
1124}
1125
1126#ifdef CONFIG_PM
1127static int serial_txx9_suspend(struct platform_device *dev, pm_message_t state)
1128{
1129 int i;
1130
1131 for (i = 0; i < UART_NR; i++) {
1132 struct uart_txx9_port *up = &serial_txx9_ports[i];
1133
1134 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1135 uart_suspend_port(&serial_txx9_reg, &up->port);
1136 }
1137
1138 return 0;
1139}
1140
1141static int serial_txx9_resume(struct platform_device *dev)
1142{
1143 int i;
1144
1145 for (i = 0; i < UART_NR; i++) {
1146 struct uart_txx9_port *up = &serial_txx9_ports[i];
1147
1148 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1149 uart_resume_port(&serial_txx9_reg, &up->port);
1150 }
1151
1152 return 0;
1153}
1154#endif
1155
1156static struct platform_driver serial_txx9_plat_driver = {
1157 .probe = serial_txx9_probe,
1158 .remove = serial_txx9_remove,
1159#ifdef CONFIG_PM
1160 .suspend = serial_txx9_suspend,
1161 .resume = serial_txx9_resume,
1162#endif
1163 .driver = {
1164 .name = "serial_txx9",
1165 },
1166};
1167
1168#ifdef ENABLE_SERIAL_TXX9_PCI
1169
1170
1171
1172
1173static int
1174pciserial_txx9_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1175{
1176 struct uart_port port;
1177 int line;
1178 int rc;
1179
1180 rc = pci_enable_device(dev);
1181 if (rc)
1182 return rc;
1183
1184 memset(&port, 0, sizeof(port));
1185 port.ops = &serial_txx9_pops;
1186 port.flags |= UPF_TXX9_HAVE_CTS_LINE;
1187 port.uartclk = 66670000;
1188 port.irq = dev->irq;
1189 port.iotype = UPIO_PORT;
1190 port.iobase = pci_resource_start(dev, 1);
1191 port.dev = &dev->dev;
1192 line = serial_txx9_register_port(&port);
1193 if (line < 0) {
1194 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), line);
1195 pci_disable_device(dev);
1196 return line;
1197 }
1198 pci_set_drvdata(dev, &serial_txx9_ports[line]);
1199
1200 return 0;
1201}
1202
1203static void pciserial_txx9_remove_one(struct pci_dev *dev)
1204{
1205 struct uart_txx9_port *up = pci_get_drvdata(dev);
1206
1207 if (up) {
1208 serial_txx9_unregister_port(up->port.line);
1209 pci_disable_device(dev);
1210 }
1211}
1212
1213#ifdef CONFIG_PM
1214static int pciserial_txx9_suspend_one(struct pci_dev *dev, pm_message_t state)
1215{
1216 struct uart_txx9_port *up = pci_get_drvdata(dev);
1217
1218 if (up)
1219 uart_suspend_port(&serial_txx9_reg, &up->port);
1220 pci_save_state(dev);
1221 pci_set_power_state(dev, pci_choose_state(dev, state));
1222 return 0;
1223}
1224
1225static int pciserial_txx9_resume_one(struct pci_dev *dev)
1226{
1227 struct uart_txx9_port *up = pci_get_drvdata(dev);
1228
1229 pci_set_power_state(dev, PCI_D0);
1230 pci_restore_state(dev);
1231 if (up)
1232 uart_resume_port(&serial_txx9_reg, &up->port);
1233 return 0;
1234}
1235#endif
1236
1237static const struct pci_device_id serial_txx9_pci_tbl[] = {
1238 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC) },
1239 { 0, }
1240};
1241
1242static struct pci_driver serial_txx9_pci_driver = {
1243 .name = "serial_txx9",
1244 .probe = pciserial_txx9_init_one,
1245 .remove = pciserial_txx9_remove_one,
1246#ifdef CONFIG_PM
1247 .suspend = pciserial_txx9_suspend_one,
1248 .resume = pciserial_txx9_resume_one,
1249#endif
1250 .id_table = serial_txx9_pci_tbl,
1251};
1252
1253MODULE_DEVICE_TABLE(pci, serial_txx9_pci_tbl);
1254#endif
1255
1256static struct platform_device *serial_txx9_plat_devs;
1257
1258static int __init serial_txx9_init(void)
1259{
1260 int ret;
1261
1262 printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
1263
1264 ret = uart_register_driver(&serial_txx9_reg);
1265 if (ret)
1266 goto out;
1267
1268 serial_txx9_plat_devs = platform_device_alloc("serial_txx9", -1);
1269 if (!serial_txx9_plat_devs) {
1270 ret = -ENOMEM;
1271 goto unreg_uart_drv;
1272 }
1273
1274 ret = platform_device_add(serial_txx9_plat_devs);
1275 if (ret)
1276 goto put_dev;
1277
1278 serial_txx9_register_ports(&serial_txx9_reg,
1279 &serial_txx9_plat_devs->dev);
1280
1281 ret = platform_driver_register(&serial_txx9_plat_driver);
1282 if (ret)
1283 goto del_dev;
1284
1285#ifdef ENABLE_SERIAL_TXX9_PCI
1286 ret = pci_register_driver(&serial_txx9_pci_driver);
1287#endif
1288 if (ret == 0)
1289 goto out;
1290
1291 del_dev:
1292 platform_device_del(serial_txx9_plat_devs);
1293 put_dev:
1294 platform_device_put(serial_txx9_plat_devs);
1295 unreg_uart_drv:
1296 uart_unregister_driver(&serial_txx9_reg);
1297 out:
1298 return ret;
1299}
1300
1301static void __exit serial_txx9_exit(void)
1302{
1303 int i;
1304
1305#ifdef ENABLE_SERIAL_TXX9_PCI
1306 pci_unregister_driver(&serial_txx9_pci_driver);
1307#endif
1308 platform_driver_unregister(&serial_txx9_plat_driver);
1309 platform_device_unregister(serial_txx9_plat_devs);
1310 for (i = 0; i < UART_NR; i++) {
1311 struct uart_txx9_port *up = &serial_txx9_ports[i];
1312 if (up->port.iobase || up->port.mapbase)
1313 uart_remove_one_port(&serial_txx9_reg, &up->port);
1314 }
1315
1316 uart_unregister_driver(&serial_txx9_reg);
1317}
1318
1319module_init(serial_txx9_init);
1320module_exit(serial_txx9_exit);
1321
1322MODULE_LICENSE("GPL");
1323MODULE_DESCRIPTION("TX39/49 serial driver");
1324
1325MODULE_ALIAS_CHARDEV_MAJOR(TXX9_TTY_MAJOR);
1326
