linux/drivers/usb/host/xhci-ring.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * xHCI host controller driver
   4 *
   5 * Copyright (C) 2008 Intel Corp.
   6 *
   7 * Author: Sarah Sharp
   8 * Some code borrowed from the Linux EHCI driver.
   9 */
  10
  11/*
  12 * Ring initialization rules:
  13 * 1. Each segment is initialized to zero, except for link TRBs.
  14 * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  15 *    Consumer Cycle State (CCS), depending on ring function.
  16 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  17 *
  18 * Ring behavior rules:
  19 * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  20 *    least one free TRB in the ring.  This is useful if you want to turn that
  21 *    into a link TRB and expand the ring.
  22 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  23 *    link TRB, then load the pointer with the address in the link TRB.  If the
  24 *    link TRB had its toggle bit set, you may need to update the ring cycle
  25 *    state (see cycle bit rules).  You may have to do this multiple times
  26 *    until you reach a non-link TRB.
  27 * 3. A ring is full if enqueue++ (for the definition of increment above)
  28 *    equals the dequeue pointer.
  29 *
  30 * Cycle bit rules:
  31 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  32 *    in a link TRB, it must toggle the ring cycle state.
  33 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  34 *    in a link TRB, it must toggle the ring cycle state.
  35 *
  36 * Producer rules:
  37 * 1. Check if ring is full before you enqueue.
  38 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  39 *    Update enqueue pointer between each write (which may update the ring
  40 *    cycle state).
  41 * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  42 *    and endpoint rings.  If HC is the producer for the event ring,
  43 *    and it generates an interrupt according to interrupt modulation rules.
  44 *
  45 * Consumer rules:
  46 * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  47 *    the TRB is owned by the consumer.
  48 * 2. Update dequeue pointer (which may update the ring cycle state) and
  49 *    continue processing TRBs until you reach a TRB which is not owned by you.
  50 * 3. Notify the producer.  SW is the consumer for the event ring, and it
  51 *   updates event ring dequeue pointer.  HC is the consumer for the command and
  52 *   endpoint rings; it generates events on the event ring for these.
  53 */
  54
  55#include <linux/scatterlist.h>
  56#include <linux/slab.h>
  57#include <linux/dma-mapping.h>
  58#include "xhci.h"
  59#include "xhci-trace.h"
  60#include "xhci-mtk.h"
  61
  62/*
  63 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  64 * address of the TRB.
  65 */
  66dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  67                union xhci_trb *trb)
  68{
  69        unsigned long segment_offset;
  70
  71        if (!seg || !trb || trb < seg->trbs)
  72                return 0;
  73        /* offset in TRBs */
  74        segment_offset = trb - seg->trbs;
  75        if (segment_offset >= TRBS_PER_SEGMENT)
  76                return 0;
  77        return seg->dma + (segment_offset * sizeof(*trb));
  78}
  79
  80static bool trb_is_noop(union xhci_trb *trb)
  81{
  82        return TRB_TYPE_NOOP_LE32(trb->generic.field[3]);
  83}
  84
  85static bool trb_is_link(union xhci_trb *trb)
  86{
  87        return TRB_TYPE_LINK_LE32(trb->link.control);
  88}
  89
  90static bool last_trb_on_seg(struct xhci_segment *seg, union xhci_trb *trb)
  91{
  92        return trb == &seg->trbs[TRBS_PER_SEGMENT - 1];
  93}
  94
  95static bool last_trb_on_ring(struct xhci_ring *ring,
  96                        struct xhci_segment *seg, union xhci_trb *trb)
  97{
  98        return last_trb_on_seg(seg, trb) && (seg->next == ring->first_seg);
  99}
 100
 101static bool link_trb_toggles_cycle(union xhci_trb *trb)
 102{
 103        return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104}
 105
 106static bool last_td_in_urb(struct xhci_td *td)
 107{
 108        struct urb_priv *urb_priv = td->urb->hcpriv;
 109
 110        return urb_priv->num_tds_done == urb_priv->num_tds;
 111}
 112
 113static void inc_td_cnt(struct urb *urb)
 114{
 115        struct urb_priv *urb_priv = urb->hcpriv;
 116
 117        urb_priv->num_tds_done++;
 118}
 119
 120static void trb_to_noop(union xhci_trb *trb, u32 noop_type)
 121{
 122        if (trb_is_link(trb)) {
 123                /* unchain chained link TRBs */
 124                trb->link.control &= cpu_to_le32(~TRB_CHAIN);
 125        } else {
 126                trb->generic.field[0] = 0;
 127                trb->generic.field[1] = 0;
 128                trb->generic.field[2] = 0;
 129                /* Preserve only the cycle bit of this TRB */
 130                trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 131                trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(noop_type));
 132        }
 133}
 134
 135/* Updates trb to point to the next TRB in the ring, and updates seg if the next
 136 * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 137 * effect the ring dequeue or enqueue pointers.
 138 */
 139static void next_trb(struct xhci_hcd *xhci,
 140                struct xhci_ring *ring,
 141                struct xhci_segment **seg,
 142                union xhci_trb **trb)
 143{
 144        if (trb_is_link(*trb)) {
 145                *seg = (*seg)->next;
 146                *trb = ((*seg)->trbs);
 147        } else {
 148                (*trb)++;
 149        }
 150}
 151
 152/*
 153 * See Cycle bit rules. SW is the consumer for the event ring only.
 154 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 155 */
 156void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 157{
 158        /* event ring doesn't have link trbs, check for last trb */
 159        if (ring->type == TYPE_EVENT) {
 160                if (!last_trb_on_seg(ring->deq_seg, ring->dequeue)) {
 161                        ring->dequeue++;
 162                        goto out;
 163                }
 164                if (last_trb_on_ring(ring, ring->deq_seg, ring->dequeue))
 165                        ring->cycle_state ^= 1;
 166                ring->deq_seg = ring->deq_seg->next;
 167                ring->dequeue = ring->deq_seg->trbs;
 168                goto out;
 169        }
 170
 171        /* All other rings have link trbs */
 172        if (!trb_is_link(ring->dequeue)) {
 173                ring->dequeue++;
 174                ring->num_trbs_free++;
 175        }
 176        while (trb_is_link(ring->dequeue)) {
 177                ring->deq_seg = ring->deq_seg->next;
 178                ring->dequeue = ring->deq_seg->trbs;
 179        }
 180
 181out:
 182        trace_xhci_inc_deq(ring);
 183
 184        return;
 185}
 186
 187/*
 188 * See Cycle bit rules. SW is the consumer for the event ring only.
 189 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 190 *
 191 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 192 * chain bit is set), then set the chain bit in all the following link TRBs.
 193 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 194 * have their chain bit cleared (so that each Link TRB is a separate TD).
 195 *
 196 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 197 * set, but other sections talk about dealing with the chain bit set.  This was
 198 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 199 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 200 *
 201 * @more_trbs_coming:   Will you enqueue more TRBs before calling
 202 *                      prepare_transfer()?
 203 */
 204static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 205                        bool more_trbs_coming)
 206{
 207        u32 chain;
 208        union xhci_trb *next;
 209
 210        chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 211        /* If this is not event ring, there is one less usable TRB */
 212        if (!trb_is_link(ring->enqueue))
 213                ring->num_trbs_free--;
 214        next = ++(ring->enqueue);
 215
 216        /* Update the dequeue pointer further if that was a link TRB */
 217        while (trb_is_link(next)) {
 218
 219                /*
 220                 * If the caller doesn't plan on enqueueing more TDs before
 221                 * ringing the doorbell, then we don't want to give the link TRB
 222                 * to the hardware just yet. We'll give the link TRB back in
 223                 * prepare_ring() just before we enqueue the TD at the top of
 224                 * the ring.
 225                 */
 226                if (!chain && !more_trbs_coming)
 227                        break;
 228
 229                /* If we're not dealing with 0.95 hardware or isoc rings on
 230                 * AMD 0.96 host, carry over the chain bit of the previous TRB
 231                 * (which may mean the chain bit is cleared).
 232                 */
 233                if (!(ring->type == TYPE_ISOC &&
 234                      (xhci->quirks & XHCI_AMD_0x96_HOST)) &&
 235                    !xhci_link_trb_quirk(xhci)) {
 236                        next->link.control &= cpu_to_le32(~TRB_CHAIN);
 237                        next->link.control |= cpu_to_le32(chain);
 238                }
 239                /* Give this link TRB to the hardware */
 240                wmb();
 241                next->link.control ^= cpu_to_le32(TRB_CYCLE);
 242
 243                /* Toggle the cycle bit after the last ring segment. */
 244                if (link_trb_toggles_cycle(next))
 245                        ring->cycle_state ^= 1;
 246
 247                ring->enq_seg = ring->enq_seg->next;
 248                ring->enqueue = ring->enq_seg->trbs;
 249                next = ring->enqueue;
 250        }
 251
 252        trace_xhci_inc_enq(ring);
 253}
 254
 255/*
 256 * Check to see if there's room to enqueue num_trbs on the ring and make sure
 257 * enqueue pointer will not advance into dequeue segment. See rules above.
 258 */
 259static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 260                unsigned int num_trbs)
 261{
 262        int num_trbs_in_deq_seg;
 263
 264        if (ring->num_trbs_free < num_trbs)
 265                return 0;
 266
 267        if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 268                num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 269                if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 270                        return 0;
 271        }
 272
 273        return 1;
 274}
 275
 276/* Ring the host controller doorbell after placing a command on the ring */
 277void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 278{
 279        if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 280                return;
 281
 282        xhci_dbg(xhci, "// Ding dong!\n");
 283        writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 284        /* Flush PCI posted writes */
 285        readl(&xhci->dba->doorbell[0]);
 286}
 287
 288static bool xhci_mod_cmd_timer(struct xhci_hcd *xhci, unsigned long delay)
 289{
 290        return mod_delayed_work(system_wq, &xhci->cmd_timer, delay);
 291}
 292
 293static struct xhci_command *xhci_next_queued_cmd(struct xhci_hcd *xhci)
 294{
 295        return list_first_entry_or_null(&xhci->cmd_list, struct xhci_command,
 296                                        cmd_list);
 297}
 298
 299/*
 300 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
 301 * If there are other commands waiting then restart the ring and kick the timer.
 302 * This must be called with command ring stopped and xhci->lock held.
 303 */
 304static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
 305                                         struct xhci_command *cur_cmd)
 306{
 307        struct xhci_command *i_cmd;
 308
 309        /* Turn all aborted commands in list to no-ops, then restart */
 310        list_for_each_entry(i_cmd, &xhci->cmd_list, cmd_list) {
 311
 312                if (i_cmd->status != COMP_COMMAND_ABORTED)
 313                        continue;
 314
 315                i_cmd->status = COMP_COMMAND_RING_STOPPED;
 316
 317                xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
 318                         i_cmd->command_trb);
 319
 320                trb_to_noop(i_cmd->command_trb, TRB_CMD_NOOP);
 321
 322                /*
 323                 * caller waiting for completion is called when command
 324                 *  completion event is received for these no-op commands
 325                 */
 326        }
 327
 328        xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
 329
 330        /* ring command ring doorbell to restart the command ring */
 331        if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
 332            !(xhci->xhc_state & XHCI_STATE_DYING)) {
 333                xhci->current_cmd = cur_cmd;
 334                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
 335                xhci_ring_cmd_db(xhci);
 336        }
 337}
 338
 339/* Must be called with xhci->lock held, releases and aquires lock back */
 340static int xhci_abort_cmd_ring(struct xhci_hcd *xhci, unsigned long flags)
 341{
 342        u64 temp_64;
 343        int ret;
 344
 345        xhci_dbg(xhci, "Abort command ring\n");
 346
 347        reinit_completion(&xhci->cmd_ring_stop_completion);
 348
 349        temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 350        xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 351                        &xhci->op_regs->cmd_ring);
 352
 353        /* Section 4.6.1.2 of xHCI 1.0 spec says software should also time the
 354         * completion of the Command Abort operation. If CRR is not negated in 5
 355         * seconds then driver handles it as if host died (-ENODEV).
 356         * In the future we should distinguish between -ENODEV and -ETIMEDOUT
 357         * and try to recover a -ETIMEDOUT with a host controller reset.
 358         */
 359        ret = xhci_handshake(&xhci->op_regs->cmd_ring,
 360                        CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 361        if (ret < 0) {
 362                xhci_err(xhci, "Abort failed to stop command ring: %d\n", ret);
 363                xhci_halt(xhci);
 364                xhci_hc_died(xhci);
 365                return ret;
 366        }
 367        /*
 368         * Writing the CMD_RING_ABORT bit should cause a cmd completion event,
 369         * however on some host hw the CMD_RING_RUNNING bit is correctly cleared
 370         * but the completion event in never sent. Wait 2 secs (arbitrary
 371         * number) to handle those cases after negation of CMD_RING_RUNNING.
 372         */
 373        spin_unlock_irqrestore(&xhci->lock, flags);
 374        ret = wait_for_completion_timeout(&xhci->cmd_ring_stop_completion,
 375                                          msecs_to_jiffies(2000));
 376        spin_lock_irqsave(&xhci->lock, flags);
 377        if (!ret) {
 378                xhci_dbg(xhci, "No stop event for abort, ring start fail?\n");
 379                xhci_cleanup_command_queue(xhci);
 380        } else {
 381                xhci_handle_stopped_cmd_ring(xhci, xhci_next_queued_cmd(xhci));
 382        }
 383        return 0;
 384}
 385
 386void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 387                unsigned int slot_id,
 388                unsigned int ep_index,
 389                unsigned int stream_id)
 390{
 391        __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 392        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 393        unsigned int ep_state = ep->ep_state;
 394
 395        /* Don't ring the doorbell for this endpoint if there are pending
 396         * cancellations because we don't want to interrupt processing.
 397         * We don't want to restart any stream rings if there's a set dequeue
 398         * pointer command pending because the device can choose to start any
 399         * stream once the endpoint is on the HW schedule.
 400         */
 401        if ((ep_state & EP_STOP_CMD_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 402            (ep_state & EP_HALTED))
 403                return;
 404        writel(DB_VALUE(ep_index, stream_id), db_addr);
 405        /* The CPU has better things to do at this point than wait for a
 406         * write-posting flush.  It'll get there soon enough.
 407         */
 408}
 409
 410/* Ring the doorbell for any rings with pending URBs */
 411static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 412                unsigned int slot_id,
 413                unsigned int ep_index)
 414{
 415        unsigned int stream_id;
 416        struct xhci_virt_ep *ep;
 417
 418        ep = &xhci->devs[slot_id]->eps[ep_index];
 419
 420        /* A ring has pending URBs if its TD list is not empty */
 421        if (!(ep->ep_state & EP_HAS_STREAMS)) {
 422                if (ep->ring && !(list_empty(&ep->ring->td_list)))
 423                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 424                return;
 425        }
 426
 427        for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 428                        stream_id++) {
 429                struct xhci_stream_info *stream_info = ep->stream_info;
 430                if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 431                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 432                                                stream_id);
 433        }
 434}
 435
 436/* Get the right ring for the given slot_id, ep_index and stream_id.
 437 * If the endpoint supports streams, boundary check the URB's stream ID.
 438 * If the endpoint doesn't support streams, return the singular endpoint ring.
 439 */
 440struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 441                unsigned int slot_id, unsigned int ep_index,
 442                unsigned int stream_id)
 443{
 444        struct xhci_virt_ep *ep;
 445
 446        ep = &xhci->devs[slot_id]->eps[ep_index];
 447        /* Common case: no streams */
 448        if (!(ep->ep_state & EP_HAS_STREAMS))
 449                return ep->ring;
 450
 451        if (stream_id == 0) {
 452                xhci_warn(xhci,
 453                                "WARN: Slot ID %u, ep index %u has streams, "
 454                                "but URB has no stream ID.\n",
 455                                slot_id, ep_index);
 456                return NULL;
 457        }
 458
 459        if (stream_id < ep->stream_info->num_streams)
 460                return ep->stream_info->stream_rings[stream_id];
 461
 462        xhci_warn(xhci,
 463                        "WARN: Slot ID %u, ep index %u has "
 464                        "stream IDs 1 to %u allocated, "
 465                        "but stream ID %u is requested.\n",
 466                        slot_id, ep_index,
 467                        ep->stream_info->num_streams - 1,
 468                        stream_id);
 469        return NULL;
 470}
 471
 472
 473/*
 474 * Get the hw dequeue pointer xHC stopped on, either directly from the
 475 * endpoint context, or if streams are in use from the stream context.
 476 * The returned hw_dequeue contains the lowest four bits with cycle state
 477 * and possbile stream context type.
 478 */
 479static u64 xhci_get_hw_deq(struct xhci_hcd *xhci, struct xhci_virt_device *vdev,
 480                           unsigned int ep_index, unsigned int stream_id)
 481{
 482        struct xhci_ep_ctx *ep_ctx;
 483        struct xhci_stream_ctx *st_ctx;
 484        struct xhci_virt_ep *ep;
 485
 486        ep = &vdev->eps[ep_index];
 487
 488        if (ep->ep_state & EP_HAS_STREAMS) {
 489                st_ctx = &ep->stream_info->stream_ctx_array[stream_id];
 490                return le64_to_cpu(st_ctx->stream_ring);
 491        }
 492        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 493        return le64_to_cpu(ep_ctx->deq);
 494}
 495
 496/*
 497 * Move the xHC's endpoint ring dequeue pointer past cur_td.
 498 * Record the new state of the xHC's endpoint ring dequeue segment,
 499 * dequeue pointer, stream id, and new consumer cycle state in state.
 500 * Update our internal representation of the ring's dequeue pointer.
 501 *
 502 * We do this in three jumps:
 503 *  - First we update our new ring state to be the same as when the xHC stopped.
 504 *  - Then we traverse the ring to find the segment that contains
 505 *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 506 *    any link TRBs with the toggle cycle bit set.
 507 *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 508 *    if we've moved it past a link TRB with the toggle cycle bit set.
 509 *
 510 * Some of the uses of xhci_generic_trb are grotty, but if they're done
 511 * with correct __le32 accesses they should work fine.  Only users of this are
 512 * in here.
 513 */
 514void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 515                unsigned int slot_id, unsigned int ep_index,
 516                unsigned int stream_id, struct xhci_td *cur_td,
 517                struct xhci_dequeue_state *state)
 518{
 519        struct xhci_virt_device *dev = xhci->devs[slot_id];
 520        struct xhci_virt_ep *ep = &dev->eps[ep_index];
 521        struct xhci_ring *ep_ring;
 522        struct xhci_segment *new_seg;
 523        union xhci_trb *new_deq;
 524        dma_addr_t addr;
 525        u64 hw_dequeue;
 526        bool cycle_found = false;
 527        bool td_last_trb_found = false;
 528
 529        ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 530                        ep_index, stream_id);
 531        if (!ep_ring) {
 532                xhci_warn(xhci, "WARN can't find new dequeue state "
 533                                "for invalid stream ID %u.\n",
 534                                stream_id);
 535                return;
 536        }
 537        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 538        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 539                        "Finding endpoint context");
 540
 541        hw_dequeue = xhci_get_hw_deq(xhci, dev, ep_index, stream_id);
 542        new_seg = ep_ring->deq_seg;
 543        new_deq = ep_ring->dequeue;
 544        state->new_cycle_state = hw_dequeue & 0x1;
 545        state->stream_id = stream_id;
 546
 547        /*
 548         * We want to find the pointer, segment and cycle state of the new trb
 549         * (the one after current TD's last_trb). We know the cycle state at
 550         * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 551         * found.
 552         */
 553        do {
 554                if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 555                    == (dma_addr_t)(hw_dequeue & ~0xf)) {
 556                        cycle_found = true;
 557                        if (td_last_trb_found)
 558                                break;
 559                }
 560                if (new_deq == cur_td->last_trb)
 561                        td_last_trb_found = true;
 562
 563                if (cycle_found && trb_is_link(new_deq) &&
 564                    link_trb_toggles_cycle(new_deq))
 565                        state->new_cycle_state ^= 0x1;
 566
 567                next_trb(xhci, ep_ring, &new_seg, &new_deq);
 568
 569                /* Search wrapped around, bail out */
 570                if (new_deq == ep->ring->dequeue) {
 571                        xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 572                        state->new_deq_seg = NULL;
 573                        state->new_deq_ptr = NULL;
 574                        return;
 575                }
 576
 577        } while (!cycle_found || !td_last_trb_found);
 578
 579        state->new_deq_seg = new_seg;
 580        state->new_deq_ptr = new_deq;
 581
 582        /* Don't update the ring cycle state for the producer (us). */
 583        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 584                        "Cycle state = 0x%x", state->new_cycle_state);
 585
 586        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 587                        "New dequeue segment = %p (virtual)",
 588                        state->new_deq_seg);
 589        addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 590        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 591                        "New dequeue pointer = 0x%llx (DMA)",
 592                        (unsigned long long) addr);
 593}
 594
 595/* flip_cycle means flip the cycle bit of all but the first and last TRB.
 596 * (The last TRB actually points to the ring enqueue pointer, which is not part
 597 * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 598 */
 599static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 600                       struct xhci_td *td, bool flip_cycle)
 601{
 602        struct xhci_segment *seg        = td->start_seg;
 603        union xhci_trb *trb             = td->first_trb;
 604
 605        while (1) {
 606                trb_to_noop(trb, TRB_TR_NOOP);
 607
 608                /* flip cycle if asked to */
 609                if (flip_cycle && trb != td->first_trb && trb != td->last_trb)
 610                        trb->generic.field[3] ^= cpu_to_le32(TRB_CYCLE);
 611
 612                if (trb == td->last_trb)
 613                        break;
 614
 615                next_trb(xhci, ep_ring, &seg, &trb);
 616        }
 617}
 618
 619static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 620                struct xhci_virt_ep *ep)
 621{
 622        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 623        /* Can't del_timer_sync in interrupt */
 624        del_timer(&ep->stop_cmd_timer);
 625}
 626
 627/*
 628 * Must be called with xhci->lock held in interrupt context,
 629 * releases and re-acquires xhci->lock
 630 */
 631static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 632                                     struct xhci_td *cur_td, int status)
 633{
 634        struct urb      *urb            = cur_td->urb;
 635        struct urb_priv *urb_priv       = urb->hcpriv;
 636        struct usb_hcd  *hcd            = bus_to_hcd(urb->dev->bus);
 637
 638        if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 639                xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 640                if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 641                        if (xhci->quirks & XHCI_AMD_PLL_FIX)
 642                                usb_amd_quirk_pll_enable();
 643                }
 644        }
 645        xhci_urb_free_priv(urb_priv);
 646        usb_hcd_unlink_urb_from_ep(hcd, urb);
 647        spin_unlock(&xhci->lock);
 648        trace_xhci_urb_giveback(urb);
 649        usb_hcd_giveback_urb(hcd, urb, status);
 650        spin_lock(&xhci->lock);
 651}
 652
 653static void xhci_unmap_td_bounce_buffer(struct xhci_hcd *xhci,
 654                struct xhci_ring *ring, struct xhci_td *td)
 655{
 656        struct device *dev = xhci_to_hcd(xhci)->self.controller;
 657        struct xhci_segment *seg = td->bounce_seg;
 658        struct urb *urb = td->urb;
 659
 660        if (!ring || !seg || !urb)
 661                return;
 662
 663        if (usb_urb_dir_out(urb)) {
 664                dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 665                                 DMA_TO_DEVICE);
 666                return;
 667        }
 668
 669        /* for in tranfers we need to copy the data from bounce to sg */
 670        sg_pcopy_from_buffer(urb->sg, urb->num_mapped_sgs, seg->bounce_buf,
 671                             seg->bounce_len, seg->bounce_offs);
 672        dma_unmap_single(dev, seg->bounce_dma, ring->bounce_buf_len,
 673                         DMA_FROM_DEVICE);
 674        seg->bounce_len = 0;
 675        seg->bounce_offs = 0;
 676}
 677
 678/*
 679 * When we get a command completion for a Stop Endpoint Command, we need to
 680 * unlink any cancelled TDs from the ring.  There are two ways to do that:
 681 *
 682 *  1. If the HW was in the middle of processing the TD that needs to be
 683 *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 684 *     in the TD with a Set Dequeue Pointer Command.
 685 *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 686 *     bit cleared) so that the HW will skip over them.
 687 */
 688static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
 689                union xhci_trb *trb, struct xhci_event_cmd *event)
 690{
 691        unsigned int ep_index;
 692        struct xhci_ring *ep_ring;
 693        struct xhci_virt_ep *ep;
 694        struct xhci_td *cur_td = NULL;
 695        struct xhci_td *last_unlinked_td;
 696        struct xhci_ep_ctx *ep_ctx;
 697        struct xhci_virt_device *vdev;
 698        u64 hw_deq;
 699        struct xhci_dequeue_state deq_state;
 700
 701        if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
 702                if (!xhci->devs[slot_id])
 703                        xhci_warn(xhci, "Stop endpoint command "
 704                                "completion for disabled slot %u\n",
 705                                slot_id);
 706                return;
 707        }
 708
 709        memset(&deq_state, 0, sizeof(deq_state));
 710        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 711
 712        vdev = xhci->devs[slot_id];
 713        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
 714        trace_xhci_handle_cmd_stop_ep(ep_ctx);
 715
 716        ep = &xhci->devs[slot_id]->eps[ep_index];
 717        last_unlinked_td = list_last_entry(&ep->cancelled_td_list,
 718                        struct xhci_td, cancelled_td_list);
 719
 720        if (list_empty(&ep->cancelled_td_list)) {
 721                xhci_stop_watchdog_timer_in_irq(xhci, ep);
 722                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 723                return;
 724        }
 725
 726        /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 727         * We have the xHCI lock, so nothing can modify this list until we drop
 728         * it.  We're also in the event handler, so we can't get re-interrupted
 729         * if another Stop Endpoint command completes
 730         */
 731        list_for_each_entry(cur_td, &ep->cancelled_td_list, cancelled_td_list) {
 732                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 733                                "Removing canceled TD starting at 0x%llx (dma).",
 734                                (unsigned long long)xhci_trb_virt_to_dma(
 735                                        cur_td->start_seg, cur_td->first_trb));
 736                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 737                if (!ep_ring) {
 738                        /* This shouldn't happen unless a driver is mucking
 739                         * with the stream ID after submission.  This will
 740                         * leave the TD on the hardware ring, and the hardware
 741                         * will try to execute it, and may access a buffer
 742                         * that has already been freed.  In the best case, the
 743                         * hardware will execute it, and the event handler will
 744                         * ignore the completion event for that TD, since it was
 745                         * removed from the td_list for that endpoint.  In
 746                         * short, don't muck with the stream ID after
 747                         * submission.
 748                         */
 749                        xhci_warn(xhci, "WARN Cancelled URB %p "
 750                                        "has invalid stream ID %u.\n",
 751                                        cur_td->urb,
 752                                        cur_td->urb->stream_id);
 753                        goto remove_finished_td;
 754                }
 755                /*
 756                 * If we stopped on the TD we need to cancel, then we have to
 757                 * move the xHC endpoint ring dequeue pointer past this TD.
 758                 */
 759                hw_deq = xhci_get_hw_deq(xhci, vdev, ep_index,
 760                                         cur_td->urb->stream_id);
 761                hw_deq &= ~0xf;
 762
 763                if (trb_in_td(xhci, cur_td->start_seg, cur_td->first_trb,
 764                              cur_td->last_trb, hw_deq, false)) {
 765                        xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 766                                                    cur_td->urb->stream_id,
 767                                                    cur_td, &deq_state);
 768                } else {
 769                        td_to_noop(xhci, ep_ring, cur_td, false);
 770                }
 771
 772remove_finished_td:
 773                /*
 774                 * The event handler won't see a completion for this TD anymore,
 775                 * so remove it from the endpoint ring's TD list.  Keep it in
 776                 * the cancelled TD list for URB completion later.
 777                 */
 778                list_del_init(&cur_td->td_list);
 779        }
 780
 781        xhci_stop_watchdog_timer_in_irq(xhci, ep);
 782
 783        /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 784        if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 785                xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
 786                                             &deq_state);
 787                xhci_ring_cmd_db(xhci);
 788        } else {
 789                /* Otherwise ring the doorbell(s) to restart queued transfers */
 790                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 791        }
 792
 793        /*
 794         * Drop the lock and complete the URBs in the cancelled TD list.
 795         * New TDs to be cancelled might be added to the end of the list before
 796         * we can complete all the URBs for the TDs we already unlinked.
 797         * So stop when we've completed the URB for the last TD we unlinked.
 798         */
 799        do {
 800                cur_td = list_first_entry(&ep->cancelled_td_list,
 801                                struct xhci_td, cancelled_td_list);
 802                list_del_init(&cur_td->cancelled_td_list);
 803
 804                /* Clean up the cancelled URB */
 805                /* Doesn't matter what we pass for status, since the core will
 806                 * just overwrite it (because the URB has been unlinked).
 807                 */
 808                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 809                xhci_unmap_td_bounce_buffer(xhci, ep_ring, cur_td);
 810                inc_td_cnt(cur_td->urb);
 811                if (last_td_in_urb(cur_td))
 812                        xhci_giveback_urb_in_irq(xhci, cur_td, 0);
 813
 814                /* Stop processing the cancelled list if the watchdog timer is
 815                 * running.
 816                 */
 817                if (xhci->xhc_state & XHCI_STATE_DYING)
 818                        return;
 819        } while (cur_td != last_unlinked_td);
 820
 821        /* Return to the event handler with xhci->lock re-acquired */
 822}
 823
 824static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
 825{
 826        struct xhci_td *cur_td;
 827        struct xhci_td *tmp;
 828
 829        list_for_each_entry_safe(cur_td, tmp, &ring->td_list, td_list) {
 830                list_del_init(&cur_td->td_list);
 831
 832                if (!list_empty(&cur_td->cancelled_td_list))
 833                        list_del_init(&cur_td->cancelled_td_list);
 834
 835                xhci_unmap_td_bounce_buffer(xhci, ring, cur_td);
 836
 837                inc_td_cnt(cur_td->urb);
 838                if (last_td_in_urb(cur_td))
 839                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 840        }
 841}
 842
 843static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
 844                int slot_id, int ep_index)
 845{
 846        struct xhci_td *cur_td;
 847        struct xhci_td *tmp;
 848        struct xhci_virt_ep *ep;
 849        struct xhci_ring *ring;
 850
 851        ep = &xhci->devs[slot_id]->eps[ep_index];
 852        if ((ep->ep_state & EP_HAS_STREAMS) ||
 853                        (ep->ep_state & EP_GETTING_NO_STREAMS)) {
 854                int stream_id;
 855
 856                for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 857                                stream_id++) {
 858                        ring = ep->stream_info->stream_rings[stream_id];
 859                        if (!ring)
 860                                continue;
 861
 862                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 863                                        "Killing URBs for slot ID %u, ep index %u, stream %u",
 864                                        slot_id, ep_index, stream_id);
 865                        xhci_kill_ring_urbs(xhci, ring);
 866                }
 867        } else {
 868                ring = ep->ring;
 869                if (!ring)
 870                        return;
 871                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 872                                "Killing URBs for slot ID %u, ep index %u",
 873                                slot_id, ep_index);
 874                xhci_kill_ring_urbs(xhci, ring);
 875        }
 876
 877        list_for_each_entry_safe(cur_td, tmp, &ep->cancelled_td_list,
 878                        cancelled_td_list) {
 879                list_del_init(&cur_td->cancelled_td_list);
 880                inc_td_cnt(cur_td->urb);
 881
 882                if (last_td_in_urb(cur_td))
 883                        xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
 884        }
 885}
 886
 887/*
 888 * host controller died, register read returns 0xffffffff
 889 * Complete pending commands, mark them ABORTED.
 890 * URBs need to be given back as usb core might be waiting with device locks
 891 * held for the URBs to finish during device disconnect, blocking host remove.
 892 *
 893 * Call with xhci->lock held.
 894 * lock is relased and re-acquired while giving back urb.
 895 */
 896void xhci_hc_died(struct xhci_hcd *xhci)
 897{
 898        int i, j;
 899
 900        if (xhci->xhc_state & XHCI_STATE_DYING)
 901                return;
 902
 903        xhci_err(xhci, "xHCI host controller not responding, assume dead\n");
 904        xhci->xhc_state |= XHCI_STATE_DYING;
 905
 906        xhci_cleanup_command_queue(xhci);
 907
 908        /* return any pending urbs, remove may be waiting for them */
 909        for (i = 0; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
 910                if (!xhci->devs[i])
 911                        continue;
 912                for (j = 0; j < 31; j++)
 913                        xhci_kill_endpoint_urbs(xhci, i, j);
 914        }
 915
 916        /* inform usb core hc died if PCI remove isn't already handling it */
 917        if (!(xhci->xhc_state & XHCI_STATE_REMOVING))
 918                usb_hc_died(xhci_to_hcd(xhci));
 919}
 920
 921/* Watchdog timer function for when a stop endpoint command fails to complete.
 922 * In this case, we assume the host controller is broken or dying or dead.  The
 923 * host may still be completing some other events, so we have to be careful to
 924 * let the event ring handler and the URB dequeueing/enqueueing functions know
 925 * through xhci->state.
 926 *
 927 * The timer may also fire if the host takes a very long time to respond to the
 928 * command, and the stop endpoint command completion handler cannot delete the
 929 * timer before the timer function is called.  Another endpoint cancellation may
 930 * sneak in before the timer function can grab the lock, and that may queue
 931 * another stop endpoint command and add the timer back.  So we cannot use a
 932 * simple flag to say whether there is a pending stop endpoint command for a
 933 * particular endpoint.
 934 *
 935 * Instead we use a combination of that flag and checking if a new timer is
 936 * pending.
 937 */
 938void xhci_stop_endpoint_command_watchdog(struct timer_list *t)
 939{
 940        struct xhci_virt_ep *ep = from_timer(ep, t, stop_cmd_timer);
 941        struct xhci_hcd *xhci = ep->xhci;
 942        unsigned long flags;
 943
 944        spin_lock_irqsave(&xhci->lock, flags);
 945
 946        /* bail out if cmd completed but raced with stop ep watchdog timer.*/
 947        if (!(ep->ep_state & EP_STOP_CMD_PENDING) ||
 948            timer_pending(&ep->stop_cmd_timer)) {
 949                spin_unlock_irqrestore(&xhci->lock, flags);
 950                xhci_dbg(xhci, "Stop EP timer raced with cmd completion, exit");
 951                return;
 952        }
 953
 954        xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 955        ep->ep_state &= ~EP_STOP_CMD_PENDING;
 956
 957        xhci_halt(xhci);
 958
 959        /*
 960         * handle a stop endpoint cmd timeout as if host died (-ENODEV).
 961         * In the future we could distinguish between -ENODEV and -ETIMEDOUT
 962         * and try to recover a -ETIMEDOUT with a host controller reset
 963         */
 964        xhci_hc_died(xhci);
 965
 966        spin_unlock_irqrestore(&xhci->lock, flags);
 967        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
 968                        "xHCI host controller is dead.");
 969}
 970
 971static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 972                struct xhci_virt_device *dev,
 973                struct xhci_ring *ep_ring,
 974                unsigned int ep_index)
 975{
 976        union xhci_trb *dequeue_temp;
 977        int num_trbs_free_temp;
 978        bool revert = false;
 979
 980        num_trbs_free_temp = ep_ring->num_trbs_free;
 981        dequeue_temp = ep_ring->dequeue;
 982
 983        /* If we get two back-to-back stalls, and the first stalled transfer
 984         * ends just before a link TRB, the dequeue pointer will be left on
 985         * the link TRB by the code in the while loop.  So we have to update
 986         * the dequeue pointer one segment further, or we'll jump off
 987         * the segment into la-la-land.
 988         */
 989        if (trb_is_link(ep_ring->dequeue)) {
 990                ep_ring->deq_seg = ep_ring->deq_seg->next;
 991                ep_ring->dequeue = ep_ring->deq_seg->trbs;
 992        }
 993
 994        while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
 995                /* We have more usable TRBs */
 996                ep_ring->num_trbs_free++;
 997                ep_ring->dequeue++;
 998                if (trb_is_link(ep_ring->dequeue)) {
 999                        if (ep_ring->dequeue ==
1000                                        dev->eps[ep_index].queued_deq_ptr)
1001                                break;
1002                        ep_ring->deq_seg = ep_ring->deq_seg->next;
1003                        ep_ring->dequeue = ep_ring->deq_seg->trbs;
1004                }
1005                if (ep_ring->dequeue == dequeue_temp) {
1006                        revert = true;
1007                        break;
1008                }
1009        }
1010
1011        if (revert) {
1012                xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1013                ep_ring->num_trbs_free = num_trbs_free_temp;
1014        }
1015}
1016
1017/*
1018 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1019 * we need to clear the set deq pending flag in the endpoint ring state, so that
1020 * the TD queueing code can ring the doorbell again.  We also need to ring the
1021 * endpoint doorbell to restart the ring, but only if there aren't more
1022 * cancellations pending.
1023 */
1024static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
1025                union xhci_trb *trb, u32 cmd_comp_code)
1026{
1027        unsigned int ep_index;
1028        unsigned int stream_id;
1029        struct xhci_ring *ep_ring;
1030        struct xhci_virt_device *dev;
1031        struct xhci_virt_ep *ep;
1032        struct xhci_ep_ctx *ep_ctx;
1033        struct xhci_slot_ctx *slot_ctx;
1034
1035        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1036        stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1037        dev = xhci->devs[slot_id];
1038        ep = &dev->eps[ep_index];
1039
1040        ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1041        if (!ep_ring) {
1042                xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
1043                                stream_id);
1044                /* XXX: Harmless??? */
1045                goto cleanup;
1046        }
1047
1048        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1049        slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1050        trace_xhci_handle_cmd_set_deq(slot_ctx);
1051        trace_xhci_handle_cmd_set_deq_ep(ep_ctx);
1052
1053        if (cmd_comp_code != COMP_SUCCESS) {
1054                unsigned int ep_state;
1055                unsigned int slot_state;
1056
1057                switch (cmd_comp_code) {
1058                case COMP_TRB_ERROR:
1059                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
1060                        break;
1061                case COMP_CONTEXT_STATE_ERROR:
1062                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
1063                        ep_state = GET_EP_CTX_STATE(ep_ctx);
1064                        slot_state = le32_to_cpu(slot_ctx->dev_state);
1065                        slot_state = GET_SLOT_STATE(slot_state);
1066                        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1067                                        "Slot state = %u, EP state = %u",
1068                                        slot_state, ep_state);
1069                        break;
1070                case COMP_SLOT_NOT_ENABLED_ERROR:
1071                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
1072                                        slot_id);
1073                        break;
1074                default:
1075                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
1076                                        cmd_comp_code);
1077                        break;
1078                }
1079                /* OK what do we do now?  The endpoint state is hosed, and we
1080                 * should never get to this point if the synchronization between
1081                 * queueing, and endpoint state are correct.  This might happen
1082                 * if the device gets disconnected after we've finished
1083                 * cancelling URBs, which might not be an error...
1084                 */
1085        } else {
1086                u64 deq;
1087                /* 4.6.10 deq ptr is written to the stream ctx for streams */
1088                if (ep->ep_state & EP_HAS_STREAMS) {
1089                        struct xhci_stream_ctx *ctx =
1090                                &ep->stream_info->stream_ctx_array[stream_id];
1091                        deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1092                } else {
1093                        deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1094                }
1095                xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1096                        "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1097                if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1098                                         ep->queued_deq_ptr) == deq) {
1099                        /* Update the ring's dequeue segment and dequeue pointer
1100                         * to reflect the new position.
1101                         */
1102                        update_ring_for_set_deq_completion(xhci, dev,
1103                                ep_ring, ep_index);
1104                } else {
1105                        xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
1106                        xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1107                                  ep->queued_deq_seg, ep->queued_deq_ptr);
1108                }
1109        }
1110
1111cleanup:
1112        dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1113        dev->eps[ep_index].queued_deq_seg = NULL;
1114        dev->eps[ep_index].queued_deq_ptr = NULL;
1115        /* Restart any rings with pending URBs */
1116        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1117}
1118
1119static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
1120                union xhci_trb *trb, u32 cmd_comp_code)
1121{
1122        struct xhci_virt_device *vdev;
1123        struct xhci_ep_ctx *ep_ctx;
1124        unsigned int ep_index;
1125
1126        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1127        vdev = xhci->devs[slot_id];
1128        ep_ctx = xhci_get_ep_ctx(xhci, vdev->out_ctx, ep_index);
1129        trace_xhci_handle_cmd_reset_ep(ep_ctx);
1130
1131        /* This command will only fail if the endpoint wasn't halted,
1132         * but we don't care.
1133         */
1134        xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
1135                "Ignoring reset ep completion code of %u", cmd_comp_code);
1136
1137        /* HW with the reset endpoint quirk needs to have a configure endpoint
1138         * command complete before the endpoint can be used.  Queue that here
1139         * because the HW can't handle two commands being queued in a row.
1140         */
1141        if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1142                struct xhci_command *command;
1143
1144                command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1145                if (!command)
1146                        return;
1147
1148                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1149                                "Queueing configure endpoint command");
1150                xhci_queue_configure_endpoint(xhci, command,
1151                                xhci->devs[slot_id]->in_ctx->dma, slot_id,
1152                                false);
1153                xhci_ring_cmd_db(xhci);
1154        } else {
1155                /* Clear our internal halted state */
1156                xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1157        }
1158}
1159
1160static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1161                struct xhci_command *command, u32 cmd_comp_code)
1162{
1163        if (cmd_comp_code == COMP_SUCCESS)
1164                command->slot_id = slot_id;
1165        else
1166                command->slot_id = 0;
1167}
1168
1169static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1170{
1171        struct xhci_virt_device *virt_dev;
1172        struct xhci_slot_ctx *slot_ctx;
1173
1174        virt_dev = xhci->devs[slot_id];
1175        if (!virt_dev)
1176                return;
1177
1178        slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
1179        trace_xhci_handle_cmd_disable_slot(slot_ctx);
1180
1181        if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1182                /* Delete default control endpoint resources */
1183                xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1184        xhci_free_virt_device(xhci, slot_id);
1185}
1186
1187static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1188                struct xhci_event_cmd *event, u32 cmd_comp_code)
1189{
1190        struct xhci_virt_device *virt_dev;
1191        struct xhci_input_control_ctx *ctrl_ctx;
1192        struct xhci_ep_ctx *ep_ctx;
1193        unsigned int ep_index;
1194        unsigned int ep_state;
1195        u32 add_flags, drop_flags;
1196
1197        /*
1198         * Configure endpoint commands can come from the USB core
1199         * configuration or alt setting changes, or because the HW
1200         * needed an extra configure endpoint command after a reset
1201         * endpoint command or streams were being configured.
1202         * If the command was for a halted endpoint, the xHCI driver
1203         * is not waiting on the configure endpoint command.
1204         */
1205        virt_dev = xhci->devs[slot_id];
1206        ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1207        if (!ctrl_ctx) {
1208                xhci_warn(xhci, "Could not get input context, bad type.\n");
1209                return;
1210        }
1211
1212        add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1213        drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1214        /* Input ctx add_flags are the endpoint index plus one */
1215        ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1216
1217        ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, ep_index);
1218        trace_xhci_handle_cmd_config_ep(ep_ctx);
1219
1220        /* A usb_set_interface() call directly after clearing a halted
1221         * condition may race on this quirky hardware.  Not worth
1222         * worrying about, since this is prototype hardware.  Not sure
1223         * if this will work for streams, but streams support was
1224         * untested on this prototype.
1225         */
1226        if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1227                        ep_index != (unsigned int) -1 &&
1228                        add_flags - SLOT_FLAG == drop_flags) {
1229                ep_state = virt_dev->eps[ep_index].ep_state;
1230                if (!(ep_state & EP_HALTED))
1231                        return;
1232                xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1233                                "Completed config ep cmd - "
1234                                "last ep index = %d, state = %d",
1235                                ep_index, ep_state);
1236                /* Clear internal halted state and restart ring(s) */
1237                virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1238                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1239                return;
1240        }
1241        return;
1242}
1243
1244static void xhci_handle_cmd_addr_dev(struct xhci_hcd *xhci, int slot_id)
1245{
1246        struct xhci_virt_device *vdev;
1247        struct xhci_slot_ctx *slot_ctx;
1248
1249        vdev = xhci->devs[slot_id];
1250        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1251        trace_xhci_handle_cmd_addr_dev(slot_ctx);
1252}
1253
1254static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1255                struct xhci_event_cmd *event)
1256{
1257        struct xhci_virt_device *vdev;
1258        struct xhci_slot_ctx *slot_ctx;
1259
1260        vdev = xhci->devs[slot_id];
1261        slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
1262        trace_xhci_handle_cmd_reset_dev(slot_ctx);
1263
1264        xhci_dbg(xhci, "Completed reset device command.\n");
1265        if (!xhci->devs[slot_id])
1266                xhci_warn(xhci, "Reset device command completion "
1267                                "for disabled slot %u\n", slot_id);
1268}
1269
1270static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1271                struct xhci_event_cmd *event)
1272{
1273        if (!(xhci->quirks & XHCI_NEC_HOST)) {
1274                xhci_warn(xhci, "WARN NEC_GET_FW command on non-NEC host\n");
1275                return;
1276        }
1277        xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1278                        "NEC firmware version %2x.%02x",
1279                        NEC_FW_MAJOR(le32_to_cpu(event->status)),
1280                        NEC_FW_MINOR(le32_to_cpu(event->status)));
1281}
1282
1283static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
1284{
1285        list_del(&cmd->cmd_list);
1286
1287        if (cmd->completion) {
1288                cmd->status = status;
1289                complete(cmd->completion);
1290        } else {
1291                kfree(cmd);
1292        }
1293}
1294
1295void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1296{
1297        struct xhci_command *cur_cmd, *tmp_cmd;
1298        xhci->current_cmd = NULL;
1299        list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
1300                xhci_complete_del_and_free_cmd(cur_cmd, COMP_COMMAND_ABORTED);
1301}
1302
1303void xhci_handle_command_timeout(struct work_struct *work)
1304{
1305        struct xhci_hcd *xhci;
1306        unsigned long flags;
1307        u64 hw_ring_state;
1308
1309        xhci = container_of(to_delayed_work(work), struct xhci_hcd, cmd_timer);
1310
1311        spin_lock_irqsave(&xhci->lock, flags);
1312
1313        /*
1314         * If timeout work is pending, or current_cmd is NULL, it means we
1315         * raced with command completion. Command is handled so just return.
1316         */
1317        if (!xhci->current_cmd || delayed_work_pending(&xhci->cmd_timer)) {
1318                spin_unlock_irqrestore(&xhci->lock, flags);
1319                return;
1320        }
1321        /* mark this command to be cancelled */
1322        xhci->current_cmd->status = COMP_COMMAND_ABORTED;
1323
1324        /* Make sure command ring is running before aborting it */
1325        hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1326        if (hw_ring_state == ~(u64)0) {
1327                xhci_hc_died(xhci);
1328                goto time_out_completed;
1329        }
1330
1331        if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1332            (hw_ring_state & CMD_RING_RUNNING))  {
1333                /* Prevent new doorbell, and start command abort */
1334                xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
1335                xhci_dbg(xhci, "Command timeout\n");
1336                xhci_abort_cmd_ring(xhci, flags);
1337                goto time_out_completed;
1338        }
1339
1340        /* host removed. Bail out */
1341        if (xhci->xhc_state & XHCI_STATE_REMOVING) {
1342                xhci_dbg(xhci, "host removed, ring start fail?\n");
1343                xhci_cleanup_command_queue(xhci);
1344
1345                goto time_out_completed;
1346        }
1347
1348        /* command timeout on stopped ring, ring can't be aborted */
1349        xhci_dbg(xhci, "Command timeout on stopped ring\n");
1350        xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1351
1352time_out_completed:
1353        spin_unlock_irqrestore(&xhci->lock, flags);
1354        return;
1355}
1356
1357static void handle_cmd_completion(struct xhci_hcd *xhci,
1358                struct xhci_event_cmd *event)
1359{
1360        int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1361        u64 cmd_dma;
1362        dma_addr_t cmd_dequeue_dma;
1363        u32 cmd_comp_code;
1364        union xhci_trb *cmd_trb;
1365        struct xhci_command *cmd;
1366        u32 cmd_type;
1367
1368        cmd_dma = le64_to_cpu(event->cmd_trb);
1369        cmd_trb = xhci->cmd_ring->dequeue;
1370
1371        trace_xhci_handle_command(xhci->cmd_ring, &cmd_trb->generic);
1372
1373        cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1374                        cmd_trb);
1375        /*
1376         * Check whether the completion event is for our internal kept
1377         * command.
1378         */
1379        if (!cmd_dequeue_dma || cmd_dma != (u64)cmd_dequeue_dma) {
1380                xhci_warn(xhci,
1381                          "ERROR mismatched command completion event\n");
1382                return;
1383        }
1384
1385        cmd = list_first_entry(&xhci->cmd_list, struct xhci_command, cmd_list);
1386
1387        cancel_delayed_work(&xhci->cmd_timer);
1388
1389        cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
1390
1391        /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1392        if (cmd_comp_code == COMP_COMMAND_RING_STOPPED) {
1393                complete_all(&xhci->cmd_ring_stop_completion);
1394                return;
1395        }
1396
1397        if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1398                xhci_err(xhci,
1399                         "Command completion event does not match command\n");
1400                return;
1401        }
1402
1403        /*
1404         * Host aborted the command ring, check if the current command was
1405         * supposed to be aborted, otherwise continue normally.
1406         * The command ring is stopped now, but the xHC will issue a Command
1407         * Ring Stopped event which will cause us to restart it.
1408         */
1409        if (cmd_comp_code == COMP_COMMAND_ABORTED) {
1410                xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1411                if (cmd->status == COMP_COMMAND_ABORTED) {
1412                        if (xhci->current_cmd == cmd)
1413                                xhci->current_cmd = NULL;
1414                        goto event_handled;
1415                }
1416        }
1417
1418        cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1419        switch (cmd_type) {
1420        case TRB_ENABLE_SLOT:
1421                xhci_handle_cmd_enable_slot(xhci, slot_id, cmd, cmd_comp_code);
1422                break;
1423        case TRB_DISABLE_SLOT:
1424                xhci_handle_cmd_disable_slot(xhci, slot_id);
1425                break;
1426        case TRB_CONFIG_EP:
1427                if (!cmd->completion)
1428                        xhci_handle_cmd_config_ep(xhci, slot_id, event,
1429                                                  cmd_comp_code);
1430                break;
1431        case TRB_EVAL_CONTEXT:
1432                break;
1433        case TRB_ADDR_DEV:
1434                xhci_handle_cmd_addr_dev(xhci, slot_id);
1435                break;
1436        case TRB_STOP_RING:
1437                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1438                                le32_to_cpu(cmd_trb->generic.field[3])));
1439                if (!cmd->completion)
1440                        xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
1441                break;
1442        case TRB_SET_DEQ:
1443                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1444                                le32_to_cpu(cmd_trb->generic.field[3])));
1445                xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
1446                break;
1447        case TRB_CMD_NOOP:
1448                /* Is this an aborted command turned to NO-OP? */
1449                if (cmd->status == COMP_COMMAND_RING_STOPPED)
1450                        cmd_comp_code = COMP_COMMAND_RING_STOPPED;
1451                break;
1452        case TRB_RESET_EP:
1453                WARN_ON(slot_id != TRB_TO_SLOT_ID(
1454                                le32_to_cpu(cmd_trb->generic.field[3])));
1455                xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
1456                break;
1457        case TRB_RESET_DEV:
1458                /* SLOT_ID field in reset device cmd completion event TRB is 0.
1459                 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1460                 */
1461                slot_id = TRB_TO_SLOT_ID(
1462                                le32_to_cpu(cmd_trb->generic.field[3]));
1463                xhci_handle_cmd_reset_dev(xhci, slot_id, event);
1464                break;
1465        case TRB_NEC_GET_FW:
1466                xhci_handle_cmd_nec_get_fw(xhci, event);
1467                break;
1468        default:
1469                /* Skip over unknown commands on the event ring */
1470                xhci_info(xhci, "INFO unknown command type %d\n", cmd_type);
1471                break;
1472        }
1473
1474        /* restart timer if this wasn't the last command */
1475        if (!list_is_singular(&xhci->cmd_list)) {
1476                xhci->current_cmd = list_first_entry(&cmd->cmd_list,
1477                                                struct xhci_command, cmd_list);
1478                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
1479        } else if (xhci->current_cmd == cmd) {
1480                xhci->current_cmd = NULL;
1481        }
1482
1483event_handled:
1484        xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
1485
1486        inc_deq(xhci, xhci->cmd_ring);
1487}
1488
1489static void handle_vendor_event(struct xhci_hcd *xhci,
1490                union xhci_trb *event)
1491{
1492        u32 trb_type;
1493
1494        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1495        xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1496        if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1497                handle_cmd_completion(xhci, &event->event_cmd);
1498}
1499
1500static void handle_device_notification(struct xhci_hcd *xhci,
1501                union xhci_trb *event)
1502{
1503        u32 slot_id;
1504        struct usb_device *udev;
1505
1506        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
1507        if (!xhci->devs[slot_id]) {
1508                xhci_warn(xhci, "Device Notification event for "
1509                                "unused slot %u\n", slot_id);
1510                return;
1511        }
1512
1513        xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1514                        slot_id);
1515        udev = xhci->devs[slot_id]->udev;
1516        if (udev && udev->parent)
1517                usb_wakeup_notification(udev->parent, udev->portnum);
1518}
1519
1520static void handle_port_status(struct xhci_hcd *xhci,
1521                union xhci_trb *event)
1522{
1523        struct usb_hcd *hcd;
1524        u32 port_id;
1525        u32 portsc, cmd_reg;
1526        int max_ports;
1527        int slot_id;
1528        unsigned int hcd_portnum;
1529        struct xhci_bus_state *bus_state;
1530        bool bogus_port_status = false;
1531        struct xhci_port *port;
1532
1533        /* Port status change events always have a successful completion code */
1534        if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS)
1535                xhci_warn(xhci,
1536                          "WARN: xHC returned failed port status event\n");
1537
1538        port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1539        xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1540
1541        max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1542        if ((port_id <= 0) || (port_id > max_ports)) {
1543                xhci_warn(xhci, "Invalid port id %d\n", port_id);
1544                inc_deq(xhci, xhci->event_ring);
1545                return;
1546        }
1547
1548        port = &xhci->hw_ports[port_id - 1];
1549        if (!port || !port->rhub || port->hcd_portnum == DUPLICATE_ENTRY) {
1550                xhci_warn(xhci, "Event for invalid port %u\n", port_id);
1551                bogus_port_status = true;
1552                goto cleanup;
1553        }
1554
1555        hcd = port->rhub->hcd;
1556        bus_state = &xhci->bus_state[hcd_index(hcd)];
1557        hcd_portnum = port->hcd_portnum;
1558        portsc = readl(port->addr);
1559
1560        trace_xhci_handle_port_status(hcd_portnum, portsc);
1561
1562        if (hcd->state == HC_STATE_SUSPENDED) {
1563                xhci_dbg(xhci, "resume root hub\n");
1564                usb_hcd_resume_root_hub(hcd);
1565        }
1566
1567        if (hcd->speed >= HCD_USB3 && (portsc & PORT_PLS_MASK) == XDEV_INACTIVE)
1568                bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1569
1570        if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_RESUME) {
1571                xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1572
1573                cmd_reg = readl(&xhci->op_regs->command);
1574                if (!(cmd_reg & CMD_RUN)) {
1575                        xhci_warn(xhci, "xHC is not running.\n");
1576                        goto cleanup;
1577                }
1578
1579                if (DEV_SUPERSPEED_ANY(portsc)) {
1580                        xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1581                        /* Set a flag to say the port signaled remote wakeup,
1582                         * so we can tell the difference between the end of
1583                         * device and host initiated resume.
1584                         */
1585                        bus_state->port_remote_wakeup |= 1 << hcd_portnum;
1586                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1587                        xhci_set_link_state(xhci, port, XDEV_U0);
1588                        /* Need to wait until the next link state change
1589                         * indicates the device is actually in U0.
1590                         */
1591                        bogus_port_status = true;
1592                        goto cleanup;
1593                } else if (!test_bit(hcd_portnum, &bus_state->resuming_ports)) {
1594                        xhci_dbg(xhci, "resume HS port %d\n", port_id);
1595                        bus_state->resume_done[hcd_portnum] = jiffies +
1596                                msecs_to_jiffies(USB_RESUME_TIMEOUT);
1597                        set_bit(hcd_portnum, &bus_state->resuming_ports);
1598                        /* Do the rest in GetPortStatus after resume time delay.
1599                         * Avoid polling roothub status before that so that a
1600                         * usb device auto-resume latency around ~40ms.
1601                         */
1602                        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1603                        mod_timer(&hcd->rh_timer,
1604                                  bus_state->resume_done[hcd_portnum]);
1605                        bogus_port_status = true;
1606                }
1607        }
1608
1609        if ((portsc & PORT_PLC) && (portsc & PORT_PLS_MASK) == XDEV_U0 &&
1610                        DEV_SUPERSPEED_ANY(portsc)) {
1611                xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1612                /* We've just brought the device into U0 through either the
1613                 * Resume state after a device remote wakeup, or through the
1614                 * U3Exit state after a host-initiated resume.  If it's a device
1615                 * initiated remote wake, don't pass up the link state change,
1616                 * so the roothub behavior is consistent with external
1617                 * USB 3.0 hub behavior.
1618                 */
1619                slot_id = xhci_find_slot_id_by_port(hcd, xhci, hcd_portnum + 1);
1620                if (slot_id && xhci->devs[slot_id])
1621                        xhci_ring_device(xhci, slot_id);
1622                if (bus_state->port_remote_wakeup & (1 << hcd_portnum)) {
1623                        bus_state->port_remote_wakeup &= ~(1 << hcd_portnum);
1624                        xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1625                        usb_wakeup_notification(hcd->self.root_hub,
1626                                        hcd_portnum + 1);
1627                        bogus_port_status = true;
1628                        goto cleanup;
1629                }
1630        }
1631
1632        /*
1633         * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1634         * RExit to a disconnect state).  If so, let the the driver know it's
1635         * out of the RExit state.
1636         */
1637        if (!DEV_SUPERSPEED_ANY(portsc) &&
1638                        test_and_clear_bit(hcd_portnum,
1639                                &bus_state->rexit_ports)) {
1640                complete(&bus_state->rexit_done[hcd_portnum]);
1641                bogus_port_status = true;
1642                goto cleanup;
1643        }
1644
1645        if (hcd->speed < HCD_USB3)
1646                xhci_test_and_clear_bit(xhci, port, PORT_PLC);
1647
1648cleanup:
1649        /* Update event ring dequeue pointer before dropping the lock */
1650        inc_deq(xhci, xhci->event_ring);
1651
1652        /* Don't make the USB core poll the roothub if we got a bad port status
1653         * change event.  Besides, at that point we can't tell which roothub
1654         * (USB 2.0 or USB 3.0) to kick.
1655         */
1656        if (bogus_port_status)
1657                return;
1658
1659        /*
1660         * xHCI port-status-change events occur when the "or" of all the
1661         * status-change bits in the portsc register changes from 0 to 1.
1662         * New status changes won't cause an event if any other change
1663         * bits are still set.  When an event occurs, switch over to
1664         * polling to avoid losing status changes.
1665         */
1666        xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1667        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1668        spin_unlock(&xhci->lock);
1669        /* Pass this up to the core */
1670        usb_hcd_poll_rh_status(hcd);
1671        spin_lock(&xhci->lock);
1672}
1673
1674/*
1675 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1676 * at end_trb, which may be in another segment.  If the suspect DMA address is a
1677 * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1678 * returns 0.
1679 */
1680struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1681                struct xhci_segment *start_seg,
1682                union xhci_trb  *start_trb,
1683                union xhci_trb  *end_trb,
1684                dma_addr_t      suspect_dma,
1685                bool            debug)
1686{
1687        dma_addr_t start_dma;
1688        dma_addr_t end_seg_dma;
1689        dma_addr_t end_trb_dma;
1690        struct xhci_segment *cur_seg;
1691
1692        start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1693        cur_seg = start_seg;
1694
1695        do {
1696                if (start_dma == 0)
1697                        return NULL;
1698                /* We may get an event for a Link TRB in the middle of a TD */
1699                end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1700                                &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1701                /* If the end TRB isn't in this segment, this is set to 0 */
1702                end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1703
1704                if (debug)
1705                        xhci_warn(xhci,
1706                                "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1707                                (unsigned long long)suspect_dma,
1708                                (unsigned long long)start_dma,
1709                                (unsigned long long)end_trb_dma,
1710                                (unsigned long long)cur_seg->dma,
1711                                (unsigned long long)end_seg_dma);
1712
1713                if (end_trb_dma > 0) {
1714                        /* The end TRB is in this segment, so suspect should be here */
1715                        if (start_dma <= end_trb_dma) {
1716                                if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1717                                        return cur_seg;
1718                        } else {
1719                                /* Case for one segment with
1720                                 * a TD wrapped around to the top
1721                                 */
1722                                if ((suspect_dma >= start_dma &&
1723                                                        suspect_dma <= end_seg_dma) ||
1724                                                (suspect_dma >= cur_seg->dma &&
1725                                                 suspect_dma <= end_trb_dma))
1726                                        return cur_seg;
1727                        }
1728                        return NULL;
1729                } else {
1730                        /* Might still be somewhere in this segment */
1731                        if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1732                                return cur_seg;
1733                }
1734                cur_seg = cur_seg->next;
1735                start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1736        } while (cur_seg != start_seg);
1737
1738        return NULL;
1739}
1740
1741static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1742                unsigned int slot_id, unsigned int ep_index,
1743                unsigned int stream_id, struct xhci_td *td,
1744                enum xhci_ep_reset_type reset_type)
1745{
1746        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1747        struct xhci_command *command;
1748        command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1749        if (!command)
1750                return;
1751
1752        ep->ep_state |= EP_HALTED;
1753
1754        xhci_queue_reset_ep(xhci, command, slot_id, ep_index, reset_type);
1755
1756        if (reset_type == EP_HARD_RESET) {
1757                ep->ep_state |= EP_HARD_CLEAR_TOGGLE;
1758                xhci_cleanup_stalled_ring(xhci, ep_index, stream_id, td);
1759        }
1760        xhci_ring_cmd_db(xhci);
1761}
1762
1763/* Check if an error has halted the endpoint ring.  The class driver will
1764 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1765 * However, a babble and other errors also halt the endpoint ring, and the class
1766 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1767 * Ring Dequeue Pointer command manually.
1768 */
1769static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1770                struct xhci_ep_ctx *ep_ctx,
1771                unsigned int trb_comp_code)
1772{
1773        /* TRB completion codes that may require a manual halt cleanup */
1774        if (trb_comp_code == COMP_USB_TRANSACTION_ERROR ||
1775                        trb_comp_code == COMP_BABBLE_DETECTED_ERROR ||
1776                        trb_comp_code == COMP_SPLIT_TRANSACTION_ERROR)
1777                /* The 0.95 spec says a babbling control endpoint
1778                 * is not halted. The 0.96 spec says it is.  Some HW
1779                 * claims to be 0.95 compliant, but it halts the control
1780                 * endpoint anyway.  Check if a babble halted the
1781                 * endpoint.
1782                 */
1783                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_HALTED)
1784                        return 1;
1785
1786        return 0;
1787}
1788
1789int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1790{
1791        if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1792                /* Vendor defined "informational" completion code,
1793                 * treat as not-an-error.
1794                 */
1795                xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1796                                trb_comp_code);
1797                xhci_dbg(xhci, "Treating code as success.\n");
1798                return 1;
1799        }
1800        return 0;
1801}
1802
1803static int xhci_td_cleanup(struct xhci_hcd *xhci, struct xhci_td *td,
1804                struct xhci_ring *ep_ring, int *status)
1805{
1806        struct urb *urb = NULL;
1807
1808        /* Clean up the endpoint's TD list */
1809        urb = td->urb;
1810
1811        /* if a bounce buffer was used to align this td then unmap it */
1812        xhci_unmap_td_bounce_buffer(xhci, ep_ring, td);
1813
1814        /* Do one last check of the actual transfer length.
1815         * If the host controller said we transferred more data than the buffer
1816         * length, urb->actual_length will be a very big number (since it's
1817         * unsigned).  Play it safe and say we didn't transfer anything.
1818         */
1819        if (urb->actual_length > urb->transfer_buffer_length) {
1820                xhci_warn(xhci, "URB req %u and actual %u transfer length mismatch\n",
1821                          urb->transfer_buffer_length, urb->actual_length);
1822                urb->actual_length = 0;
1823                *status = 0;
1824        }
1825        list_del_init(&td->td_list);
1826        /* Was this TD slated to be cancelled but completed anyway? */
1827        if (!list_empty(&td->cancelled_td_list))
1828                list_del_init(&td->cancelled_td_list);
1829
1830        inc_td_cnt(urb);
1831        /* Giveback the urb when all the tds are completed */
1832        if (last_td_in_urb(td)) {
1833                if ((urb->actual_length != urb->transfer_buffer_length &&
1834                     (urb->transfer_flags & URB_SHORT_NOT_OK)) ||
1835                    (*status != 0 && !usb_endpoint_xfer_isoc(&urb->ep->desc)))
1836                        xhci_dbg(xhci, "Giveback URB %p, len = %d, expected = %d, status = %d\n",
1837                                 urb, urb->actual_length,
1838                                 urb->transfer_buffer_length, *status);
1839
1840                /* set isoc urb status to 0 just as EHCI, UHCI, and OHCI */
1841                if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
1842                        *status = 0;
1843                xhci_giveback_urb_in_irq(xhci, td, *status);
1844        }
1845
1846        return 0;
1847}
1848
1849static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1850        struct xhci_transfer_event *event,
1851        struct xhci_virt_ep *ep, int *status)
1852{
1853        struct xhci_virt_device *xdev;
1854        struct xhci_ep_ctx *ep_ctx;
1855        struct xhci_ring *ep_ring;
1856        unsigned int slot_id;
1857        u32 trb_comp_code;
1858        int ep_index;
1859
1860        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1861        xdev = xhci->devs[slot_id];
1862        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1863        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1864        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1865        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1866
1867        if (trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
1868                        trb_comp_code == COMP_STOPPED ||
1869                        trb_comp_code == COMP_STOPPED_SHORT_PACKET) {
1870                /* The Endpoint Stop Command completion will take care of any
1871                 * stopped TDs.  A stopped TD may be restarted, so don't update
1872                 * the ring dequeue pointer or take this TD off any lists yet.
1873                 */
1874                return 0;
1875        }
1876        if (trb_comp_code == COMP_STALL_ERROR ||
1877                xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1878                                                trb_comp_code)) {
1879                /* Issue a reset endpoint command to clear the host side
1880                 * halt, followed by a set dequeue command to move the
1881                 * dequeue pointer past the TD.
1882                 * The class driver clears the device side halt later.
1883                 */
1884                xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1885                                        ep_ring->stream_id, td, EP_HARD_RESET);
1886        } else {
1887                /* Update ring dequeue pointer */
1888                while (ep_ring->dequeue != td->last_trb)
1889                        inc_deq(xhci, ep_ring);
1890                inc_deq(xhci, ep_ring);
1891        }
1892
1893        return xhci_td_cleanup(xhci, td, ep_ring, status);
1894}
1895
1896/* sum trb lengths from ring dequeue up to stop_trb, _excluding_ stop_trb */
1897static int sum_trb_lengths(struct xhci_hcd *xhci, struct xhci_ring *ring,
1898                           union xhci_trb *stop_trb)
1899{
1900        u32 sum;
1901        union xhci_trb *trb = ring->dequeue;
1902        struct xhci_segment *seg = ring->deq_seg;
1903
1904        for (sum = 0; trb != stop_trb; next_trb(xhci, ring, &seg, &trb)) {
1905                if (!trb_is_noop(trb) && !trb_is_link(trb))
1906                        sum += TRB_LEN(le32_to_cpu(trb->generic.field[2]));
1907        }
1908        return sum;
1909}
1910
1911/*
1912 * Process control tds, update urb status and actual_length.
1913 */
1914static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1915        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1916        struct xhci_virt_ep *ep, int *status)
1917{
1918        struct xhci_virt_device *xdev;
1919        unsigned int slot_id;
1920        int ep_index;
1921        struct xhci_ep_ctx *ep_ctx;
1922        u32 trb_comp_code;
1923        u32 remaining, requested;
1924        u32 trb_type;
1925
1926        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(ep_trb->generic.field[3]));
1927        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1928        xdev = xhci->devs[slot_id];
1929        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1930        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1931        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1932        requested = td->urb->transfer_buffer_length;
1933        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1934
1935        switch (trb_comp_code) {
1936        case COMP_SUCCESS:
1937                if (trb_type != TRB_STATUS) {
1938                        xhci_warn(xhci, "WARN: Success on ctrl %s TRB without IOC set?\n",
1939                                  (trb_type == TRB_DATA) ? "data" : "setup");
1940                        *status = -ESHUTDOWN;
1941                        break;
1942                }
1943                *status = 0;
1944                break;
1945        case COMP_SHORT_PACKET:
1946                *status = 0;
1947                break;
1948        case COMP_STOPPED_SHORT_PACKET:
1949                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
1950                        td->urb->actual_length = remaining;
1951                else
1952                        xhci_warn(xhci, "WARN: Stopped Short Packet on ctrl setup or status TRB\n");
1953                goto finish_td;
1954        case COMP_STOPPED:
1955                switch (trb_type) {
1956                case TRB_SETUP:
1957                        td->urb->actual_length = 0;
1958                        goto finish_td;
1959                case TRB_DATA:
1960                case TRB_NORMAL:
1961                        td->urb->actual_length = requested - remaining;
1962                        goto finish_td;
1963                case TRB_STATUS:
1964                        td->urb->actual_length = requested;
1965                        goto finish_td;
1966                default:
1967                        xhci_warn(xhci, "WARN: unexpected TRB Type %d\n",
1968                                  trb_type);
1969                        goto finish_td;
1970                }
1971        case COMP_STOPPED_LENGTH_INVALID:
1972                goto finish_td;
1973        default:
1974                if (!xhci_requires_manual_halt_cleanup(xhci,
1975                                                       ep_ctx, trb_comp_code))
1976                        break;
1977                xhci_dbg(xhci, "TRB error %u, halted endpoint index = %u\n",
1978                         trb_comp_code, ep_index);
1979                /* else fall through */
1980        case COMP_STALL_ERROR:
1981                /* Did we transfer part of the data (middle) phase? */
1982                if (trb_type == TRB_DATA || trb_type == TRB_NORMAL)
1983                        td->urb->actual_length = requested - remaining;
1984                else if (!td->urb_length_set)
1985                        td->urb->actual_length = 0;
1986                goto finish_td;
1987        }
1988
1989        /* stopped at setup stage, no data transferred */
1990        if (trb_type == TRB_SETUP)
1991                goto finish_td;
1992
1993        /*
1994         * if on data stage then update the actual_length of the URB and flag it
1995         * as set, so it won't be overwritten in the event for the last TRB.
1996         */
1997        if (trb_type == TRB_DATA ||
1998                trb_type == TRB_NORMAL) {
1999                td->urb_length_set = true;
2000                td->urb->actual_length = requested - remaining;
2001                xhci_dbg(xhci, "Waiting for status stage event\n");
2002                return 0;
2003        }
2004
2005        /* at status stage */
2006        if (!td->urb_length_set)
2007                td->urb->actual_length = requested;
2008
2009finish_td:
2010        return finish_td(xhci, td, event, ep, status);
2011}
2012
2013/*
2014 * Process isochronous tds, update urb packet status and actual_length.
2015 */
2016static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2017        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2018        struct xhci_virt_ep *ep, int *status)
2019{
2020        struct xhci_ring *ep_ring;
2021        struct urb_priv *urb_priv;
2022        int idx;
2023        struct usb_iso_packet_descriptor *frame;
2024        u32 trb_comp_code;
2025        bool sum_trbs_for_length = false;
2026        u32 remaining, requested, ep_trb_len;
2027        int short_framestatus;
2028
2029        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2030        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2031        urb_priv = td->urb->hcpriv;
2032        idx = urb_priv->num_tds_done;
2033        frame = &td->urb->iso_frame_desc[idx];
2034        requested = frame->length;
2035        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2036        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2037        short_framestatus = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2038                -EREMOTEIO : 0;
2039
2040        /* handle completion code */
2041        switch (trb_comp_code) {
2042        case COMP_SUCCESS:
2043                if (remaining) {
2044                        frame->status = short_framestatus;
2045                        if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2046                                sum_trbs_for_length = true;
2047                        break;
2048                }
2049                frame->status = 0;
2050                break;
2051        case COMP_SHORT_PACKET:
2052                frame->status = short_framestatus;
2053                sum_trbs_for_length = true;
2054                break;
2055        case COMP_BANDWIDTH_OVERRUN_ERROR:
2056                frame->status = -ECOMM;
2057                break;
2058        case COMP_ISOCH_BUFFER_OVERRUN:
2059        case COMP_BABBLE_DETECTED_ERROR:
2060                frame->status = -EOVERFLOW;
2061                break;
2062        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2063        case COMP_STALL_ERROR:
2064                frame->status = -EPROTO;
2065                break;
2066        case COMP_USB_TRANSACTION_ERROR:
2067                frame->status = -EPROTO;
2068                if (ep_trb != td->last_trb)
2069                        return 0;
2070                break;
2071        case COMP_STOPPED:
2072                sum_trbs_for_length = true;
2073                break;
2074        case COMP_STOPPED_SHORT_PACKET:
2075                /* field normally containing residue now contains tranferred */
2076                frame->status = short_framestatus;
2077                requested = remaining;
2078                break;
2079        case COMP_STOPPED_LENGTH_INVALID:
2080                requested = 0;
2081                remaining = 0;
2082                break;
2083        default:
2084                sum_trbs_for_length = true;
2085                frame->status = -1;
2086                break;
2087        }
2088
2089        if (sum_trbs_for_length)
2090                frame->actual_length = sum_trb_lengths(xhci, ep_ring, ep_trb) +
2091                        ep_trb_len - remaining;
2092        else
2093                frame->actual_length = requested;
2094
2095        td->urb->actual_length += frame->actual_length;
2096
2097        return finish_td(xhci, td, event, ep, status);
2098}
2099
2100static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2101                        struct xhci_transfer_event *event,
2102                        struct xhci_virt_ep *ep, int *status)
2103{
2104        struct xhci_ring *ep_ring;
2105        struct urb_priv *urb_priv;
2106        struct usb_iso_packet_descriptor *frame;
2107        int idx;
2108
2109        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2110        urb_priv = td->urb->hcpriv;
2111        idx = urb_priv->num_tds_done;
2112        frame = &td->urb->iso_frame_desc[idx];
2113
2114        /* The transfer is partly done. */
2115        frame->status = -EXDEV;
2116
2117        /* calc actual length */
2118        frame->actual_length = 0;
2119
2120        /* Update ring dequeue pointer */
2121        while (ep_ring->dequeue != td->last_trb)
2122                inc_deq(xhci, ep_ring);
2123        inc_deq(xhci, ep_ring);
2124
2125        return xhci_td_cleanup(xhci, td, ep_ring, status);
2126}
2127
2128/*
2129 * Process bulk and interrupt tds, update urb status and actual_length.
2130 */
2131static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2132        union xhci_trb *ep_trb, struct xhci_transfer_event *event,
2133        struct xhci_virt_ep *ep, int *status)
2134{
2135        struct xhci_ring *ep_ring;
2136        u32 trb_comp_code;
2137        u32 remaining, requested, ep_trb_len;
2138
2139        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2140        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2141        remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2142        ep_trb_len = TRB_LEN(le32_to_cpu(ep_trb->generic.field[2]));
2143        requested = td->urb->transfer_buffer_length;
2144
2145        switch (trb_comp_code) {
2146        case COMP_SUCCESS:
2147                /* handle success with untransferred data as short packet */
2148                if (ep_trb != td->last_trb || remaining) {
2149                        xhci_warn(xhci, "WARN Successful completion on short TX\n");
2150                        xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2151                                 td->urb->ep->desc.bEndpointAddress,
2152                                 requested, remaining);
2153                }
2154                *status = 0;
2155                break;
2156        case COMP_SHORT_PACKET:
2157                xhci_dbg(xhci, "ep %#x - asked for %d bytes, %d bytes untransferred\n",
2158                         td->urb->ep->desc.bEndpointAddress,
2159                         requested, remaining);
2160                *status = 0;
2161                break;
2162        case COMP_STOPPED_SHORT_PACKET:
2163                td->urb->actual_length = remaining;
2164                goto finish_td;
2165        case COMP_STOPPED_LENGTH_INVALID:
2166                /* stopped on ep trb with invalid length, exclude it */
2167                ep_trb_len      = 0;
2168                remaining       = 0;
2169                break;
2170        default:
2171                /* do nothing */
2172                break;
2173        }
2174
2175        if (ep_trb == td->last_trb)
2176                td->urb->actual_length = requested - remaining;
2177        else
2178                td->urb->actual_length =
2179                        sum_trb_lengths(xhci, ep_ring, ep_trb) +
2180                        ep_trb_len - remaining;
2181finish_td:
2182        if (remaining > requested) {
2183                xhci_warn(xhci, "bad transfer trb length %d in event trb\n",
2184                          remaining);
2185                td->urb->actual_length = 0;
2186        }
2187        return finish_td(xhci, td, event, ep, status);
2188}
2189
2190/*
2191 * If this function returns an error condition, it means it got a Transfer
2192 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2193 * At this point, the host controller is probably hosed and should be reset.
2194 */
2195static int handle_tx_event(struct xhci_hcd *xhci,
2196                struct xhci_transfer_event *event)
2197{
2198        struct xhci_virt_device *xdev;
2199        struct xhci_virt_ep *ep;
2200        struct xhci_ring *ep_ring;
2201        unsigned int slot_id;
2202        int ep_index;
2203        struct xhci_td *td = NULL;
2204        dma_addr_t ep_trb_dma;
2205        struct xhci_segment *ep_seg;
2206        union xhci_trb *ep_trb;
2207        int status = -EINPROGRESS;
2208        struct xhci_ep_ctx *ep_ctx;
2209        struct list_head *tmp;
2210        u32 trb_comp_code;
2211        int td_num = 0;
2212        bool handling_skipped_tds = false;
2213
2214        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2215        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2216        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2217        ep_trb_dma = le64_to_cpu(event->buffer);
2218
2219        xdev = xhci->devs[slot_id];
2220        if (!xdev) {
2221                xhci_err(xhci, "ERROR Transfer event pointed to bad slot %u\n",
2222                         slot_id);
2223                goto err_out;
2224        }
2225
2226        ep = &xdev->eps[ep_index];
2227        ep_ring = xhci_dma_to_transfer_ring(ep, ep_trb_dma);
2228        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2229
2230        if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) {
2231                xhci_err(xhci,
2232                         "ERROR Transfer event for disabled endpoint slot %u ep %u\n",
2233                          slot_id, ep_index);
2234                goto err_out;
2235        }
2236
2237        /* Some transfer events don't always point to a trb, see xhci 4.17.4 */
2238        if (!ep_ring) {
2239                switch (trb_comp_code) {
2240                case COMP_STALL_ERROR:
2241                case COMP_USB_TRANSACTION_ERROR:
2242                case COMP_INVALID_STREAM_TYPE_ERROR:
2243                case COMP_INVALID_STREAM_ID_ERROR:
2244                        xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index, 0,
2245                                                     NULL, EP_SOFT_RESET);
2246                        goto cleanup;
2247                case COMP_RING_UNDERRUN:
2248                case COMP_RING_OVERRUN:
2249                        goto cleanup;
2250                default:
2251                        xhci_err(xhci, "ERROR Transfer event for unknown stream ring slot %u ep %u\n",
2252                                 slot_id, ep_index);
2253                        goto err_out;
2254                }
2255        }
2256
2257        /* Count current td numbers if ep->skip is set */
2258        if (ep->skip) {
2259                list_for_each(tmp, &ep_ring->td_list)
2260                        td_num++;
2261        }
2262
2263        /* Look for common error cases */
2264        switch (trb_comp_code) {
2265        /* Skip codes that require special handling depending on
2266         * transfer type
2267         */
2268        case COMP_SUCCESS:
2269                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2270                        break;
2271                if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2272                        trb_comp_code = COMP_SHORT_PACKET;
2273                else
2274                        xhci_warn_ratelimited(xhci,
2275                                              "WARN Successful completion on short TX for slot %u ep %u: needs XHCI_TRUST_TX_LENGTH quirk?\n",
2276                                              slot_id, ep_index);
2277        case COMP_SHORT_PACKET:
2278                break;
2279        /* Completion codes for endpoint stopped state */
2280        case COMP_STOPPED:
2281                xhci_dbg(xhci, "Stopped on Transfer TRB for slot %u ep %u\n",
2282                         slot_id, ep_index);
2283                break;
2284        case COMP_STOPPED_LENGTH_INVALID:
2285                xhci_dbg(xhci,
2286                         "Stopped on No-op or Link TRB for slot %u ep %u\n",
2287                         slot_id, ep_index);
2288                break;
2289        case COMP_STOPPED_SHORT_PACKET:
2290                xhci_dbg(xhci,
2291                         "Stopped with short packet transfer detected for slot %u ep %u\n",
2292                         slot_id, ep_index);
2293                break;
2294        /* Completion codes for endpoint halted state */
2295        case COMP_STALL_ERROR:
2296                xhci_dbg(xhci, "Stalled endpoint for slot %u ep %u\n", slot_id,
2297                         ep_index);
2298                ep->ep_state |= EP_HALTED;
2299                status = -EPIPE;
2300                break;
2301        case COMP_SPLIT_TRANSACTION_ERROR:
2302        case COMP_USB_TRANSACTION_ERROR:
2303                xhci_dbg(xhci, "Transfer error for slot %u ep %u on endpoint\n",
2304                         slot_id, ep_index);
2305                status = -EPROTO;
2306                break;
2307        case COMP_BABBLE_DETECTED_ERROR:
2308                xhci_dbg(xhci, "Babble error for slot %u ep %u on endpoint\n",
2309                         slot_id, ep_index);
2310                status = -EOVERFLOW;
2311                break;
2312        /* Completion codes for endpoint error state */
2313        case COMP_TRB_ERROR:
2314                xhci_warn(xhci,
2315                          "WARN: TRB error for slot %u ep %u on endpoint\n",
2316                          slot_id, ep_index);
2317                status = -EILSEQ;
2318                break;
2319        /* completion codes not indicating endpoint state change */
2320        case COMP_DATA_BUFFER_ERROR:
2321                xhci_warn(xhci,
2322                          "WARN: HC couldn't access mem fast enough for slot %u ep %u\n",
2323                          slot_id, ep_index);
2324                status = -ENOSR;
2325                break;
2326        case COMP_BANDWIDTH_OVERRUN_ERROR:
2327                xhci_warn(xhci,
2328                          "WARN: bandwidth overrun event for slot %u ep %u on endpoint\n",
2329                          slot_id, ep_index);
2330                break;
2331        case COMP_ISOCH_BUFFER_OVERRUN:
2332                xhci_warn(xhci,
2333                          "WARN: buffer overrun event for slot %u ep %u on endpoint",
2334                          slot_id, ep_index);
2335                break;
2336        case COMP_RING_UNDERRUN:
2337                /*
2338                 * When the Isoch ring is empty, the xHC will generate
2339                 * a Ring Overrun Event for IN Isoch endpoint or Ring
2340                 * Underrun Event for OUT Isoch endpoint.
2341                 */
2342                xhci_dbg(xhci, "underrun event on endpoint\n");
2343                if (!list_empty(&ep_ring->td_list))
2344                        xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2345                                        "still with TDs queued?\n",
2346                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2347                                 ep_index);
2348                goto cleanup;
2349        case COMP_RING_OVERRUN:
2350                xhci_dbg(xhci, "overrun event on endpoint\n");
2351                if (!list_empty(&ep_ring->td_list))
2352                        xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2353                                        "still with TDs queued?\n",
2354                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2355                                 ep_index);
2356                goto cleanup;
2357        case COMP_MISSED_SERVICE_ERROR:
2358                /*
2359                 * When encounter missed service error, one or more isoc tds
2360                 * may be missed by xHC.
2361                 * Set skip flag of the ep_ring; Complete the missed tds as
2362                 * short transfer when process the ep_ring next time.
2363                 */
2364                ep->skip = true;
2365                xhci_dbg(xhci,
2366                         "Miss service interval error for slot %u ep %u, set skip flag\n",
2367                         slot_id, ep_index);
2368                goto cleanup;
2369        case COMP_NO_PING_RESPONSE_ERROR:
2370                ep->skip = true;
2371                xhci_dbg(xhci,
2372                         "No Ping response error for slot %u ep %u, Skip one Isoc TD\n",
2373                         slot_id, ep_index);
2374                goto cleanup;
2375
2376        case COMP_INCOMPATIBLE_DEVICE_ERROR:
2377                /* needs disable slot command to recover */
2378                xhci_warn(xhci,
2379                          "WARN: detect an incompatible device for slot %u ep %u",
2380                          slot_id, ep_index);
2381                status = -EPROTO;
2382                break;
2383        default:
2384                if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2385                        status = 0;
2386                        break;
2387                }
2388                xhci_warn(xhci,
2389                          "ERROR Unknown event condition %u for slot %u ep %u , HC probably busted\n",
2390                          trb_comp_code, slot_id, ep_index);
2391                goto cleanup;
2392        }
2393
2394        do {
2395                /* This TRB should be in the TD at the head of this ring's
2396                 * TD list.
2397                 */
2398                if (list_empty(&ep_ring->td_list)) {
2399                        /*
2400                         * Don't print wanings if it's due to a stopped endpoint
2401                         * generating an extra completion event if the device
2402                         * was suspended. Or, a event for the last TRB of a
2403                         * short TD we already got a short event for.
2404                         * The short TD is already removed from the TD list.
2405                         */
2406
2407                        if (!(trb_comp_code == COMP_STOPPED ||
2408                              trb_comp_code == COMP_STOPPED_LENGTH_INVALID ||
2409                              ep_ring->last_td_was_short)) {
2410                                xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2411                                                TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2412                                                ep_index);
2413                        }
2414                        if (ep->skip) {
2415                                ep->skip = false;
2416                                xhci_dbg(xhci, "td_list is empty while skip flag set. Clear skip flag for slot %u ep %u.\n",
2417                                         slot_id, ep_index);
2418                        }
2419                        goto cleanup;
2420                }
2421
2422                /* We've skipped all the TDs on the ep ring when ep->skip set */
2423                if (ep->skip && td_num == 0) {
2424                        ep->skip = false;
2425                        xhci_dbg(xhci, "All tds on the ep_ring skipped. Clear skip flag for slot %u ep %u.\n",
2426                                 slot_id, ep_index);
2427                        goto cleanup;
2428                }
2429
2430                td = list_first_entry(&ep_ring->td_list, struct xhci_td,
2431                                      td_list);
2432                if (ep->skip)
2433                        td_num--;
2434
2435                /* Is this a TRB in the currently executing TD? */
2436                ep_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2437                                td->last_trb, ep_trb_dma, false);
2438
2439                /*
2440                 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2441                 * is not in the current TD pointed by ep_ring->dequeue because
2442                 * that the hardware dequeue pointer still at the previous TRB
2443                 * of the current TD. The previous TRB maybe a Link TD or the
2444                 * last TRB of the previous TD. The command completion handle
2445                 * will take care the rest.
2446                 */
2447                if (!ep_seg && (trb_comp_code == COMP_STOPPED ||
2448                           trb_comp_code == COMP_STOPPED_LENGTH_INVALID)) {
2449                        goto cleanup;
2450                }
2451
2452                if (!ep_seg) {
2453                        if (!ep->skip ||
2454                            !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2455                                /* Some host controllers give a spurious
2456                                 * successful event after a short transfer.
2457                                 * Ignore it.
2458                                 */
2459                                if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2460                                                ep_ring->last_td_was_short) {
2461                                        ep_ring->last_td_was_short = false;
2462                                        goto cleanup;
2463                                }
2464                                /* HC is busted, give up! */
2465                                xhci_err(xhci,
2466                                        "ERROR Transfer event TRB DMA ptr not "
2467                                        "part of current TD ep_index %d "
2468                                        "comp_code %u\n", ep_index,
2469                                        trb_comp_code);
2470                                trb_in_td(xhci, ep_ring->deq_seg,
2471                                          ep_ring->dequeue, td->last_trb,
2472                                          ep_trb_dma, true);
2473                                return -ESHUTDOWN;
2474                        }
2475
2476                        skip_isoc_td(xhci, td, event, ep, &status);
2477                        goto cleanup;
2478                }
2479                if (trb_comp_code == COMP_SHORT_PACKET)
2480                        ep_ring->last_td_was_short = true;
2481                else
2482                        ep_ring->last_td_was_short = false;
2483
2484                if (ep->skip) {
2485                        xhci_dbg(xhci,
2486                                 "Found td. Clear skip flag for slot %u ep %u.\n",
2487                                 slot_id, ep_index);
2488                        ep->skip = false;
2489                }
2490
2491                ep_trb = &ep_seg->trbs[(ep_trb_dma - ep_seg->dma) /
2492                                                sizeof(*ep_trb)];
2493
2494                trace_xhci_handle_transfer(ep_ring,
2495                                (struct xhci_generic_trb *) ep_trb);
2496
2497                /*
2498                 * No-op TRB could trigger interrupts in a case where
2499                 * a URB was killed and a STALL_ERROR happens right
2500                 * after the endpoint ring stopped. Reset the halted
2501                 * endpoint. Otherwise, the endpoint remains stalled
2502                 * indefinitely.
2503                 */
2504                if (trb_is_noop(ep_trb)) {
2505                        if (trb_comp_code == COMP_STALL_ERROR ||
2506                            xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
2507                                                              trb_comp_code))
2508                                xhci_cleanup_halted_endpoint(xhci, slot_id,
2509                                                             ep_index,
2510                                                             ep_ring->stream_id,
2511                                                             td, EP_HARD_RESET);
2512                        goto cleanup;
2513                }
2514
2515                /* update the urb's actual_length and give back to the core */
2516                if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2517                        process_ctrl_td(xhci, td, ep_trb, event, ep, &status);
2518                else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2519                        process_isoc_td(xhci, td, ep_trb, event, ep, &status);
2520                else
2521                        process_bulk_intr_td(xhci, td, ep_trb, event, ep,
2522                                             &status);
2523cleanup:
2524                handling_skipped_tds = ep->skip &&
2525                        trb_comp_code != COMP_MISSED_SERVICE_ERROR &&
2526                        trb_comp_code != COMP_NO_PING_RESPONSE_ERROR;
2527
2528                /*
2529                 * Do not update event ring dequeue pointer if we're in a loop
2530                 * processing missed tds.
2531                 */
2532                if (!handling_skipped_tds)
2533                        inc_deq(xhci, xhci->event_ring);
2534
2535        /*
2536         * If ep->skip is set, it means there are missed tds on the
2537         * endpoint ring need to take care of.
2538         * Process them as short transfer until reach the td pointed by
2539         * the event.
2540         */
2541        } while (handling_skipped_tds);
2542
2543        return 0;
2544
2545err_out:
2546        xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2547                 (unsigned long long) xhci_trb_virt_to_dma(
2548                         xhci->event_ring->deq_seg,
2549                         xhci->event_ring->dequeue),
2550                 lower_32_bits(le64_to_cpu(event->buffer)),
2551                 upper_32_bits(le64_to_cpu(event->buffer)),
2552                 le32_to_cpu(event->transfer_len),
2553                 le32_to_cpu(event->flags));
2554        return -ENODEV;
2555}
2556
2557/*
2558 * This function handles all OS-owned events on the event ring.  It may drop
2559 * xhci->lock between event processing (e.g. to pass up port status changes).
2560 * Returns >0 for "possibly more events to process" (caller should call again),
2561 * otherwise 0 if done.  In future, <0 returns should indicate error code.
2562 */
2563static int xhci_handle_event(struct xhci_hcd *xhci)
2564{
2565        union xhci_trb *event;
2566        int update_ptrs = 1;
2567        int ret;
2568
2569        /* Event ring hasn't been allocated yet. */
2570        if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2571                xhci_err(xhci, "ERROR event ring not ready\n");
2572                return -ENOMEM;
2573        }
2574
2575        event = xhci->event_ring->dequeue;
2576        /* Does the HC or OS own the TRB? */
2577        if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2578            xhci->event_ring->cycle_state)
2579                return 0;
2580
2581        trace_xhci_handle_event(xhci->event_ring, &event->generic);
2582
2583        /*
2584         * Barrier between reading the TRB_CYCLE (valid) flag above and any
2585         * speculative reads of the event's flags/data below.
2586         */
2587        rmb();
2588        /* FIXME: Handle more event types. */
2589        switch (le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) {
2590        case TRB_TYPE(TRB_COMPLETION):
2591                handle_cmd_completion(xhci, &event->event_cmd);
2592                break;
2593        case TRB_TYPE(TRB_PORT_STATUS):
2594                handle_port_status(xhci, event);
2595                update_ptrs = 0;
2596                break;
2597        case TRB_TYPE(TRB_TRANSFER):
2598                ret = handle_tx_event(xhci, &event->trans_event);
2599                if (ret >= 0)
2600                        update_ptrs = 0;
2601                break;
2602        case TRB_TYPE(TRB_DEV_NOTE):
2603                handle_device_notification(xhci, event);
2604                break;
2605        default:
2606                if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2607                    TRB_TYPE(48))
2608                        handle_vendor_event(xhci, event);
2609                else
2610                        xhci_warn(xhci, "ERROR unknown event type %d\n",
2611                                  TRB_FIELD_TO_TYPE(
2612                                  le32_to_cpu(event->event_cmd.flags)));
2613        }
2614        /* Any of the above functions may drop and re-acquire the lock, so check
2615         * to make sure a watchdog timer didn't mark the host as non-responsive.
2616         */
2617        if (xhci->xhc_state & XHCI_STATE_DYING) {
2618                xhci_dbg(xhci, "xHCI host dying, returning from "
2619                                "event handler.\n");
2620                return 0;
2621        }
2622
2623        if (update_ptrs)
2624                /* Update SW event ring dequeue pointer */
2625                inc_deq(xhci, xhci->event_ring);
2626
2627        /* Are there more items on the event ring?  Caller will call us again to
2628         * check.
2629         */
2630        return 1;
2631}
2632
2633/*
2634 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2635 * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2636 * indicators of an event TRB error, but we check the status *first* to be safe.
2637 */
2638irqreturn_t xhci_irq(struct usb_hcd *hcd)
2639{
2640        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2641        union xhci_trb *event_ring_deq;
2642        irqreturn_t ret = IRQ_NONE;
2643        unsigned long flags;
2644        dma_addr_t deq;
2645        u64 temp_64;
2646        u32 status;
2647
2648        spin_lock_irqsave(&xhci->lock, flags);
2649        /* Check if the xHC generated the interrupt, or the irq is shared */
2650        status = readl(&xhci->op_regs->status);
2651        if (status == ~(u32)0) {
2652                xhci_hc_died(xhci);
2653                ret = IRQ_HANDLED;
2654                goto out;
2655        }
2656
2657        if (!(status & STS_EINT))
2658                goto out;
2659
2660        if (status & STS_FATAL) {
2661                xhci_warn(xhci, "WARNING: Host System Error\n");
2662                xhci_halt(xhci);
2663                ret = IRQ_HANDLED;
2664                goto out;
2665        }
2666
2667        /*
2668         * Clear the op reg interrupt status first,
2669         * so we can receive interrupts from other MSI-X interrupters.
2670         * Write 1 to clear the interrupt status.
2671         */
2672        status |= STS_EINT;
2673        writel(status, &xhci->op_regs->status);
2674
2675        if (!hcd->msi_enabled) {
2676                u32 irq_pending;
2677                irq_pending = readl(&xhci->ir_set->irq_pending);
2678                irq_pending |= IMAN_IP;
2679                writel(irq_pending, &xhci->ir_set->irq_pending);
2680        }
2681
2682        if (xhci->xhc_state & XHCI_STATE_DYING ||
2683            xhci->xhc_state & XHCI_STATE_HALTED) {
2684                xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2685                                "Shouldn't IRQs be disabled?\n");
2686                /* Clear the event handler busy flag (RW1C);
2687                 * the event ring should be empty.
2688                 */
2689                temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2690                xhci_write_64(xhci, temp_64 | ERST_EHB,
2691                                &xhci->ir_set->erst_dequeue);
2692                ret = IRQ_HANDLED;
2693                goto out;
2694        }
2695
2696        event_ring_deq = xhci->event_ring->dequeue;
2697        /* FIXME this should be a delayed service routine
2698         * that clears the EHB.
2699         */
2700        while (xhci_handle_event(xhci) > 0) {}
2701
2702        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2703        /* If necessary, update the HW's version of the event ring deq ptr. */
2704        if (event_ring_deq != xhci->event_ring->dequeue) {
2705                deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2706                                xhci->event_ring->dequeue);
2707                if (deq == 0)
2708                        xhci_warn(xhci, "WARN something wrong with SW event "
2709                                        "ring dequeue ptr.\n");
2710                /* Update HC event ring dequeue pointer */
2711                temp_64 &= ERST_PTR_MASK;
2712                temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2713        }
2714
2715        /* Clear the event handler busy flag (RW1C); event ring is empty. */
2716        temp_64 |= ERST_EHB;
2717        xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2718        ret = IRQ_HANDLED;
2719
2720out:
2721        spin_unlock_irqrestore(&xhci->lock, flags);
2722
2723        return ret;
2724}
2725
2726irqreturn_t xhci_msi_irq(int irq, void *hcd)
2727{
2728        return xhci_irq(hcd);
2729}
2730
2731/****           Endpoint Ring Operations        ****/
2732
2733/*
2734 * Generic function for queueing a TRB on a ring.
2735 * The caller must have checked to make sure there's room on the ring.
2736 *
2737 * @more_trbs_coming:   Will you enqueue more TRBs before calling
2738 *                      prepare_transfer()?
2739 */
2740static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2741                bool more_trbs_coming,
2742                u32 field1, u32 field2, u32 field3, u32 field4)
2743{
2744        struct xhci_generic_trb *trb;
2745
2746        trb = &ring->enqueue->generic;
2747        trb->field[0] = cpu_to_le32(field1);
2748        trb->field[1] = cpu_to_le32(field2);
2749        trb->field[2] = cpu_to_le32(field3);
2750        trb->field[3] = cpu_to_le32(field4);
2751
2752        trace_xhci_queue_trb(ring, trb);
2753
2754        inc_enq(xhci, ring, more_trbs_coming);
2755}
2756
2757/*
2758 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2759 * FIXME allocate segments if the ring is full.
2760 */
2761static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2762                u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2763{
2764        unsigned int num_trbs_needed;
2765
2766        /* Make sure the endpoint has been added to xHC schedule */
2767        switch (ep_state) {
2768        case EP_STATE_DISABLED:
2769                /*
2770                 * USB core changed config/interfaces without notifying us,
2771                 * or hardware is reporting the wrong state.
2772                 */
2773                xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2774                return -ENOENT;
2775        case EP_STATE_ERROR:
2776                xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2777                /* FIXME event handling code for error needs to clear it */
2778                /* XXX not sure if this should be -ENOENT or not */
2779                return -EINVAL;
2780        case EP_STATE_HALTED:
2781                xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2782        case EP_STATE_STOPPED:
2783        case EP_STATE_RUNNING:
2784                break;
2785        default:
2786                xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2787                /*
2788                 * FIXME issue Configure Endpoint command to try to get the HC
2789                 * back into a known state.
2790                 */
2791                return -EINVAL;
2792        }
2793
2794        while (1) {
2795                if (room_on_ring(xhci, ep_ring, num_trbs))
2796                        break;
2797
2798                if (ep_ring == xhci->cmd_ring) {
2799                        xhci_err(xhci, "Do not support expand command ring\n");
2800                        return -ENOMEM;
2801                }
2802
2803                xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2804                                "ERROR no room on ep ring, try ring expansion");
2805                num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2806                if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2807                                        mem_flags)) {
2808                        xhci_err(xhci, "Ring expansion failed\n");
2809                        return -ENOMEM;
2810                }
2811        }
2812
2813        while (trb_is_link(ep_ring->enqueue)) {
2814                /* If we're not dealing with 0.95 hardware or isoc rings
2815                 * on AMD 0.96 host, clear the chain bit.
2816                 */
2817                if (!xhci_link_trb_quirk(xhci) &&
2818                    !(ep_ring->type == TYPE_ISOC &&
2819                      (xhci->quirks & XHCI_AMD_0x96_HOST)))
2820                        ep_ring->enqueue->link.control &=
2821                                cpu_to_le32(~TRB_CHAIN);
2822                else
2823                        ep_ring->enqueue->link.control |=
2824                                cpu_to_le32(TRB_CHAIN);
2825
2826                wmb();
2827                ep_ring->enqueue->link.control ^= cpu_to_le32(TRB_CYCLE);
2828
2829                /* Toggle the cycle bit after the last ring segment. */
2830                if (link_trb_toggles_cycle(ep_ring->enqueue))
2831                        ep_ring->cycle_state ^= 1;
2832
2833                ep_ring->enq_seg = ep_ring->enq_seg->next;
2834                ep_ring->enqueue = ep_ring->enq_seg->trbs;
2835        }
2836        return 0;
2837}
2838
2839static int prepare_transfer(struct xhci_hcd *xhci,
2840                struct xhci_virt_device *xdev,
2841                unsigned int ep_index,
2842                unsigned int stream_id,
2843                unsigned int num_trbs,
2844                struct urb *urb,
2845                unsigned int td_index,
2846                gfp_t mem_flags)
2847{
2848        int ret;
2849        struct urb_priv *urb_priv;
2850        struct xhci_td  *td;
2851        struct xhci_ring *ep_ring;
2852        struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2853
2854        ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2855        if (!ep_ring) {
2856                xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2857                                stream_id);
2858                return -EINVAL;
2859        }
2860
2861        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
2862                           num_trbs, mem_flags);
2863        if (ret)
2864                return ret;
2865
2866        urb_priv = urb->hcpriv;
2867        td = &urb_priv->td[td_index];
2868
2869        INIT_LIST_HEAD(&td->td_list);
2870        INIT_LIST_HEAD(&td->cancelled_td_list);
2871
2872        if (td_index == 0) {
2873                ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2874                if (unlikely(ret))
2875                        return ret;
2876        }
2877
2878        td->urb = urb;
2879        /* Add this TD to the tail of the endpoint ring's TD list */
2880        list_add_tail(&td->td_list, &ep_ring->td_list);
2881        td->start_seg = ep_ring->enq_seg;
2882        td->first_trb = ep_ring->enqueue;
2883
2884        return 0;
2885}
2886
2887unsigned int count_trbs(u64 addr, u64 len)
2888{
2889        unsigned int num_trbs;
2890
2891        num_trbs = DIV_ROUND_UP(len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
2892                        TRB_MAX_BUFF_SIZE);
2893        if (num_trbs == 0)
2894                num_trbs++;
2895
2896        return num_trbs;
2897}
2898
2899static inline unsigned int count_trbs_needed(struct urb *urb)
2900{
2901        return count_trbs(urb->transfer_dma, urb->transfer_buffer_length);
2902}
2903
2904static unsigned int count_sg_trbs_needed(struct urb *urb)
2905{
2906        struct scatterlist *sg;
2907        unsigned int i, len, full_len, num_trbs = 0;
2908
2909        full_len = urb->transfer_buffer_length;
2910
2911        for_each_sg(urb->sg, sg, urb->num_mapped_sgs, i) {
2912                len = sg_dma_len(sg);
2913                num_trbs += count_trbs(sg_dma_address(sg), len);
2914                len = min_t(unsigned int, len, full_len);
2915                full_len -= len;
2916                if (full_len == 0)
2917                        break;
2918        }
2919
2920        return num_trbs;
2921}
2922
2923static unsigned int count_isoc_trbs_needed(struct urb *urb, int i)
2924{
2925        u64 addr, len;
2926
2927        addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
2928        len = urb->iso_frame_desc[i].length;
2929
2930        return count_trbs(addr, len);
2931}
2932
2933static void check_trb_math(struct urb *urb, int running_total)
2934{
2935        if (unlikely(running_total != urb->transfer_buffer_length))
2936                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2937                                "queued %#x (%d), asked for %#x (%d)\n",
2938                                __func__,
2939                                urb->ep->desc.bEndpointAddress,
2940                                running_total, running_total,
2941                                urb->transfer_buffer_length,
2942                                urb->transfer_buffer_length);
2943}
2944
2945static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2946                unsigned int ep_index, unsigned int stream_id, int start_cycle,
2947                struct xhci_generic_trb *start_trb)
2948{
2949        /*
2950         * Pass all the TRBs to the hardware at once and make sure this write
2951         * isn't reordered.
2952         */
2953        wmb();
2954        if (start_cycle)
2955                start_trb->field[3] |= cpu_to_le32(start_cycle);
2956        else
2957                start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2958        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2959}
2960
2961static void check_interval(struct xhci_hcd *xhci, struct urb *urb,
2962                                                struct xhci_ep_ctx *ep_ctx)
2963{
2964        int xhci_interval;
2965        int ep_interval;
2966
2967        xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2968        ep_interval = urb->interval;
2969
2970        /* Convert to microframes */
2971        if (urb->dev->speed == USB_SPEED_LOW ||
2972                        urb->dev->speed == USB_SPEED_FULL)
2973                ep_interval *= 8;
2974
2975        /* FIXME change this to a warning and a suggestion to use the new API
2976         * to set the polling interval (once the API is added).
2977         */
2978        if (xhci_interval != ep_interval) {
2979                dev_dbg_ratelimited(&urb->dev->dev,
2980                                "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
2981                                ep_interval, ep_interval == 1 ? "" : "s",
2982                                xhci_interval, xhci_interval == 1 ? "" : "s");
2983                urb->interval = xhci_interval;
2984                /* Convert back to frames for LS/FS devices */
2985                if (urb->dev->speed == USB_SPEED_LOW ||
2986                                urb->dev->speed == USB_SPEED_FULL)
2987                        urb->interval /= 8;
2988        }
2989}
2990
2991/*
2992 * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2993 * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2994 * (comprised of sg list entries) can take several service intervals to
2995 * transmit.
2996 */
2997int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2998                struct urb *urb, int slot_id, unsigned int ep_index)
2999{
3000        struct xhci_ep_ctx *ep_ctx;
3001
3002        ep_ctx = xhci_get_ep_ctx(xhci, xhci->devs[slot_id]->out_ctx, ep_index);
3003        check_interval(xhci, urb, ep_ctx);
3004
3005        return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3006}
3007
3008/*
3009 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3010 * packets remaining in the TD (*not* including this TRB).
3011 *
3012 * Total TD packet count = total_packet_count =
3013 *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3014 *
3015 * Packets transferred up to and including this TRB = packets_transferred =
3016 *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3017 *
3018 * TD size = total_packet_count - packets_transferred
3019 *
3020 * For xHCI 0.96 and older, TD size field should be the remaining bytes
3021 * including this TRB, right shifted by 10
3022 *
3023 * For all hosts it must fit in bits 21:17, so it can't be bigger than 31.
3024 * This is taken care of in the TRB_TD_SIZE() macro
3025 *
3026 * The last TRB in a TD must have the TD size set to zero.
3027 */
3028static u32 xhci_td_remainder(struct xhci_hcd *xhci, int transferred,
3029                              int trb_buff_len, unsigned int td_total_len,
3030                              struct urb *urb, bool more_trbs_coming)
3031{
3032        u32 maxp, total_packet_count;
3033
3034        /* MTK xHCI 0.96 contains some features from 1.0 */
3035        if (xhci->hci_version < 0x100 && !(xhci->quirks & XHCI_MTK_HOST))
3036                return ((td_total_len - transferred) >> 10);
3037
3038        /* One TRB with a zero-length data packet. */
3039        if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) ||
3040            trb_buff_len == td_total_len)
3041                return 0;
3042
3043        /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */
3044        if ((xhci->quirks & XHCI_MTK_HOST) && (xhci->hci_version < 0x100))
3045                trb_buff_len = 0;
3046
3047        maxp = usb_endpoint_maxp(&urb->ep->desc);
3048        total_packet_count = DIV_ROUND_UP(td_total_len, maxp);
3049
3050        /* Queueing functions don't count the current TRB into transferred */
3051        return (total_packet_count - ((transferred + trb_buff_len) / maxp));
3052}
3053
3054
3055static int xhci_align_td(struct xhci_hcd *xhci, struct urb *urb, u32 enqd_len,
3056                         u32 *trb_buff_len, struct xhci_segment *seg)
3057{
3058        struct device *dev = xhci_to_hcd(xhci)->self.controller;
3059        unsigned int unalign;
3060        unsigned int max_pkt;
3061        u32 new_buff_len;
3062
3063        max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3064        unalign = (enqd_len + *trb_buff_len) % max_pkt;
3065
3066        /* we got lucky, last normal TRB data on segment is packet aligned */
3067        if (unalign == 0)
3068                return 0;
3069
3070        xhci_dbg(xhci, "Unaligned %d bytes, buff len %d\n",
3071                 unalign, *trb_buff_len);
3072
3073        /* is the last nornal TRB alignable by splitting it */
3074        if (*trb_buff_len > unalign) {
3075                *trb_buff_len -= unalign;
3076                xhci_dbg(xhci, "split align, new buff len %d\n", *trb_buff_len);
3077                return 0;
3078        }
3079
3080        /*
3081         * We want enqd_len + trb_buff_len to sum up to a number aligned to
3082         * number which is divisible by the endpoint's wMaxPacketSize. IOW:
3083         * (size of currently enqueued TRBs + remainder) % wMaxPacketSize == 0.
3084         */
3085        new_buff_len = max_pkt - (enqd_len % max_pkt);
3086
3087        if (new_buff_len > (urb->transfer_buffer_length - enqd_len))
3088                new_buff_len = (urb->transfer_buffer_length - enqd_len);
3089
3090        /* create a max max_pkt sized bounce buffer pointed to by last trb */
3091        if (usb_urb_dir_out(urb)) {
3092                sg_pcopy_to_buffer(urb->sg, urb->num_mapped_sgs,
3093                                   seg->bounce_buf, new_buff_len, enqd_len);
3094                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3095                                                 max_pkt, DMA_TO_DEVICE);
3096        } else {
3097                seg->bounce_dma = dma_map_single(dev, seg->bounce_buf,
3098                                                 max_pkt, DMA_FROM_DEVICE);
3099        }
3100
3101        if (dma_mapping_error(dev, seg->bounce_dma)) {
3102                /* try without aligning. Some host controllers survive */
3103                xhci_warn(xhci, "Failed mapping bounce buffer, not aligning\n");
3104                return 0;
3105        }
3106        *trb_buff_len = new_buff_len;
3107        seg->bounce_len = new_buff_len;
3108        seg->bounce_offs = enqd_len;
3109
3110        xhci_dbg(xhci, "Bounce align, new buff len %d\n", *trb_buff_len);
3111
3112        return 1;
3113}
3114
3115/* This is very similar to what ehci-q.c qtd_fill() does */
3116int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3117                struct urb *urb, int slot_id, unsigned int ep_index)
3118{
3119        struct xhci_ring *ring;
3120        struct urb_priv *urb_priv;
3121        struct xhci_td *td;
3122        struct xhci_generic_trb *start_trb;
3123        struct scatterlist *sg = NULL;
3124        bool more_trbs_coming = true;
3125        bool need_zero_pkt = false;
3126        bool first_trb = true;
3127        unsigned int num_trbs;
3128        unsigned int start_cycle, num_sgs = 0;
3129        unsigned int enqd_len, block_len, trb_buff_len, full_len;
3130        int sent_len, ret;
3131        u32 field, length_field, remainder;
3132        u64 addr, send_addr;
3133
3134        ring = xhci_urb_to_transfer_ring(xhci, urb);
3135        if (!ring)
3136                return -EINVAL;
3137
3138        full_len = urb->transfer_buffer_length;
3139        /* If we have scatter/gather list, we use it. */
3140        if (urb->num_sgs) {
3141                num_sgs = urb->num_mapped_sgs;
3142                sg = urb->sg;
3143                addr = (u64) sg_dma_address(sg);
3144                block_len = sg_dma_len(sg);
3145                num_trbs = count_sg_trbs_needed(urb);
3146        } else {
3147                num_trbs = count_trbs_needed(urb);
3148                addr = (u64) urb->transfer_dma;
3149                block_len = full_len;
3150        }
3151        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3152                        ep_index, urb->stream_id,
3153                        num_trbs, urb, 0, mem_flags);
3154        if (unlikely(ret < 0))
3155                return ret;
3156
3157        urb_priv = urb->hcpriv;
3158
3159        /* Deal with URB_ZERO_PACKET - need one more td/trb */
3160        if (urb->transfer_flags & URB_ZERO_PACKET && urb_priv->num_tds > 1)
3161                need_zero_pkt = true;
3162
3163        td = &urb_priv->td[0];
3164
3165        /*
3166         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3167         * until we've finished creating all the other TRBs.  The ring's cycle
3168         * state may change as we enqueue the other TRBs, so save it too.
3169         */
3170        start_trb = &ring->enqueue->generic;
3171        start_cycle = ring->cycle_state;
3172        send_addr = addr;
3173
3174        /* Queue the TRBs, even if they are zero-length */
3175        for (enqd_len = 0; first_trb || enqd_len < full_len;
3176                        enqd_len += trb_buff_len) {
3177                field = TRB_TYPE(TRB_NORMAL);
3178
3179                /* TRB buffer should not cross 64KB boundaries */
3180                trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3181                trb_buff_len = min_t(unsigned int, trb_buff_len, block_len);
3182
3183                if (enqd_len + trb_buff_len > full_len)
3184                        trb_buff_len = full_len - enqd_len;
3185
3186                /* Don't change the cycle bit of the first TRB until later */
3187                if (first_trb) {
3188                        first_trb = false;
3189                        if (start_cycle == 0)
3190                                field |= TRB_CYCLE;
3191                } else
3192                        field |= ring->cycle_state;
3193
3194                /* Chain all the TRBs together; clear the chain bit in the last
3195                 * TRB to indicate it's the last TRB in the chain.
3196                 */
3197                if (enqd_len + trb_buff_len < full_len) {
3198                        field |= TRB_CHAIN;
3199                        if (trb_is_link(ring->enqueue + 1)) {
3200                                if (xhci_align_td(xhci, urb, enqd_len,
3201                                                  &trb_buff_len,
3202                                                  ring->enq_seg)) {
3203                                        send_addr = ring->enq_seg->bounce_dma;
3204                                        /* assuming TD won't span 2 segs */
3205                                        td->bounce_seg = ring->enq_seg;
3206                                }
3207                        }
3208                }
3209                if (enqd_len + trb_buff_len >= full_len) {
3210                        field &= ~TRB_CHAIN;
3211                        field |= TRB_IOC;
3212                        more_trbs_coming = false;
3213                        td->last_trb = ring->enqueue;
3214                }
3215
3216                /* Only set interrupt on short packet for IN endpoints */
3217                if (usb_urb_dir_in(urb))
3218                        field |= TRB_ISP;
3219
3220                /* Set the TRB length, TD size, and interrupter fields. */
3221                remainder = xhci_td_remainder(xhci, enqd_len, trb_buff_len,
3222                                              full_len, urb, more_trbs_coming);
3223
3224                length_field = TRB_LEN(trb_buff_len) |
3225                        TRB_TD_SIZE(remainder) |
3226                        TRB_INTR_TARGET(0);
3227
3228                queue_trb(xhci, ring, more_trbs_coming | need_zero_pkt,
3229                                lower_32_bits(send_addr),
3230                                upper_32_bits(send_addr),
3231                                length_field,
3232                                field);
3233
3234                addr += trb_buff_len;
3235                sent_len = trb_buff_len;
3236
3237                while (sg && sent_len >= block_len) {
3238                        /* New sg entry */
3239                        --num_sgs;
3240                        sent_len -= block_len;
3241                        if (num_sgs != 0) {
3242                                sg = sg_next(sg);
3243                                block_len = sg_dma_len(sg);
3244                                addr = (u64) sg_dma_address(sg);
3245                                addr += sent_len;
3246                        }
3247                }
3248                block_len -= sent_len;
3249                send_addr = addr;
3250        }
3251
3252        if (need_zero_pkt) {
3253                ret = prepare_transfer(xhci, xhci->devs[slot_id],
3254                                       ep_index, urb->stream_id,
3255                                       1, urb, 1, mem_flags);
3256                urb_priv->td[1].last_trb = ring->enqueue;
3257                field = TRB_TYPE(TRB_NORMAL) | ring->cycle_state | TRB_IOC;
3258                queue_trb(xhci, ring, 0, 0, 0, TRB_INTR_TARGET(0), field);
3259        }
3260
3261        check_trb_math(urb, enqd_len);
3262        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3263                        start_cycle, start_trb);
3264        return 0;
3265}
3266
3267/* Caller must have locked xhci->lock */
3268int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3269                struct urb *urb, int slot_id, unsigned int ep_index)
3270{
3271        struct xhci_ring *ep_ring;
3272        int num_trbs;
3273        int ret;
3274        struct usb_ctrlrequest *setup;
3275        struct xhci_generic_trb *start_trb;
3276        int start_cycle;
3277        u32 field;
3278        struct urb_priv *urb_priv;
3279        struct xhci_td *td;
3280
3281        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3282        if (!ep_ring)
3283                return -EINVAL;
3284
3285        /*
3286         * Need to copy setup packet into setup TRB, so we can't use the setup
3287         * DMA address.
3288         */
3289        if (!urb->setup_packet)
3290                return -EINVAL;
3291
3292        /* 1 TRB for setup, 1 for status */
3293        num_trbs = 2;
3294        /*
3295         * Don't need to check if we need additional event data and normal TRBs,
3296         * since data in control transfers will never get bigger than 16MB
3297         * XXX: can we get a buffer that crosses 64KB boundaries?
3298         */
3299        if (urb->transfer_buffer_length > 0)
3300                num_trbs++;
3301        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3302                        ep_index, urb->stream_id,
3303                        num_trbs, urb, 0, mem_flags);
3304        if (ret < 0)
3305                return ret;
3306
3307        urb_priv = urb->hcpriv;
3308        td = &urb_priv->td[0];
3309
3310        /*
3311         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3312         * until we've finished creating all the other TRBs.  The ring's cycle
3313         * state may change as we enqueue the other TRBs, so save it too.
3314         */
3315        start_trb = &ep_ring->enqueue->generic;
3316        start_cycle = ep_ring->cycle_state;
3317
3318        /* Queue setup TRB - see section 6.4.1.2.1 */
3319        /* FIXME better way to translate setup_packet into two u32 fields? */
3320        setup = (struct usb_ctrlrequest *) urb->setup_packet;
3321        field = 0;
3322        field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3323        if (start_cycle == 0)
3324                field |= 0x1;
3325
3326        /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3327        if ((xhci->hci_version >= 0x100) || (xhci->quirks & XHCI_MTK_HOST)) {
3328                if (urb->transfer_buffer_length > 0) {
3329                        if (setup->bRequestType & USB_DIR_IN)
3330                                field |= TRB_TX_TYPE(TRB_DATA_IN);
3331                        else
3332                                field |= TRB_TX_TYPE(TRB_DATA_OUT);
3333                }
3334        }
3335
3336        queue_trb(xhci, ep_ring, true,
3337                  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3338                  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3339                  TRB_LEN(8) | TRB_INTR_TARGET(0),
3340                  /* Immediate data in pointer */
3341                  field);
3342
3343        /* If there's data, queue data TRBs */
3344        /* Only set interrupt on short packet for IN endpoints */
3345        if (usb_urb_dir_in(urb))
3346                field = TRB_ISP | TRB_TYPE(TRB_DATA);
3347        else
3348                field = TRB_TYPE(TRB_DATA);
3349
3350        if (urb->transfer_buffer_length > 0) {
3351                u32 length_field, remainder;
3352
3353                remainder = xhci_td_remainder(xhci, 0,
3354                                urb->transfer_buffer_length,
3355                                urb->transfer_buffer_length,
3356                                urb, 1);
3357                length_field = TRB_LEN(urb->transfer_buffer_length) |
3358                                TRB_TD_SIZE(remainder) |
3359                                TRB_INTR_TARGET(0);
3360                if (setup->bRequestType & USB_DIR_IN)
3361                        field |= TRB_DIR_IN;
3362                queue_trb(xhci, ep_ring, true,
3363                                lower_32_bits(urb->transfer_dma),
3364                                upper_32_bits(urb->transfer_dma),
3365                                length_field,
3366                                field | ep_ring->cycle_state);
3367        }
3368
3369        /* Save the DMA address of the last TRB in the TD */
3370        td->last_trb = ep_ring->enqueue;
3371
3372        /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3373        /* If the device sent data, the status stage is an OUT transfer */
3374        if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3375                field = 0;
3376        else
3377                field = TRB_DIR_IN;
3378        queue_trb(xhci, ep_ring, false,
3379                        0,
3380                        0,
3381                        TRB_INTR_TARGET(0),
3382                        /* Event on completion */
3383                        field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3384
3385        giveback_first_trb(xhci, slot_id, ep_index, 0,
3386                        start_cycle, start_trb);
3387        return 0;
3388}
3389
3390/*
3391 * The transfer burst count field of the isochronous TRB defines the number of
3392 * bursts that are required to move all packets in this TD.  Only SuperSpeed
3393 * devices can burst up to bMaxBurst number of packets per service interval.
3394 * This field is zero based, meaning a value of zero in the field means one
3395 * burst.  Basically, for everything but SuperSpeed devices, this field will be
3396 * zero.  Only xHCI 1.0 host controllers support this field.
3397 */
3398static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3399                struct urb *urb, unsigned int total_packet_count)
3400{
3401        unsigned int max_burst;
3402
3403        if (xhci->hci_version < 0x100 || urb->dev->speed < USB_SPEED_SUPER)
3404                return 0;
3405
3406        max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3407        return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3408}
3409
3410/*
3411 * Returns the number of packets in the last "burst" of packets.  This field is
3412 * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3413 * the last burst packet count is equal to the total number of packets in the
3414 * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3415 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3416 * contain 1 to (bMaxBurst + 1) packets.
3417 */
3418static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3419                struct urb *urb, unsigned int total_packet_count)
3420{
3421        unsigned int max_burst;
3422        unsigned int residue;
3423
3424        if (xhci->hci_version < 0x100)
3425                return 0;
3426
3427        if (urb->dev->speed >= USB_SPEED_SUPER) {
3428                /* bMaxBurst is zero based: 0 means 1 packet per burst */
3429                max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3430                residue = total_packet_count % (max_burst + 1);
3431                /* If residue is zero, the last burst contains (max_burst + 1)
3432                 * number of packets, but the TLBPC field is zero-based.
3433                 */
3434                if (residue == 0)
3435                        return max_burst;
3436                return residue - 1;
3437        }
3438        if (total_packet_count == 0)
3439                return 0;
3440        return total_packet_count - 1;
3441}
3442
3443/*
3444 * Calculates Frame ID field of the isochronous TRB identifies the
3445 * target frame that the Interval associated with this Isochronous
3446 * Transfer Descriptor will start on. Refer to 4.11.2.5 in 1.1 spec.
3447 *
3448 * Returns actual frame id on success, negative value on error.
3449 */
3450static int xhci_get_isoc_frame_id(struct xhci_hcd *xhci,
3451                struct urb *urb, int index)
3452{
3453        int start_frame, ist, ret = 0;
3454        int start_frame_id, end_frame_id, current_frame_id;
3455
3456        if (urb->dev->speed == USB_SPEED_LOW ||
3457                        urb->dev->speed == USB_SPEED_FULL)
3458                start_frame = urb->start_frame + index * urb->interval;
3459        else
3460                start_frame = (urb->start_frame + index * urb->interval) >> 3;
3461
3462        /* Isochronous Scheduling Threshold (IST, bits 0~3 in HCSPARAMS2):
3463         *
3464         * If bit [3] of IST is cleared to '0', software can add a TRB no
3465         * later than IST[2:0] Microframes before that TRB is scheduled to
3466         * be executed.
3467         * If bit [3] of IST is set to '1', software can add a TRB no later
3468         * than IST[2:0] Frames before that TRB is scheduled to be executed.
3469         */
3470        ist = HCS_IST(xhci->hcs_params2) & 0x7;
3471        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3472                ist <<= 3;
3473
3474        /* Software shall not schedule an Isoch TD with a Frame ID value that
3475         * is less than the Start Frame ID or greater than the End Frame ID,
3476         * where:
3477         *
3478         * End Frame ID = (Current MFINDEX register value + 895 ms.) MOD 2048
3479         * Start Frame ID = (Current MFINDEX register value + IST + 1) MOD 2048
3480         *
3481         * Both the End Frame ID and Start Frame ID values are calculated
3482         * in microframes. When software determines the valid Frame ID value;
3483         * The End Frame ID value should be rounded down to the nearest Frame
3484         * boundary, and the Start Frame ID value should be rounded up to the
3485         * nearest Frame boundary.
3486         */
3487        current_frame_id = readl(&xhci->run_regs->microframe_index);
3488        start_frame_id = roundup(current_frame_id + ist + 1, 8);
3489        end_frame_id = rounddown(current_frame_id + 895 * 8, 8);
3490
3491        start_frame &= 0x7ff;
3492        start_frame_id = (start_frame_id >> 3) & 0x7ff;
3493        end_frame_id = (end_frame_id >> 3) & 0x7ff;
3494
3495        xhci_dbg(xhci, "%s: index %d, reg 0x%x start_frame_id 0x%x, end_frame_id 0x%x, start_frame 0x%x\n",
3496                 __func__, index, readl(&xhci->run_regs->microframe_index),
3497                 start_frame_id, end_frame_id, start_frame);
3498
3499        if (start_frame_id < end_frame_id) {
3500                if (start_frame > end_frame_id ||
3501                                start_frame < start_frame_id)
3502                        ret = -EINVAL;
3503        } else if (start_frame_id > end_frame_id) {
3504                if ((start_frame > end_frame_id &&
3505                                start_frame < start_frame_id))
3506                        ret = -EINVAL;
3507        } else {
3508                        ret = -EINVAL;
3509        }
3510
3511        if (index == 0) {
3512                if (ret == -EINVAL || start_frame == start_frame_id) {
3513                        start_frame = start_frame_id + 1;
3514                        if (urb->dev->speed == USB_SPEED_LOW ||
3515                                        urb->dev->speed == USB_SPEED_FULL)
3516                                urb->start_frame = start_frame;
3517                        else
3518                                urb->start_frame = start_frame << 3;
3519                        ret = 0;
3520                }
3521        }
3522
3523        if (ret) {
3524                xhci_warn(xhci, "Frame ID %d (reg %d, index %d) beyond range (%d, %d)\n",
3525                                start_frame, current_frame_id, index,
3526                                start_frame_id, end_frame_id);
3527                xhci_warn(xhci, "Ignore frame ID field, use SIA bit instead\n");
3528                return ret;
3529        }
3530
3531        return start_frame;
3532}
3533
3534/* This is for isoc transfer */
3535static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3536                struct urb *urb, int slot_id, unsigned int ep_index)
3537{
3538        struct xhci_ring *ep_ring;
3539        struct urb_priv *urb_priv;
3540        struct xhci_td *td;
3541        int num_tds, trbs_per_td;
3542        struct xhci_generic_trb *start_trb;
3543        bool first_trb;
3544        int start_cycle;
3545        u32 field, length_field;
3546        int running_total, trb_buff_len, td_len, td_remain_len, ret;
3547        u64 start_addr, addr;
3548        int i, j;
3549        bool more_trbs_coming;
3550        struct xhci_virt_ep *xep;
3551        int frame_id;
3552
3553        xep = &xhci->devs[slot_id]->eps[ep_index];
3554        ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3555
3556        num_tds = urb->number_of_packets;
3557        if (num_tds < 1) {
3558                xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3559                return -EINVAL;
3560        }
3561        start_addr = (u64) urb->transfer_dma;
3562        start_trb = &ep_ring->enqueue->generic;
3563        start_cycle = ep_ring->cycle_state;
3564
3565        urb_priv = urb->hcpriv;
3566        /* Queue the TRBs for each TD, even if they are zero-length */
3567        for (i = 0; i < num_tds; i++) {
3568                unsigned int total_pkt_count, max_pkt;
3569                unsigned int burst_count, last_burst_pkt_count;
3570                u32 sia_frame_id;
3571
3572                first_trb = true;
3573                running_total = 0;
3574                addr = start_addr + urb->iso_frame_desc[i].offset;
3575                td_len = urb->iso_frame_desc[i].length;
3576                td_remain_len = td_len;
3577                max_pkt = usb_endpoint_maxp(&urb->ep->desc);
3578                total_pkt_count = DIV_ROUND_UP(td_len, max_pkt);
3579
3580                /* A zero-length transfer still involves at least one packet. */
3581                if (total_pkt_count == 0)
3582                        total_pkt_count++;
3583                burst_count = xhci_get_burst_count(xhci, urb, total_pkt_count);
3584                last_burst_pkt_count = xhci_get_last_burst_packet_count(xhci,
3585                                                        urb, total_pkt_count);
3586
3587                trbs_per_td = count_isoc_trbs_needed(urb, i);
3588
3589                ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3590                                urb->stream_id, trbs_per_td, urb, i, mem_flags);
3591                if (ret < 0) {
3592                        if (i == 0)
3593                                return ret;
3594                        goto cleanup;
3595                }
3596                td = &urb_priv->td[i];
3597
3598                /* use SIA as default, if frame id is used overwrite it */
3599                sia_frame_id = TRB_SIA;
3600                if (!(urb->transfer_flags & URB_ISO_ASAP) &&
3601                    HCC_CFC(xhci->hcc_params)) {
3602                        frame_id = xhci_get_isoc_frame_id(xhci, urb, i);
3603                        if (frame_id >= 0)
3604                                sia_frame_id = TRB_FRAME_ID(frame_id);
3605                }
3606                /*
3607                 * Set isoc specific data for the first TRB in a TD.
3608                 * Prevent HW from getting the TRBs by keeping the cycle state
3609                 * inverted in the first TDs isoc TRB.
3610                 */
3611                field = TRB_TYPE(TRB_ISOC) |
3612                        TRB_TLBPC(last_burst_pkt_count) |
3613                        sia_frame_id |
3614                        (i ? ep_ring->cycle_state : !start_cycle);
3615
3616                /* xhci 1.1 with ETE uses TD_Size field for TBC, old is Rsvdz */
3617                if (!xep->use_extended_tbc)
3618                        field |= TRB_TBC(burst_count);
3619
3620                /* fill the rest of the TRB fields, and remaining normal TRBs */
3621                for (j = 0; j < trbs_per_td; j++) {
3622                        u32 remainder = 0;
3623
3624                        /* only first TRB is isoc, overwrite otherwise */
3625                        if (!first_trb)
3626                                field = TRB_TYPE(TRB_NORMAL) |
3627                                        ep_ring->cycle_state;
3628
3629                        /* Only set interrupt on short packet for IN EPs */
3630                        if (usb_urb_dir_in(urb))
3631                                field |= TRB_ISP;
3632
3633                        /* Set the chain bit for all except the last TRB  */
3634                        if (j < trbs_per_td - 1) {
3635                                more_trbs_coming = true;
3636                                field |= TRB_CHAIN;
3637                        } else {
3638                                more_trbs_coming = false;
3639                                td->last_trb = ep_ring->enqueue;
3640                                field |= TRB_IOC;
3641                                /* set BEI, except for the last TD */
3642                                if (xhci->hci_version >= 0x100 &&
3643                                    !(xhci->quirks & XHCI_AVOID_BEI) &&
3644                                    i < num_tds - 1)
3645                                        field |= TRB_BEI;
3646                        }
3647                        /* Calculate TRB length */
3648                        trb_buff_len = TRB_BUFF_LEN_UP_TO_BOUNDARY(addr);
3649                        if (trb_buff_len > td_remain_len)
3650                                trb_buff_len = td_remain_len;
3651
3652                        /* Set the TRB length, TD size, & interrupter fields. */
3653                        remainder = xhci_td_remainder(xhci, running_total,
3654                                                   trb_buff_len, td_len,
3655                                                   urb, more_trbs_coming);
3656
3657                        length_field = TRB_LEN(trb_buff_len) |
3658                                TRB_INTR_TARGET(0);
3659
3660                        /* xhci 1.1 with ETE uses TD Size field for TBC */
3661                        if (first_trb && xep->use_extended_tbc)
3662                                length_field |= TRB_TD_SIZE_TBC(burst_count);
3663                        else
3664                                length_field |= TRB_TD_SIZE(remainder);
3665                        first_trb = false;
3666
3667                        queue_trb(xhci, ep_ring, more_trbs_coming,
3668                                lower_32_bits(addr),
3669                                upper_32_bits(addr),
3670                                length_field,
3671                                field);
3672                        running_total += trb_buff_len;
3673
3674                        addr += trb_buff_len;
3675                        td_remain_len -= trb_buff_len;
3676                }
3677
3678                /* Check TD length */
3679                if (running_total != td_len) {
3680                        xhci_err(xhci, "ISOC TD length unmatch\n");
3681                        ret = -EINVAL;
3682                        goto cleanup;
3683                }
3684        }
3685
3686        /* store the next frame id */
3687        if (HCC_CFC(xhci->hcc_params))
3688                xep->next_frame_id = urb->start_frame + num_tds * urb->interval;
3689
3690        if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3691                if (xhci->quirks & XHCI_AMD_PLL_FIX)
3692                        usb_amd_quirk_pll_disable();
3693        }
3694        xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3695
3696        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3697                        start_cycle, start_trb);
3698        return 0;
3699cleanup:
3700        /* Clean up a partially enqueued isoc transfer. */
3701
3702        for (i--; i >= 0; i--)
3703                list_del_init(&urb_priv->td[i].td_list);
3704
3705        /* Use the first TD as a temporary variable to turn the TDs we've queued
3706         * into No-ops with a software-owned cycle bit. That way the hardware
3707         * won't accidentally start executing bogus TDs when we partially
3708         * overwrite them.  td->first_trb and td->start_seg are already set.
3709         */
3710        urb_priv->td[0].last_trb = ep_ring->enqueue;
3711        /* Every TRB except the first & last will have its cycle bit flipped. */
3712        td_to_noop(xhci, ep_ring, &urb_priv->td[0], true);
3713
3714        /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3715        ep_ring->enqueue = urb_priv->td[0].first_trb;
3716        ep_ring->enq_seg = urb_priv->td[0].start_seg;
3717        ep_ring->cycle_state = start_cycle;
3718        ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3719        usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3720        return ret;
3721}
3722
3723/*
3724 * Check transfer ring to guarantee there is enough room for the urb.
3725 * Update ISO URB start_frame and interval.
3726 * Update interval as xhci_queue_intr_tx does. Use xhci frame_index to
3727 * update urb->start_frame if URB_ISO_ASAP is set in transfer_flags or
3728 * Contiguous Frame ID is not supported by HC.
3729 */
3730int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3731                struct urb *urb, int slot_id, unsigned int ep_index)
3732{
3733        struct xhci_virt_device *xdev;
3734        struct xhci_ring *ep_ring;
3735        struct xhci_ep_ctx *ep_ctx;
3736        int start_frame;
3737        int num_tds, num_trbs, i;
3738        int ret;
3739        struct xhci_virt_ep *xep;
3740        int ist;
3741
3742        xdev = xhci->devs[slot_id];
3743        xep = &xhci->devs[slot_id]->eps[ep_index];
3744        ep_ring = xdev->eps[ep_index].ring;
3745        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3746
3747        num_trbs = 0;
3748        num_tds = urb->number_of_packets;
3749        for (i = 0; i < num_tds; i++)
3750                num_trbs += count_isoc_trbs_needed(urb, i);
3751
3752        /* Check the ring to guarantee there is enough room for the whole urb.
3753         * Do not insert any td of the urb to the ring if the check failed.
3754         */
3755        ret = prepare_ring(xhci, ep_ring, GET_EP_CTX_STATE(ep_ctx),
3756                           num_trbs, mem_flags);
3757        if (ret)
3758                return ret;
3759
3760        /*
3761         * Check interval value. This should be done before we start to
3762         * calculate the start frame value.
3763         */
3764        check_interval(xhci, urb, ep_ctx);
3765
3766        /* Calculate the start frame and put it in urb->start_frame. */
3767        if (HCC_CFC(xhci->hcc_params) && !list_empty(&ep_ring->td_list)) {
3768                if (GET_EP_CTX_STATE(ep_ctx) == EP_STATE_RUNNING) {
3769                        urb->start_frame = xep->next_frame_id;
3770                        goto skip_start_over;
3771                }
3772        }
3773
3774        start_frame = readl(&xhci->run_regs->microframe_index);
3775        start_frame &= 0x3fff;
3776        /*
3777         * Round up to the next frame and consider the time before trb really
3778         * gets scheduled by hardare.
3779         */
3780        ist = HCS_IST(xhci->hcs_params2) & 0x7;
3781        if (HCS_IST(xhci->hcs_params2) & (1 << 3))
3782                ist <<= 3;
3783        start_frame += ist + XHCI_CFC_DELAY;
3784        start_frame = roundup(start_frame, 8);
3785
3786        /*
3787         * Round up to the next ESIT (Endpoint Service Interval Time) if ESIT
3788         * is greate than 8 microframes.
3789         */
3790        if (urb->dev->speed == USB_SPEED_LOW ||
3791                        urb->dev->speed == USB_SPEED_FULL) {
3792                start_frame = roundup(start_frame, urb->interval << 3);
3793                urb->start_frame = start_frame >> 3;
3794        } else {
3795                start_frame = roundup(start_frame, urb->interval);
3796                urb->start_frame = start_frame;
3797        }
3798
3799skip_start_over:
3800        ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3801
3802        return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3803}
3804
3805/****           Command Ring Operations         ****/
3806
3807/* Generic function for queueing a command TRB on the command ring.
3808 * Check to make sure there's room on the command ring for one command TRB.
3809 * Also check that there's room reserved for commands that must not fail.
3810 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3811 * then only check for the number of reserved spots.
3812 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3813 * because the command event handler may want to resubmit a failed command.
3814 */
3815static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3816                         u32 field1, u32 field2,
3817                         u32 field3, u32 field4, bool command_must_succeed)
3818{
3819        int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3820        int ret;
3821
3822        if ((xhci->xhc_state & XHCI_STATE_DYING) ||
3823                (xhci->xhc_state & XHCI_STATE_HALTED)) {
3824                xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
3825                return -ESHUTDOWN;
3826        }
3827
3828        if (!command_must_succeed)
3829                reserved_trbs++;
3830
3831        ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3832                        reserved_trbs, GFP_ATOMIC);
3833        if (ret < 0) {
3834                xhci_err(xhci, "ERR: No room for command on command ring\n");
3835                if (command_must_succeed)
3836                        xhci_err(xhci, "ERR: Reserved TRB counting for "
3837                                        "unfailable commands failed.\n");
3838                return ret;
3839        }
3840
3841        cmd->command_trb = xhci->cmd_ring->enqueue;
3842
3843        /* if there are no other commands queued we start the timeout timer */
3844        if (list_empty(&xhci->cmd_list)) {
3845                xhci->current_cmd = cmd;
3846                xhci_mod_cmd_timer(xhci, XHCI_CMD_DEFAULT_TIMEOUT);
3847        }
3848
3849        list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
3850
3851        queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3852                        field4 | xhci->cmd_ring->cycle_state);
3853        return 0;
3854}
3855
3856/* Queue a slot enable or disable request on the command ring */
3857int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3858                u32 trb_type, u32 slot_id)
3859{
3860        return queue_command(xhci, cmd, 0, 0, 0,
3861                        TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3862}
3863
3864/* Queue an address device command TRB */
3865int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3866                dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
3867{
3868        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3869                        upper_32_bits(in_ctx_ptr), 0,
3870                        TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3871                        | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
3872}
3873
3874int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3875                u32 field1, u32 field2, u32 field3, u32 field4)
3876{
3877        return queue_command(xhci, cmd, field1, field2, field3, field4, false);
3878}
3879
3880/* Queue a reset device command TRB */
3881int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3882                u32 slot_id)
3883{
3884        return queue_command(xhci, cmd, 0, 0, 0,
3885                        TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3886                        false);
3887}
3888
3889/* Queue a configure endpoint command TRB */
3890int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3891                struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
3892                u32 slot_id, bool command_must_succeed)
3893{
3894        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3895                        upper_32_bits(in_ctx_ptr), 0,
3896                        TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3897                        command_must_succeed);
3898}
3899
3900/* Queue an evaluate context command TRB */
3901int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3902                dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
3903{
3904        return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
3905                        upper_32_bits(in_ctx_ptr), 0,
3906                        TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3907                        command_must_succeed);
3908}
3909
3910/*
3911 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3912 * activity on an endpoint that is about to be suspended.
3913 */
3914int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3915                             int slot_id, unsigned int ep_index, int suspend)
3916{
3917        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3918        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3919        u32 type = TRB_TYPE(TRB_STOP_RING);
3920        u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3921
3922        return queue_command(xhci, cmd, 0, 0, 0,
3923                        trb_slot_id | trb_ep_index | type | trb_suspend, false);
3924}
3925
3926/* Set Transfer Ring Dequeue Pointer command */
3927void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3928                unsigned int slot_id, unsigned int ep_index,
3929                struct xhci_dequeue_state *deq_state)
3930{
3931        dma_addr_t addr;
3932        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3933        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3934        u32 trb_stream_id = STREAM_ID_FOR_TRB(deq_state->stream_id);
3935        u32 trb_sct = 0;
3936        u32 type = TRB_TYPE(TRB_SET_DEQ);
3937        struct xhci_virt_ep *ep;
3938        struct xhci_command *cmd;
3939        int ret;
3940
3941        xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
3942                "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3943                deq_state->new_deq_seg,
3944                (unsigned long long)deq_state->new_deq_seg->dma,
3945                deq_state->new_deq_ptr,
3946                (unsigned long long)xhci_trb_virt_to_dma(
3947                        deq_state->new_deq_seg, deq_state->new_deq_ptr),
3948                deq_state->new_cycle_state);
3949
3950        addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3951                                    deq_state->new_deq_ptr);
3952        if (addr == 0) {
3953                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3954                xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3955                          deq_state->new_deq_seg, deq_state->new_deq_ptr);
3956                return;
3957        }
3958        ep = &xhci->devs[slot_id]->eps[ep_index];
3959        if ((ep->ep_state & SET_DEQ_PENDING)) {
3960                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3961                xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3962                return;
3963        }
3964
3965        /* This function gets called from contexts where it cannot sleep */
3966        cmd = xhci_alloc_command(xhci, false, GFP_ATOMIC);
3967        if (!cmd)
3968                return;
3969
3970        ep->queued_deq_seg = deq_state->new_deq_seg;
3971        ep->queued_deq_ptr = deq_state->new_deq_ptr;
3972        if (deq_state->stream_id)
3973                trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
3974        ret = queue_command(xhci, cmd,
3975                lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
3976                upper_32_bits(addr), trb_stream_id,
3977                trb_slot_id | trb_ep_index | type, false);
3978        if (ret < 0) {
3979                xhci_free_command(xhci, cmd);
3980                return;
3981        }
3982
3983        /* Stop the TD queueing code from ringing the doorbell until
3984         * this command completes.  The HC won't set the dequeue pointer
3985         * if the ring is running, and ringing the doorbell starts the
3986         * ring running.
3987         */
3988        ep->ep_state |= SET_DEQ_PENDING;
3989}
3990
3991int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3992                        int slot_id, unsigned int ep_index,
3993                        enum xhci_ep_reset_type reset_type)
3994{
3995        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3996        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3997        u32 type = TRB_TYPE(TRB_RESET_EP);
3998
3999        if (reset_type == EP_SOFT_RESET)
4000                type |= TRB_TSP;
4001
4002        return queue_command(xhci, cmd, 0, 0, 0,
4003                        trb_slot_id | trb_ep_index | type, false);
4004}
4005