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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39
40
41
42
43
44
45
46
47
48
49
50
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55
56struct pci_slot {
57 struct pci_bus *bus;
58 struct list_head list;
59 struct hotplug_slot *hotplug;
60 unsigned char number;
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75
76enum {
77
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81
82 PCI_ROM_RESOURCE,
83
84
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97
98 PCI_NUM_RESOURCES,
99
100
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104
105
106
107
108
109
110
111
112
113
114
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123
124#define PCI_NUM_INTX 4
125
126
127
128
129
130typedef int __bitwise pci_power_t;
131
132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
137#define PCI_UNKNOWN ((pci_power_t __force) 5)
138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
145 return pci_power_names[1 + (__force int) state];
146}
147
148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
152
153
154
155
156
157
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
177
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
180
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
186
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208};
209
210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
221};
222
223
224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
230 PCIE_LNK_X12 = 0x0c,
231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
234};
235
236
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
264struct pci_cap_saved_data {
265 u16 cap_nr;
266 bool cap_extended;
267 unsigned int size;
268 u32 data[0];
269};
270
271struct pci_cap_saved_state {
272 struct hlist_node next;
273 struct pci_cap_saved_data cap;
274};
275
276struct irq_affinity;
277struct pcie_link_state;
278struct pci_vpd;
279struct pci_sriov;
280struct pci_ats;
281
282
283struct pci_dev {
284 struct list_head bus_list;
285 struct pci_bus *bus;
286 struct pci_bus *subordinate;
287
288 void *sysdata;
289 struct proc_dir_entry *procent;
290 struct pci_slot *slot;
291
292 unsigned int devfn;
293 unsigned short vendor;
294 unsigned short device;
295 unsigned short subsystem_vendor;
296 unsigned short subsystem_device;
297 unsigned int class;
298 u8 revision;
299 u8 hdr_type;
300#ifdef CONFIG_PCIEAER
301 u16 aer_cap;
302#endif
303 u8 pcie_cap;
304 u8 msi_cap;
305 u8 msix_cap;
306 u8 pcie_mpss:3;
307 u8 rom_base_reg;
308 u8 pin;
309 u16 pcie_flags_reg;
310 unsigned long *dma_alias_mask;
311
312 struct pci_driver *driver;
313 u64 dma_mask;
314
315
316
317
318
319 struct device_dma_parameters dma_parms;
320
321 pci_power_t current_state;
322
323
324 u8 pm_cap;
325 unsigned int pme_support:5;
326
327 unsigned int pme_poll:1;
328 unsigned int d1_support:1;
329 unsigned int d2_support:1;
330 unsigned int no_d1d2:1;
331 unsigned int no_d3cold:1;
332 unsigned int bridge_d3:1;
333 unsigned int d3cold_allowed:1;
334 unsigned int mmio_always_on:1;
335
336 unsigned int wakeup_prepared:1;
337 unsigned int runtime_d3cold:1;
338
339
340
341 unsigned int ignore_hotplug:1;
342 unsigned int hotplug_user_indicators:1;
343
344
345 unsigned int d3_delay;
346 unsigned int d3cold_delay;
347
348#ifdef CONFIG_PCIEASPM
349 struct pcie_link_state *link_state;
350 unsigned int ltr_path:1;
351
352#endif
353
354 pci_channel_state_t error_state;
355 struct device dev;
356
357 int cfg_size;
358
359
360
361
362
363 unsigned int irq;
364 struct resource resource[DEVICE_COUNT_RESOURCE];
365
366 bool match_driver;
367
368 unsigned int transparent:1;
369 unsigned int multifunction:1;
370
371 unsigned int is_busmaster:1;
372 unsigned int no_msi:1;
373 unsigned int no_64bit_msi:1;
374 unsigned int block_cfg_access:1;
375 unsigned int broken_parity_status:1;
376 unsigned int irq_reroute_variant:2;
377 unsigned int msi_enabled:1;
378 unsigned int msix_enabled:1;
379 unsigned int ari_enabled:1;
380 unsigned int ats_enabled:1;
381 unsigned int pasid_enabled:1;
382 unsigned int pri_enabled:1;
383 unsigned int is_managed:1;
384 unsigned int needs_freset:1;
385 unsigned int state_saved:1;
386 unsigned int is_physfn:1;
387 unsigned int is_virtfn:1;
388 unsigned int reset_fn:1;
389 unsigned int is_hotplug_bridge:1;
390 unsigned int is_thunderbolt:1;
391 unsigned int __aer_firmware_first_valid:1;
392 unsigned int __aer_firmware_first:1;
393 unsigned int broken_intx_masking:1;
394 unsigned int io_window_1k:1;
395 unsigned int irq_managed:1;
396 unsigned int has_secondary_link:1;
397 unsigned int non_compliant_bars:1;
398 unsigned int is_probed:1;
399 pci_dev_flags_t dev_flags;
400 atomic_t enable_cnt;
401
402 u32 saved_config_space[16];
403 struct hlist_head saved_cap_space;
404 struct bin_attribute *rom_attr;
405 int rom_attr_enabled;
406 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
407 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
408
409#ifdef CONFIG_HOTPLUG_PCI_PCIE
410 unsigned int broken_cmd_compl:1;
411#endif
412#ifdef CONFIG_PCIE_PTM
413 unsigned int ptm_root:1;
414 unsigned int ptm_enabled:1;
415 u8 ptm_granularity;
416#endif
417#ifdef CONFIG_PCI_MSI
418 const struct attribute_group **msi_irq_groups;
419#endif
420 struct pci_vpd *vpd;
421#ifdef CONFIG_PCI_ATS
422 union {
423 struct pci_sriov *sriov;
424 struct pci_dev *physfn;
425 };
426 u16 ats_cap;
427 u8 ats_stu;
428 atomic_t ats_ref_cnt;
429#endif
430#ifdef CONFIG_PCI_PRI
431 u32 pri_reqs_alloc;
432#endif
433#ifdef CONFIG_PCI_PASID
434 u16 pasid_features;
435#endif
436 phys_addr_t rom;
437 size_t romlen;
438 char *driver_override;
439
440 unsigned long priv_flags;
441};
442
443static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
444{
445#ifdef CONFIG_PCI_IOV
446 if (dev->is_virtfn)
447 dev = dev->physfn;
448#endif
449 return dev;
450}
451
452struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
453
454#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
455#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
456
457static inline int pci_channel_offline(struct pci_dev *pdev)
458{
459 return (pdev->error_state != pci_channel_io_normal);
460}
461
462struct pci_host_bridge {
463 struct device dev;
464 struct pci_bus *bus;
465 struct pci_ops *ops;
466 void *sysdata;
467 int busnr;
468 struct list_head windows;
469 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
470 int (*map_irq)(const struct pci_dev *, u8, u8);
471 void (*release_fn)(struct pci_host_bridge *);
472 void *release_data;
473 struct msi_controller *msi;
474 unsigned int ignore_reset_delay:1;
475 unsigned int no_ext_tags:1;
476 unsigned int native_aer:1;
477 unsigned int native_pcie_hotplug:1;
478 unsigned int native_shpc_hotplug:1;
479 unsigned int native_pme:1;
480 unsigned int native_ltr:1;
481
482 resource_size_t (*align_resource)(struct pci_dev *dev,
483 const struct resource *res,
484 resource_size_t start,
485 resource_size_t size,
486 resource_size_t align);
487 unsigned long private[0] ____cacheline_aligned;
488};
489
490#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
491
492static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
493{
494 return (void *)bridge->private;
495}
496
497static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
498{
499 return container_of(priv, struct pci_host_bridge, private);
500}
501
502struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
503struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
504 size_t priv);
505void pci_free_host_bridge(struct pci_host_bridge *bridge);
506struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
507
508void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
509 void (*release_fn)(struct pci_host_bridge *),
510 void *release_data);
511
512int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
513
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526
527#define PCI_SUBTRACTIVE_DECODE 0x1
528
529struct pci_bus_resource {
530 struct list_head list;
531 struct resource *res;
532 unsigned int flags;
533};
534
535#define PCI_REGION_FLAG_MASK 0x0fU
536
537struct pci_bus {
538 struct list_head node;
539 struct pci_bus *parent;
540 struct list_head children;
541 struct list_head devices;
542 struct pci_dev *self;
543 struct list_head slots;
544
545 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
546 struct list_head resources;
547 struct resource busn_res;
548
549 struct pci_ops *ops;
550 struct msi_controller *msi;
551 void *sysdata;
552 struct proc_dir_entry *procdir;
553
554 unsigned char number;
555 unsigned char primary;
556 unsigned char max_bus_speed;
557 unsigned char cur_bus_speed;
558#ifdef CONFIG_PCI_DOMAINS_GENERIC
559 int domain_nr;
560#endif
561
562 char name[48];
563
564 unsigned short bridge_ctl;
565 pci_bus_flags_t bus_flags;
566 struct device *bridge;
567 struct device dev;
568 struct bin_attribute *legacy_io;
569 struct bin_attribute *legacy_mem;
570 unsigned int is_added:1;
571};
572
573#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
574
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582
583static inline bool pci_is_root_bus(struct pci_bus *pbus)
584{
585 return !(pbus->parent);
586}
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595static inline bool pci_is_bridge(struct pci_dev *dev)
596{
597 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
598 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
599}
600
601#define for_each_pci_bridge(dev, bus) \
602 list_for_each_entry(dev, &bus->devices, bus_list) \
603 if (!pci_is_bridge(dev)) {} else
604
605static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
606{
607 dev = pci_physfn(dev);
608 if (pci_is_root_bus(dev->bus))
609 return NULL;
610
611 return dev->bus->self;
612}
613
614struct device *pci_get_host_bridge_device(struct pci_dev *dev);
615void pci_put_host_bridge_device(struct device *dev);
616
617#ifdef CONFIG_PCI_MSI
618static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
619{
620 return pci_dev->msi_enabled || pci_dev->msix_enabled;
621}
622#else
623static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
624#endif
625
626
627#define PCIBIOS_SUCCESSFUL 0x00
628#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
629#define PCIBIOS_BAD_VENDOR_ID 0x83
630#define PCIBIOS_DEVICE_NOT_FOUND 0x86
631#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
632#define PCIBIOS_SET_FAILED 0x88
633#define PCIBIOS_BUFFER_TOO_SMALL 0x89
634
635
636static inline int pcibios_err_to_errno(int err)
637{
638 if (err <= PCIBIOS_SUCCESSFUL)
639 return err;
640
641 switch (err) {
642 case PCIBIOS_FUNC_NOT_SUPPORTED:
643 return -ENOENT;
644 case PCIBIOS_BAD_VENDOR_ID:
645 return -ENOTTY;
646 case PCIBIOS_DEVICE_NOT_FOUND:
647 return -ENODEV;
648 case PCIBIOS_BAD_REGISTER_NUMBER:
649 return -EFAULT;
650 case PCIBIOS_SET_FAILED:
651 return -EIO;
652 case PCIBIOS_BUFFER_TOO_SMALL:
653 return -ENOSPC;
654 }
655
656 return -ERANGE;
657}
658
659
660
661struct pci_ops {
662 int (*add_bus)(struct pci_bus *bus);
663 void (*remove_bus)(struct pci_bus *bus);
664 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
665 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
666 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
667};
668
669
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671
672
673int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
674 int reg, int len, u32 *val);
675int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
676 int reg, int len, u32 val);
677
678#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
679typedef u64 pci_bus_addr_t;
680#else
681typedef u32 pci_bus_addr_t;
682#endif
683
684struct pci_bus_region {
685 pci_bus_addr_t start;
686 pci_bus_addr_t end;
687};
688
689struct pci_dynids {
690 spinlock_t lock;
691 struct list_head list;
692};
693
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700
701
702typedef unsigned int __bitwise pci_ers_result_t;
703
704enum pci_ers_result {
705
706 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
707
708
709 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
710
711
712 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
713
714
715 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
716
717
718 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
719
720
721 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
722};
723
724
725struct pci_error_handlers {
726
727 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
728 enum pci_channel_state error);
729
730
731 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
732
733
734 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
735
736
737 void (*reset_prepare)(struct pci_dev *dev);
738 void (*reset_done)(struct pci_dev *dev);
739
740
741 void (*resume)(struct pci_dev *dev);
742};
743
744
745struct module;
746struct pci_driver {
747 struct list_head node;
748 const char *name;
749 const struct pci_device_id *id_table;
750 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
751 void (*remove)(struct pci_dev *dev);
752 int (*suspend)(struct pci_dev *dev, pm_message_t state);
753 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
754 int (*resume_early)(struct pci_dev *dev);
755 int (*resume) (struct pci_dev *dev);
756 void (*shutdown) (struct pci_dev *dev);
757 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
758 const struct pci_error_handlers *err_handler;
759 const struct attribute_group **groups;
760 struct device_driver driver;
761 struct pci_dynids dynids;
762};
763
764#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
765
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774
775#define PCI_DEVICE(vend,dev) \
776 .vendor = (vend), .device = (dev), \
777 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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789#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
790 .vendor = (vend), .device = (dev), \
791 .subvendor = (subvend), .subdevice = (subdev)
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801
802#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
803 .class = (dev_class), .class_mask = (dev_class_mask), \
804 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
805 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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816
817#define PCI_VDEVICE(vend, dev) \
818 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
819 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
820
821enum {
822 PCI_REASSIGN_ALL_RSRC = 0x00000001,
823 PCI_REASSIGN_ALL_BUS = 0x00000002,
824 PCI_PROBE_ONLY = 0x00000004,
825 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
826 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
827 PCI_COMPAT_DOMAIN_0 = 0x00000020,
828 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
829};
830
831
832#ifdef CONFIG_PCI
833
834extern unsigned int pci_flags;
835
836static inline void pci_set_flags(int flags) { pci_flags = flags; }
837static inline void pci_add_flags(int flags) { pci_flags |= flags; }
838static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
839static inline int pci_has_flag(int flag) { return pci_flags & flag; }
840
841void pcie_bus_configure_settings(struct pci_bus *bus);
842
843enum pcie_bus_config_types {
844 PCIE_BUS_TUNE_OFF,
845 PCIE_BUS_DEFAULT,
846 PCIE_BUS_SAFE,
847 PCIE_BUS_PERFORMANCE,
848 PCIE_BUS_PEER2PEER,
849};
850
851extern enum pcie_bus_config_types pcie_bus_config;
852
853extern struct bus_type pci_bus_type;
854
855
856
857extern struct list_head pci_root_buses;
858
859int no_pci_devices(void);
860
861void pcibios_resource_survey_bus(struct pci_bus *bus);
862void pcibios_bus_add_device(struct pci_dev *pdev);
863void pcibios_add_bus(struct pci_bus *bus);
864void pcibios_remove_bus(struct pci_bus *bus);
865void pcibios_fixup_bus(struct pci_bus *);
866int __must_check pcibios_enable_device(struct pci_dev *, int mask);
867
868char *pcibios_setup(char *str);
869
870
871resource_size_t pcibios_align_resource(void *, const struct resource *,
872 resource_size_t,
873 resource_size_t);
874
875
876void pci_fixup_cardbus(struct pci_bus *);
877
878
879
880void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
881 struct resource *res);
882void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
883 struct pci_bus_region *region);
884void pcibios_scan_specific_bus(int busn);
885struct pci_bus *pci_find_bus(int domain, int busnr);
886void pci_bus_add_devices(const struct pci_bus *bus);
887struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
888struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
889 struct pci_ops *ops, void *sysdata,
890 struct list_head *resources);
891int pci_host_probe(struct pci_host_bridge *bridge);
892int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
893int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
894void pci_bus_release_busn_res(struct pci_bus *b);
895struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
896 struct pci_ops *ops, void *sysdata,
897 struct list_head *resources);
898int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
899struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
900 int busnr);
901void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
902struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
903 const char *name,
904 struct hotplug_slot *hotplug);
905void pci_destroy_slot(struct pci_slot *slot);
906#ifdef CONFIG_SYSFS
907void pci_dev_assign_slot(struct pci_dev *dev);
908#else
909static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
910#endif
911int pci_scan_slot(struct pci_bus *bus, int devfn);
912struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
913void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
914unsigned int pci_scan_child_bus(struct pci_bus *bus);
915void pci_bus_add_device(struct pci_dev *dev);
916void pci_read_bridge_bases(struct pci_bus *child);
917struct resource *pci_find_parent_resource(const struct pci_dev *dev,
918 struct resource *res);
919struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
920u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
921int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
922u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
923struct pci_dev *pci_dev_get(struct pci_dev *dev);
924void pci_dev_put(struct pci_dev *dev);
925void pci_remove_bus(struct pci_bus *b);
926void pci_stop_and_remove_bus_device(struct pci_dev *dev);
927void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
928void pci_stop_root_bus(struct pci_bus *bus);
929void pci_remove_root_bus(struct pci_bus *bus);
930void pci_setup_cardbus(struct pci_bus *bus);
931void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
932void pci_sort_breadthfirst(void);
933#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
934#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
935
936
937
938enum pci_lost_interrupt_reason {
939 PCI_LOST_IRQ_NO_INFORMATION = 0,
940 PCI_LOST_IRQ_DISABLE_MSI,
941 PCI_LOST_IRQ_DISABLE_MSIX,
942 PCI_LOST_IRQ_DISABLE_ACPI,
943};
944enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
945int pci_find_capability(struct pci_dev *dev, int cap);
946int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
947int pci_find_ext_capability(struct pci_dev *dev, int cap);
948int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
949int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
950int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
951struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
952
953struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
954 struct pci_dev *from);
955struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
956 unsigned int ss_vendor, unsigned int ss_device,
957 struct pci_dev *from);
958struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
959struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
960 unsigned int devfn);
961struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
962int pci_dev_present(const struct pci_device_id *ids);
963
964int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
965 int where, u8 *val);
966int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
967 int where, u16 *val);
968int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
969 int where, u32 *val);
970int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
971 int where, u8 val);
972int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
973 int where, u16 val);
974int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
975 int where, u32 val);
976
977int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
978 int where, int size, u32 *val);
979int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
980 int where, int size, u32 val);
981int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
982 int where, int size, u32 *val);
983int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
984 int where, int size, u32 val);
985
986struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
987
988int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
989int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
990int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
991int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
992int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
993int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
994
995int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
996int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
997int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
998int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
999int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1000 u16 clear, u16 set);
1001int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1002 u32 clear, u32 set);
1003
1004static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1005 u16 set)
1006{
1007 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1008}
1009
1010static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1011 u32 set)
1012{
1013 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1014}
1015
1016static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1017 u16 clear)
1018{
1019 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1020}
1021
1022static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1023 u32 clear)
1024{
1025 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1026}
1027
1028
1029int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1030int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1031int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1032int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1033int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1034int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1035
1036int __must_check pci_enable_device(struct pci_dev *dev);
1037int __must_check pci_enable_device_io(struct pci_dev *dev);
1038int __must_check pci_enable_device_mem(struct pci_dev *dev);
1039int __must_check pci_reenable_device(struct pci_dev *);
1040int __must_check pcim_enable_device(struct pci_dev *pdev);
1041void pcim_pin_device(struct pci_dev *pdev);
1042
1043static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1044{
1045
1046
1047
1048
1049 return !pdev->broken_intx_masking;
1050}
1051
1052static inline int pci_is_enabled(struct pci_dev *pdev)
1053{
1054 return (atomic_read(&pdev->enable_cnt) > 0);
1055}
1056
1057static inline int pci_is_managed(struct pci_dev *pdev)
1058{
1059 return pdev->is_managed;
1060}
1061
1062void pci_disable_device(struct pci_dev *dev);
1063
1064extern unsigned int pcibios_max_latency;
1065void pci_set_master(struct pci_dev *dev);
1066void pci_clear_master(struct pci_dev *dev);
1067
1068int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1069int pci_set_cacheline_size(struct pci_dev *dev);
1070#define HAVE_PCI_SET_MWI
1071int __must_check pci_set_mwi(struct pci_dev *dev);
1072int __must_check pcim_set_mwi(struct pci_dev *dev);
1073int pci_try_set_mwi(struct pci_dev *dev);
1074void pci_clear_mwi(struct pci_dev *dev);
1075void pci_intx(struct pci_dev *dev, int enable);
1076bool pci_check_and_mask_intx(struct pci_dev *dev);
1077bool pci_check_and_unmask_intx(struct pci_dev *dev);
1078int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1079int pci_wait_for_pending_transaction(struct pci_dev *dev);
1080int pcix_get_max_mmrbc(struct pci_dev *dev);
1081int pcix_get_mmrbc(struct pci_dev *dev);
1082int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1083int pcie_get_readrq(struct pci_dev *dev);
1084int pcie_set_readrq(struct pci_dev *dev, int rq);
1085int pcie_get_mps(struct pci_dev *dev);
1086int pcie_set_mps(struct pci_dev *dev, int mps);
1087u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1088 enum pci_bus_speed *speed,
1089 enum pcie_link_width *width);
1090void pcie_print_link_status(struct pci_dev *dev);
1091int pcie_flr(struct pci_dev *dev);
1092int __pci_reset_function_locked(struct pci_dev *dev);
1093int pci_reset_function(struct pci_dev *dev);
1094int pci_reset_function_locked(struct pci_dev *dev);
1095int pci_try_reset_function(struct pci_dev *dev);
1096int pci_probe_reset_slot(struct pci_slot *slot);
1097int pci_reset_slot(struct pci_slot *slot);
1098int pci_try_reset_slot(struct pci_slot *slot);
1099int pci_probe_reset_bus(struct pci_bus *bus);
1100int pci_reset_bus(struct pci_bus *bus);
1101int pci_try_reset_bus(struct pci_bus *bus);
1102void pci_reset_secondary_bus(struct pci_dev *dev);
1103void pcibios_reset_secondary_bus(struct pci_dev *dev);
1104int pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1105void pci_update_resource(struct pci_dev *dev, int resno);
1106int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1107int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1108void pci_release_resource(struct pci_dev *dev, int resno);
1109int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1110int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1111bool pci_device_is_present(struct pci_dev *pdev);
1112void pci_ignore_hotplug(struct pci_dev *dev);
1113
1114int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1115 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1116 const char *fmt, ...);
1117void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1118
1119
1120int pci_enable_rom(struct pci_dev *pdev);
1121void pci_disable_rom(struct pci_dev *pdev);
1122void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1123void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1124size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1125void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1126
1127
1128int pci_save_state(struct pci_dev *dev);
1129void pci_restore_state(struct pci_dev *dev);
1130struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1131int pci_load_saved_state(struct pci_dev *dev,
1132 struct pci_saved_state *state);
1133int pci_load_and_free_saved_state(struct pci_dev *dev,
1134 struct pci_saved_state **state);
1135struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1136struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1137 u16 cap);
1138int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1139int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1140 u16 cap, unsigned int size);
1141int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1142int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1143pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1144bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1145void pci_pme_active(struct pci_dev *dev, bool enable);
1146int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1147int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1148int pci_prepare_to_sleep(struct pci_dev *dev);
1149int pci_back_from_sleep(struct pci_dev *dev);
1150bool pci_dev_run_wake(struct pci_dev *dev);
1151bool pci_check_pme_status(struct pci_dev *dev);
1152void pci_pme_wakeup_bus(struct pci_bus *bus);
1153void pci_d3cold_enable(struct pci_dev *dev);
1154void pci_d3cold_disable(struct pci_dev *dev);
1155bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1156void pci_wakeup_bus(struct pci_bus *bus);
1157void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1158
1159
1160int pci_save_vc_state(struct pci_dev *dev);
1161void pci_restore_vc_state(struct pci_dev *dev);
1162void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1163
1164
1165void set_pcie_port_type(struct pci_dev *pdev);
1166void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1167
1168
1169int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1170unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1171unsigned int pci_rescan_bus(struct pci_bus *bus);
1172void pci_lock_rescan_remove(void);
1173void pci_unlock_rescan_remove(void);
1174
1175
1176ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1177ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1178int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1179
1180
1181resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1182void pci_bus_assign_resources(const struct pci_bus *bus);
1183void pci_bus_claim_resources(struct pci_bus *bus);
1184void pci_bus_size_bridges(struct pci_bus *bus);
1185int pci_claim_resource(struct pci_dev *, int);
1186int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1187void pci_assign_unassigned_resources(void);
1188void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1189void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1190void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1191int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1192void pdev_enable_device(struct pci_dev *);
1193int pci_enable_resources(struct pci_dev *, int mask);
1194void pci_assign_irq(struct pci_dev *dev);
1195struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1196#define HAVE_PCI_REQ_REGIONS 2
1197int __must_check pci_request_regions(struct pci_dev *, const char *);
1198int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1199void pci_release_regions(struct pci_dev *);
1200int __must_check pci_request_region(struct pci_dev *, int, const char *);
1201int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1202void pci_release_region(struct pci_dev *, int);
1203int pci_request_selected_regions(struct pci_dev *, int, const char *);
1204int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1205void pci_release_selected_regions(struct pci_dev *, int);
1206
1207
1208struct pci_bus *pci_bus_get(struct pci_bus *bus);
1209void pci_bus_put(struct pci_bus *bus);
1210void pci_add_resource(struct list_head *resources, struct resource *res);
1211void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1212 resource_size_t offset);
1213void pci_free_resource_list(struct list_head *resources);
1214void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1215 unsigned int flags);
1216struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1217void pci_bus_remove_resources(struct pci_bus *bus);
1218int devm_request_pci_bus_resources(struct device *dev,
1219 struct list_head *resources);
1220
1221#define pci_bus_for_each_resource(bus, res, i) \
1222 for (i = 0; \
1223 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1224 i++)
1225
1226int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1227 struct resource *res, resource_size_t size,
1228 resource_size_t align, resource_size_t min,
1229 unsigned long type_mask,
1230 resource_size_t (*alignf)(void *,
1231 const struct resource *,
1232 resource_size_t,
1233 resource_size_t),
1234 void *alignf_data);
1235
1236
1237int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1238 resource_size_t size);
1239unsigned long pci_address_to_pio(phys_addr_t addr);
1240phys_addr_t pci_pio_to_address(unsigned long pio);
1241int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1242int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1243 phys_addr_t phys_addr);
1244void pci_unmap_iospace(struct resource *res);
1245void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1246 resource_size_t offset,
1247 resource_size_t size);
1248void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1249 struct resource *res);
1250
1251static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1252{
1253 struct pci_bus_region region;
1254
1255 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1256 return region.start;
1257}
1258
1259
1260int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1261 const char *mod_name);
1262
1263
1264#define pci_register_driver(driver) \
1265 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1266
1267void pci_unregister_driver(struct pci_driver *dev);
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277#define module_pci_driver(__pci_driver) \
1278 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288#define builtin_pci_driver(__pci_driver) \
1289 builtin_driver(__pci_driver, pci_register_driver)
1290
1291struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1292int pci_add_dynid(struct pci_driver *drv,
1293 unsigned int vendor, unsigned int device,
1294 unsigned int subvendor, unsigned int subdevice,
1295 unsigned int class, unsigned int class_mask,
1296 unsigned long driver_data);
1297const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1298 struct pci_dev *dev);
1299int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1300 int pass);
1301
1302void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1303 void *userdata);
1304int pci_cfg_space_size(struct pci_dev *dev);
1305unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1306void pci_setup_bridge(struct pci_bus *bus);
1307resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1308 unsigned long type);
1309
1310#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1311#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1312
1313int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1314 unsigned int command_bits, u32 flags);
1315
1316#define PCI_IRQ_LEGACY (1 << 0)
1317#define PCI_IRQ_MSI (1 << 1)
1318#define PCI_IRQ_MSIX (1 << 2)
1319#define PCI_IRQ_AFFINITY (1 << 3)
1320#define PCI_IRQ_ALL_TYPES \
1321 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1322
1323
1324
1325#include <linux/pci-dma.h>
1326#include <linux/dmapool.h>
1327
1328#define pci_pool dma_pool
1329#define pci_pool_create(name, pdev, size, align, allocation) \
1330 dma_pool_create(name, &pdev->dev, size, align, allocation)
1331#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1332#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1333#define pci_pool_zalloc(pool, flags, handle) \
1334 dma_pool_zalloc(pool, flags, handle)
1335#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1336
1337struct msix_entry {
1338 u32 vector;
1339 u16 entry;
1340};
1341
1342#ifdef CONFIG_PCI_MSI
1343int pci_msi_vec_count(struct pci_dev *dev);
1344void pci_disable_msi(struct pci_dev *dev);
1345int pci_msix_vec_count(struct pci_dev *dev);
1346void pci_disable_msix(struct pci_dev *dev);
1347void pci_restore_msi_state(struct pci_dev *dev);
1348int pci_msi_enabled(void);
1349int pci_enable_msi(struct pci_dev *dev);
1350int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1351 int minvec, int maxvec);
1352static inline int pci_enable_msix_exact(struct pci_dev *dev,
1353 struct msix_entry *entries, int nvec)
1354{
1355 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1356 if (rc < 0)
1357 return rc;
1358 return 0;
1359}
1360int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1361 unsigned int max_vecs, unsigned int flags,
1362 const struct irq_affinity *affd);
1363
1364void pci_free_irq_vectors(struct pci_dev *dev);
1365int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1366const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1367int pci_irq_get_node(struct pci_dev *pdev, int vec);
1368
1369#else
1370static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1371static inline void pci_disable_msi(struct pci_dev *dev) { }
1372static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1373static inline void pci_disable_msix(struct pci_dev *dev) { }
1374static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1375static inline int pci_msi_enabled(void) { return 0; }
1376static inline int pci_enable_msi(struct pci_dev *dev)
1377{ return -ENOSYS; }
1378static inline int pci_enable_msix_range(struct pci_dev *dev,
1379 struct msix_entry *entries, int minvec, int maxvec)
1380{ return -ENOSYS; }
1381static inline int pci_enable_msix_exact(struct pci_dev *dev,
1382 struct msix_entry *entries, int nvec)
1383{ return -ENOSYS; }
1384
1385static inline int
1386pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1387 unsigned int max_vecs, unsigned int flags,
1388 const struct irq_affinity *aff_desc)
1389{
1390 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1391 return 1;
1392 return -ENOSPC;
1393}
1394
1395static inline void pci_free_irq_vectors(struct pci_dev *dev)
1396{
1397}
1398
1399static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1400{
1401 if (WARN_ON_ONCE(nr > 0))
1402 return -EINVAL;
1403 return dev->irq;
1404}
1405static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1406 int vec)
1407{
1408 return cpu_possible_mask;
1409}
1410
1411static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1412{
1413 return first_online_node;
1414}
1415#endif
1416
1417static inline int
1418pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1419 unsigned int max_vecs, unsigned int flags)
1420{
1421 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1422 NULL);
1423}
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1442 struct device_node *node,
1443 const u32 *intspec,
1444 unsigned int intsize,
1445 unsigned long *out_hwirq,
1446 unsigned int *out_type)
1447{
1448 const u32 intx = intspec[0];
1449
1450 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1451 return -EINVAL;
1452
1453 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1454 return 0;
1455}
1456
1457#ifdef CONFIG_PCIEPORTBUS
1458extern bool pcie_ports_disabled;
1459extern bool pcie_ports_native;
1460#else
1461#define pcie_ports_disabled true
1462#define pcie_ports_native false
1463#endif
1464
1465#ifdef CONFIG_PCIEASPM
1466bool pcie_aspm_support_enabled(void);
1467#else
1468static inline bool pcie_aspm_support_enabled(void) { return false; }
1469#endif
1470
1471#ifdef CONFIG_PCIEAER
1472void pci_no_aer(void);
1473bool pci_aer_available(void);
1474int pci_aer_init(struct pci_dev *dev);
1475#else
1476static inline void pci_no_aer(void) { }
1477static inline bool pci_aer_available(void) { return false; }
1478static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1479#endif
1480
1481#ifdef CONFIG_PCIE_ECRC
1482void pcie_set_ecrc_checking(struct pci_dev *dev);
1483void pcie_ecrc_get_policy(char *str);
1484#else
1485static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1486static inline void pcie_ecrc_get_policy(char *str) { }
1487#endif
1488
1489bool pci_ats_disabled(void);
1490
1491#ifdef CONFIG_PCI_ATS
1492
1493void pci_ats_init(struct pci_dev *dev);
1494int pci_enable_ats(struct pci_dev *dev, int ps);
1495void pci_disable_ats(struct pci_dev *dev);
1496int pci_ats_queue_depth(struct pci_dev *dev);
1497#else
1498static inline void pci_ats_init(struct pci_dev *d) { }
1499static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1500static inline void pci_disable_ats(struct pci_dev *d) { }
1501static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1502#endif
1503
1504#ifdef CONFIG_PCIE_PTM
1505int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1506#else
1507static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1508{ return -EINVAL; }
1509#endif
1510
1511void pci_cfg_access_lock(struct pci_dev *dev);
1512bool pci_cfg_access_trylock(struct pci_dev *dev);
1513void pci_cfg_access_unlock(struct pci_dev *dev);
1514
1515
1516
1517
1518
1519
1520#ifdef CONFIG_PCI_DOMAINS
1521extern int pci_domains_supported;
1522#else
1523enum { pci_domains_supported = 0 };
1524static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1525static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1526#endif
1527
1528
1529
1530
1531
1532
1533#ifdef CONFIG_PCI_DOMAINS_GENERIC
1534static inline int pci_domain_nr(struct pci_bus *bus)
1535{
1536 return bus->domain_nr;
1537}
1538#ifdef CONFIG_ACPI
1539int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1540#else
1541static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1542{ return 0; }
1543#endif
1544int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1545#endif
1546
1547
1548typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1549 unsigned int command_bits, u32 flags);
1550void pci_register_set_vga_state(arch_set_vga_state_t func);
1551
1552static inline int
1553pci_request_io_regions(struct pci_dev *pdev, const char *name)
1554{
1555 return pci_request_selected_regions(pdev,
1556 pci_select_bars(pdev, IORESOURCE_IO), name);
1557}
1558
1559static inline void
1560pci_release_io_regions(struct pci_dev *pdev)
1561{
1562 return pci_release_selected_regions(pdev,
1563 pci_select_bars(pdev, IORESOURCE_IO));
1564}
1565
1566static inline int
1567pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1568{
1569 return pci_request_selected_regions(pdev,
1570 pci_select_bars(pdev, IORESOURCE_MEM), name);
1571}
1572
1573static inline void
1574pci_release_mem_regions(struct pci_dev *pdev)
1575{
1576 return pci_release_selected_regions(pdev,
1577 pci_select_bars(pdev, IORESOURCE_MEM));
1578}
1579
1580#else
1581
1582static inline void pci_set_flags(int flags) { }
1583static inline void pci_add_flags(int flags) { }
1584static inline void pci_clear_flags(int flags) { }
1585static inline int pci_has_flag(int flag) { return 0; }
1586
1587
1588
1589
1590
1591#define _PCI_NOP(o, s, t) \
1592 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1593 int where, t val) \
1594 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1595
1596#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1597 _PCI_NOP(o, word, u16 x) \
1598 _PCI_NOP(o, dword, u32 x)
1599_PCI_NOP_ALL(read, *)
1600_PCI_NOP_ALL(write,)
1601
1602static inline struct pci_dev *pci_get_device(unsigned int vendor,
1603 unsigned int device,
1604 struct pci_dev *from)
1605{ return NULL; }
1606
1607static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1608 unsigned int device,
1609 unsigned int ss_vendor,
1610 unsigned int ss_device,
1611 struct pci_dev *from)
1612{ return NULL; }
1613
1614static inline struct pci_dev *pci_get_class(unsigned int class,
1615 struct pci_dev *from)
1616{ return NULL; }
1617
1618#define pci_dev_present(ids) (0)
1619#define no_pci_devices() (1)
1620#define pci_dev_put(dev) do { } while (0)
1621
1622static inline void pci_set_master(struct pci_dev *dev) { }
1623static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1624static inline void pci_disable_device(struct pci_dev *dev) { }
1625static inline int pci_assign_resource(struct pci_dev *dev, int i)
1626{ return -EBUSY; }
1627static inline int __pci_register_driver(struct pci_driver *drv,
1628 struct module *owner)
1629{ return 0; }
1630static inline int pci_register_driver(struct pci_driver *drv)
1631{ return 0; }
1632static inline void pci_unregister_driver(struct pci_driver *drv) { }
1633static inline int pci_find_capability(struct pci_dev *dev, int cap)
1634{ return 0; }
1635static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1636 int cap)
1637{ return 0; }
1638static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1639{ return 0; }
1640
1641
1642static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1643static inline void pci_restore_state(struct pci_dev *dev) { }
1644static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1645{ return 0; }
1646static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1647{ return 0; }
1648static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1649 pm_message_t state)
1650{ return PCI_D0; }
1651static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1652 int enable)
1653{ return 0; }
1654
1655static inline struct resource *pci_find_resource(struct pci_dev *dev,
1656 struct resource *res)
1657{ return NULL; }
1658static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1659{ return -EIO; }
1660static inline void pci_release_regions(struct pci_dev *dev) { }
1661
1662static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1663
1664static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1665static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1666{ return 0; }
1667static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1668
1669static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1670{ return NULL; }
1671static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1672 unsigned int devfn)
1673{ return NULL; }
1674static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1675 unsigned int bus, unsigned int devfn)
1676{ return NULL; }
1677
1678static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1679static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1680
1681#define dev_is_pci(d) (false)
1682#define dev_is_pf(d) (false)
1683static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1684{ return false; }
1685static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1686 struct device_node *node,
1687 const u32 *intspec,
1688 unsigned int intsize,
1689 unsigned long *out_hwirq,
1690 unsigned int *out_type)
1691{ return -EINVAL; }
1692#endif
1693
1694
1695
1696#include <asm/pci.h>
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1711 struct vm_area_struct *vma,
1712 enum pci_mmap_state mmap_state, int write_combine);
1713int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1714 struct vm_area_struct *vma,
1715 enum pci_mmap_state mmap_state, int write_combine);
1716
1717#ifndef arch_can_pci_mmap_wc
1718#define arch_can_pci_mmap_wc() 0
1719#endif
1720
1721#ifndef arch_can_pci_mmap_io
1722#define arch_can_pci_mmap_io() 0
1723#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1724#else
1725int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1726#endif
1727
1728#ifndef pci_root_bus_fwnode
1729#define pci_root_bus_fwnode(bus) NULL
1730#endif
1731
1732
1733
1734
1735
1736#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1737#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1738#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1739#define pci_resource_len(dev,bar) \
1740 ((pci_resource_start((dev), (bar)) == 0 && \
1741 pci_resource_end((dev), (bar)) == \
1742 pci_resource_start((dev), (bar))) ? 0 : \
1743 \
1744 (pci_resource_end((dev), (bar)) - \
1745 pci_resource_start((dev), (bar)) + 1))
1746
1747
1748
1749
1750
1751
1752static inline void *pci_get_drvdata(struct pci_dev *pdev)
1753{
1754 return dev_get_drvdata(&pdev->dev);
1755}
1756
1757static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1758{
1759 dev_set_drvdata(&pdev->dev, data);
1760}
1761
1762static inline const char *pci_name(const struct pci_dev *pdev)
1763{
1764 return dev_name(&pdev->dev);
1765}
1766
1767
1768
1769
1770
1771
1772#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1773void pci_resource_to_user(const struct pci_dev *dev, int bar,
1774 const struct resource *rsrc,
1775 resource_size_t *start, resource_size_t *end);
1776#else
1777static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1778 const struct resource *rsrc, resource_size_t *start,
1779 resource_size_t *end)
1780{
1781 *start = rsrc->start;
1782 *end = rsrc->end;
1783}
1784#endif
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794struct pci_fixup {
1795 u16 vendor;
1796 u16 device;
1797 u32 class;
1798 unsigned int class_shift;
1799 void (*hook)(struct pci_dev *dev);
1800};
1801
1802enum pci_fixup_pass {
1803 pci_fixup_early,
1804 pci_fixup_header,
1805 pci_fixup_final,
1806 pci_fixup_enable,
1807 pci_fixup_resume,
1808 pci_fixup_suspend,
1809 pci_fixup_resume_early,
1810 pci_fixup_suspend_late,
1811};
1812
1813
1814#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1815 class_shift, hook) \
1816 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1817 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1818 = { vendor, device, class, class_shift, hook };
1819
1820#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1821 class_shift, hook) \
1822 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1823 hook, vendor, device, class, class_shift, hook)
1824#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1825 class_shift, hook) \
1826 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1827 hook, vendor, device, class, class_shift, hook)
1828#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1829 class_shift, hook) \
1830 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1831 hook, vendor, device, class, class_shift, hook)
1832#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1833 class_shift, hook) \
1834 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1835 hook, vendor, device, class, class_shift, hook)
1836#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1837 class_shift, hook) \
1838 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1839 resume##hook, vendor, device, class, class_shift, hook)
1840#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1841 class_shift, hook) \
1842 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1843 resume_early##hook, vendor, device, class, class_shift, hook)
1844#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1845 class_shift, hook) \
1846 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1847 suspend##hook, vendor, device, class, class_shift, hook)
1848#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1849 class_shift, hook) \
1850 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1851 suspend_late##hook, vendor, device, class, class_shift, hook)
1852
1853#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1854 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1855 hook, vendor, device, PCI_ANY_ID, 0, hook)
1856#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1857 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1858 hook, vendor, device, PCI_ANY_ID, 0, hook)
1859#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1860 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1861 hook, vendor, device, PCI_ANY_ID, 0, hook)
1862#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1863 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1864 hook, vendor, device, PCI_ANY_ID, 0, hook)
1865#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1867 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1868#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1869 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1870 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1871#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1872 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1873 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1874#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1875 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1876 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1877
1878#ifdef CONFIG_PCI_QUIRKS
1879void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1880int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1881int pci_dev_specific_enable_acs(struct pci_dev *dev);
1882#else
1883static inline void pci_fixup_device(enum pci_fixup_pass pass,
1884 struct pci_dev *dev) { }
1885static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1886 u16 acs_flags)
1887{
1888 return -ENOTTY;
1889}
1890static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1891{
1892 return -ENOTTY;
1893}
1894#endif
1895
1896void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1897void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1898void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1899int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1900int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1901 const char *name);
1902void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1903
1904extern int pci_pci_problems;
1905#define PCIPCI_FAIL 1
1906#define PCIPCI_TRITON 2
1907#define PCIPCI_NATOMA 4
1908#define PCIPCI_VIAETBF 8
1909#define PCIPCI_VSFX 16
1910#define PCIPCI_ALIMAGIK 32
1911#define PCIAGP_FAIL 64
1912
1913extern unsigned long pci_cardbus_io_size;
1914extern unsigned long pci_cardbus_mem_size;
1915extern u8 pci_dfl_cache_line_size;
1916extern u8 pci_cache_line_size;
1917
1918extern unsigned long pci_hotplug_io_size;
1919extern unsigned long pci_hotplug_mem_size;
1920extern unsigned long pci_hotplug_bus_size;
1921
1922
1923void pcibios_disable_device(struct pci_dev *dev);
1924void pcibios_set_master(struct pci_dev *dev);
1925int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1926 enum pcie_reset_state state);
1927int pcibios_add_device(struct pci_dev *dev);
1928void pcibios_release_device(struct pci_dev *dev);
1929void pcibios_penalize_isa_irq(int irq, int active);
1930int pcibios_alloc_irq(struct pci_dev *dev);
1931void pcibios_free_irq(struct pci_dev *dev);
1932resource_size_t pcibios_default_alignment(void);
1933
1934#ifdef CONFIG_HIBERNATE_CALLBACKS
1935extern struct dev_pm_ops pcibios_pm_ops;
1936#endif
1937
1938#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1939void __init pci_mmcfg_early_init(void);
1940void __init pci_mmcfg_late_init(void);
1941#else
1942static inline void pci_mmcfg_early_init(void) { }
1943static inline void pci_mmcfg_late_init(void) { }
1944#endif
1945
1946int pci_ext_cfg_avail(void);
1947
1948void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1949void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1950
1951#ifdef CONFIG_PCI_IOV
1952int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1953int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1954
1955int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1956void pci_disable_sriov(struct pci_dev *dev);
1957int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1958void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1959int pci_num_vf(struct pci_dev *dev);
1960int pci_vfs_assigned(struct pci_dev *dev);
1961int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1962int pci_sriov_get_totalvfs(struct pci_dev *dev);
1963int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1964resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1965void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1966
1967
1968int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1969int pcibios_sriov_disable(struct pci_dev *pdev);
1970resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1971#else
1972static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1973{
1974 return -ENOSYS;
1975}
1976static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1977{
1978 return -ENOSYS;
1979}
1980static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1981{ return -ENODEV; }
1982static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
1983{
1984 return -ENOSYS;
1985}
1986static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1987 int id) { }
1988static inline void pci_disable_sriov(struct pci_dev *dev) { }
1989static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1990static inline int pci_vfs_assigned(struct pci_dev *dev)
1991{ return 0; }
1992static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1993{ return 0; }
1994static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1995{ return 0; }
1996#define pci_sriov_configure_simple NULL
1997static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1998{ return 0; }
1999static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2000#endif
2001
2002#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2003void pci_hp_create_module_link(struct pci_slot *pci_slot);
2004void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2005#endif
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018static inline int pci_pcie_cap(struct pci_dev *dev)
2019{
2020 return dev->pcie_cap;
2021}
2022
2023
2024
2025
2026
2027
2028
2029static inline bool pci_is_pcie(struct pci_dev *dev)
2030{
2031 return pci_pcie_cap(dev);
2032}
2033
2034
2035
2036
2037
2038static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2039{
2040 return dev->pcie_flags_reg;
2041}
2042
2043
2044
2045
2046
2047static inline int pci_pcie_type(const struct pci_dev *dev)
2048{
2049 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2050}
2051
2052static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2053{
2054 while (1) {
2055 if (!pci_is_pcie(dev))
2056 break;
2057 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2058 return dev;
2059 if (!dev->bus->self)
2060 break;
2061 dev = dev->bus->self;
2062 }
2063 return NULL;
2064}
2065
2066void pci_request_acs(void);
2067bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2068bool pci_acs_path_enabled(struct pci_dev *start,
2069 struct pci_dev *end, u16 acs_flags);
2070int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2071
2072#define PCI_VPD_LRDT 0x80
2073#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2074
2075
2076#define PCI_VPD_LTIN_ID_STRING 0x02
2077#define PCI_VPD_LTIN_RO_DATA 0x10
2078#define PCI_VPD_LTIN_RW_DATA 0x11
2079
2080#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2081#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2082#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2083
2084
2085#define PCI_VPD_STIN_END 0x0f
2086
2087#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2088
2089#define PCI_VPD_SRDT_TIN_MASK 0x78
2090#define PCI_VPD_SRDT_LEN_MASK 0x07
2091#define PCI_VPD_LRDT_TIN_MASK 0x7f
2092
2093#define PCI_VPD_LRDT_TAG_SIZE 3
2094#define PCI_VPD_SRDT_TAG_SIZE 1
2095
2096#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2097
2098#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2099#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2100#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2101#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2102
2103
2104
2105
2106
2107
2108
2109static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2110{
2111 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2112}
2113
2114
2115
2116
2117
2118
2119
2120static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2121{
2122 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2123}
2124
2125
2126
2127
2128
2129
2130
2131static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2132{
2133 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2134}
2135
2136
2137
2138
2139
2140
2141
2142static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2143{
2144 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2145}
2146
2147
2148
2149
2150
2151
2152
2153static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2154{
2155 return info_field[2];
2156}
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2181 unsigned int len, const char *kw);
2182
2183
2184#ifdef CONFIG_OF
2185struct device_node;
2186struct irq_domain;
2187void pci_set_of_node(struct pci_dev *dev);
2188void pci_release_of_node(struct pci_dev *dev);
2189void pci_set_bus_of_node(struct pci_bus *bus);
2190void pci_release_bus_of_node(struct pci_bus *bus);
2191struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2192int pci_parse_request_of_pci_ranges(struct device *dev,
2193 struct list_head *resources,
2194 struct resource **bus_range);
2195
2196
2197struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2198
2199#else
2200static inline void pci_set_of_node(struct pci_dev *dev) { }
2201static inline void pci_release_of_node(struct pci_dev *dev) { }
2202static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2203static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2204static inline struct irq_domain *
2205pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2206static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2207 struct list_head *resources,
2208 struct resource **bus_range)
2209{
2210 return -EINVAL;
2211}
2212#endif
2213
2214static inline struct device_node *
2215pci_device_to_OF_node(const struct pci_dev *pdev)
2216{
2217 return pdev ? pdev->dev.of_node : NULL;
2218}
2219
2220static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2221{
2222 return bus ? bus->dev.of_node : NULL;
2223}
2224
2225#ifdef CONFIG_ACPI
2226struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2227
2228void
2229pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2230#else
2231static inline struct irq_domain *
2232pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2233#endif
2234
2235#ifdef CONFIG_EEH
2236static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2237{
2238 return pdev->dev.archdata.edev;
2239}
2240#endif
2241
2242void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2243bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2244int pci_for_each_dma_alias(struct pci_dev *pdev,
2245 int (*fn)(struct pci_dev *pdev,
2246 u16 alias, void *data), void *data);
2247
2248
2249static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2250{
2251 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2252}
2253static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2254{
2255 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2256}
2257static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2258{
2259 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2260}
2261
2262
2263
2264
2265
2266
2267
2268static inline bool pci_ari_enabled(struct pci_bus *bus)
2269{
2270 return bus->self && bus->self->ari_enabled;
2271}
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2282{
2283 struct pci_dev *parent = pdev;
2284
2285 if (pdev->is_thunderbolt)
2286 return true;
2287
2288 while ((parent = pci_upstream_bridge(parent)))
2289 if (parent->is_thunderbolt)
2290 return true;
2291
2292 return false;
2293}
2294
2295#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2296void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2297#endif
2298
2299
2300#include <linux/pci-dma-compat.h>
2301
2302#define pci_printk(level, pdev, fmt, arg...) \
2303 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2304
2305#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2306#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2307#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2308#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2309#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2310#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2311#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2312#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2313
2314#endif
2315