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18#ifndef __ETNAVIV_DRM_H__
19#define __ETNAVIV_DRM_H__
20
21#include "drm.h"
22
23#if defined(__cplusplus)
24extern "C" {
25#endif
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43
44struct drm_etnaviv_timespec {
45 __s64 tv_sec;
46 __s64 tv_nsec;
47};
48
49#define ETNAVIV_PARAM_GPU_MODEL 0x01
50#define ETNAVIV_PARAM_GPU_REVISION 0x02
51#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
52#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
53#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
54#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
55#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
56#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
57#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
58#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
59#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
60#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
61#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
62#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
63#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
64
65#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
66#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
67#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
68#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
69#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
70#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
71#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
72#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
73#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
74#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
75#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
76
77#define ETNA_MAX_PIPES 4
78
79struct drm_etnaviv_param {
80 __u32 pipe;
81 __u32 param;
82 __u64 value;
83};
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88
89#define ETNA_BO_CACHE_MASK 0x000f0000
90
91#define ETNA_BO_CACHED 0x00010000
92#define ETNA_BO_WC 0x00020000
93#define ETNA_BO_UNCACHED 0x00040000
94
95#define ETNA_BO_FORCE_MMU 0x00100000
96
97struct drm_etnaviv_gem_new {
98 __u64 size;
99 __u32 flags;
100 __u32 handle;
101};
102
103struct drm_etnaviv_gem_info {
104 __u32 handle;
105 __u32 pad;
106 __u64 offset;
107};
108
109#define ETNA_PREP_READ 0x01
110#define ETNA_PREP_WRITE 0x02
111#define ETNA_PREP_NOSYNC 0x04
112
113struct drm_etnaviv_gem_cpu_prep {
114 __u32 handle;
115 __u32 op;
116 struct drm_etnaviv_timespec timeout;
117};
118
119struct drm_etnaviv_gem_cpu_fini {
120 __u32 handle;
121 __u32 flags;
122};
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134struct drm_etnaviv_gem_submit_reloc {
135 __u32 submit_offset;
136 __u32 reloc_idx;
137 __u64 reloc_offset;
138 __u32 flags;
139};
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151
152#define ETNA_SUBMIT_BO_READ 0x0001
153#define ETNA_SUBMIT_BO_WRITE 0x0002
154struct drm_etnaviv_gem_submit_bo {
155 __u32 flags;
156 __u32 handle;
157 __u64 presumed;
158};
159
160
161#define ETNA_PM_PROCESS_PRE 0x0001
162#define ETNA_PM_PROCESS_POST 0x0002
163struct drm_etnaviv_gem_submit_pmr {
164 __u32 flags;
165 __u8 domain;
166 __u8 pad;
167 __u16 signal;
168 __u32 sequence;
169 __u32 read_offset;
170 __u32 read_idx;
171};
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176
177#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
178#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
179#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
180#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
181 ETNA_SUBMIT_FENCE_FD_IN | \
182 ETNA_SUBMIT_FENCE_FD_OUT)
183#define ETNA_PIPE_3D 0x00
184#define ETNA_PIPE_2D 0x01
185#define ETNA_PIPE_VG 0x02
186struct drm_etnaviv_gem_submit {
187 __u32 fence;
188 __u32 pipe;
189 __u32 exec_state;
190 __u32 nr_bos;
191 __u32 nr_relocs;
192 __u32 stream_size;
193 __u64 bos;
194 __u64 relocs;
195 __u64 stream;
196 __u32 flags;
197 __s32 fence_fd;
198 __u64 pmrs;
199 __u32 nr_pmrs;
200 __u32 pad;
201};
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210#define ETNA_WAIT_NONBLOCK 0x01
211struct drm_etnaviv_wait_fence {
212 __u32 pipe;
213 __u32 fence;
214 __u32 flags;
215 __u32 pad;
216 struct drm_etnaviv_timespec timeout;
217};
218
219#define ETNA_USERPTR_READ 0x01
220#define ETNA_USERPTR_WRITE 0x02
221struct drm_etnaviv_gem_userptr {
222 __u64 user_ptr;
223 __u64 user_size;
224 __u32 flags;
225 __u32 handle;
226};
227
228struct drm_etnaviv_gem_wait {
229 __u32 pipe;
230 __u32 handle;
231 __u32 flags;
232 __u32 pad;
233 struct drm_etnaviv_timespec timeout;
234};
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239
240struct drm_etnaviv_pm_domain {
241 __u32 pipe;
242 __u8 iter;
243 __u8 id;
244 __u16 nr_signals;
245 char name[64];
246};
247
248struct drm_etnaviv_pm_signal {
249 __u32 pipe;
250 __u8 domain;
251 __u8 pad;
252 __u16 iter;
253 __u16 id;
254 char name[64];
255};
256
257#define DRM_ETNAVIV_GET_PARAM 0x00
258
259
260
261#define DRM_ETNAVIV_GEM_NEW 0x02
262#define DRM_ETNAVIV_GEM_INFO 0x03
263#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
264#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
265#define DRM_ETNAVIV_GEM_SUBMIT 0x06
266#define DRM_ETNAVIV_WAIT_FENCE 0x07
267#define DRM_ETNAVIV_GEM_USERPTR 0x08
268#define DRM_ETNAVIV_GEM_WAIT 0x09
269#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
270#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
271#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
272
273#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
274#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
275#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
276#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
277#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
278#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
279#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
280#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
281#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
282#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
283#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
284
285#if defined(__cplusplus)
286}
287#endif
288
289#endif
290