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12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5668.h>
34
35#include "rl6231.h"
36#include "rt5668.h"
37
38#define RT5668_NUM_SUPPLIES 3
39
40static const char *rt5668_supply_names[RT5668_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5668_priv {
47 struct snd_soc_component *component;
48 struct rt5668_platform_data pdata;
49 struct regmap *regmap;
50 struct snd_soc_jack *hs_jack;
51 struct regulator_bulk_data supplies[RT5668_NUM_SUPPLIES];
52 struct delayed_work jack_detect_work;
53 struct delayed_work jd_check_work;
54 struct mutex calibrate_mutex;
55
56 int sysclk;
57 int sysclk_src;
58 int lrck[RT5668_AIFS];
59 int bclk[RT5668_AIFS];
60 int master[RT5668_AIFS];
61
62 int pll_src;
63 int pll_in;
64 int pll_out;
65
66 int jack_type;
67};
68
69static const struct reg_default rt5668_reg[] = {
70 {0x0002, 0x8080},
71 {0x0003, 0x8000},
72 {0x0005, 0x0000},
73 {0x0006, 0x0000},
74 {0x0008, 0x800f},
75 {0x000b, 0x0000},
76 {0x0010, 0x4040},
77 {0x0011, 0x0000},
78 {0x0012, 0x1404},
79 {0x0013, 0x1000},
80 {0x0014, 0xa00a},
81 {0x0015, 0x0404},
82 {0x0016, 0x0404},
83 {0x0019, 0xafaf},
84 {0x001c, 0x2f2f},
85 {0x001f, 0x0000},
86 {0x0022, 0x5757},
87 {0x0023, 0x0039},
88 {0x0024, 0x000b},
89 {0x0026, 0xc0c4},
90 {0x0029, 0x8080},
91 {0x002a, 0xa0a0},
92 {0x002b, 0x0300},
93 {0x0030, 0x0000},
94 {0x003c, 0x0080},
95 {0x0044, 0x0c0c},
96 {0x0049, 0x0000},
97 {0x0061, 0x0000},
98 {0x0062, 0x0000},
99 {0x0063, 0x003f},
100 {0x0064, 0x0000},
101 {0x0065, 0x0000},
102 {0x0066, 0x0030},
103 {0x0067, 0x0000},
104 {0x006b, 0x0000},
105 {0x006c, 0x0000},
106 {0x006d, 0x2200},
107 {0x006e, 0x0a10},
108 {0x0070, 0x8000},
109 {0x0071, 0x8000},
110 {0x0073, 0x0000},
111 {0x0074, 0x0000},
112 {0x0075, 0x0002},
113 {0x0076, 0x0001},
114 {0x0079, 0x0000},
115 {0x007a, 0x0000},
116 {0x007b, 0x0000},
117 {0x007c, 0x0100},
118 {0x007e, 0x0000},
119 {0x0080, 0x0000},
120 {0x0081, 0x0000},
121 {0x0082, 0x0000},
122 {0x0083, 0x0000},
123 {0x0084, 0x0000},
124 {0x0085, 0x0000},
125 {0x0086, 0x0005},
126 {0x0087, 0x0000},
127 {0x0088, 0x0000},
128 {0x008c, 0x0003},
129 {0x008d, 0x0000},
130 {0x008e, 0x0060},
131 {0x008f, 0x1000},
132 {0x0091, 0x0c26},
133 {0x0092, 0x0073},
134 {0x0093, 0x0000},
135 {0x0094, 0x0080},
136 {0x0098, 0x0000},
137 {0x009a, 0x0000},
138 {0x009b, 0x0000},
139 {0x009c, 0x0000},
140 {0x009d, 0x0000},
141 {0x009e, 0x100c},
142 {0x009f, 0x0000},
143 {0x00a0, 0x0000},
144 {0x00a3, 0x0002},
145 {0x00a4, 0x0001},
146 {0x00ae, 0x2040},
147 {0x00af, 0x0000},
148 {0x00b6, 0x0000},
149 {0x00b7, 0x0000},
150 {0x00b8, 0x0000},
151 {0x00b9, 0x0002},
152 {0x00be, 0x0000},
153 {0x00c0, 0x0160},
154 {0x00c1, 0x82a0},
155 {0x00c2, 0x0000},
156 {0x00d0, 0x0000},
157 {0x00d1, 0x2244},
158 {0x00d2, 0x3300},
159 {0x00d3, 0x2200},
160 {0x00d4, 0x0000},
161 {0x00d9, 0x0009},
162 {0x00da, 0x0000},
163 {0x00db, 0x0000},
164 {0x00dc, 0x00c0},
165 {0x00dd, 0x2220},
166 {0x00de, 0x3131},
167 {0x00df, 0x3131},
168 {0x00e0, 0x3131},
169 {0x00e2, 0x0000},
170 {0x00e3, 0x4000},
171 {0x00e4, 0x0aa0},
172 {0x00e5, 0x3131},
173 {0x00e6, 0x3131},
174 {0x00e7, 0x3131},
175 {0x00e8, 0x3131},
176 {0x00ea, 0xb320},
177 {0x00eb, 0x0000},
178 {0x00f0, 0x0000},
179 {0x00f1, 0x00d0},
180 {0x00f2, 0x00d0},
181 {0x00f6, 0x0000},
182 {0x00fa, 0x0000},
183 {0x00fb, 0x0000},
184 {0x00fc, 0x0000},
185 {0x00fd, 0x0000},
186 {0x00fe, 0x10ec},
187 {0x00ff, 0x6530},
188 {0x0100, 0xa0a0},
189 {0x010b, 0x0000},
190 {0x010c, 0xae00},
191 {0x010d, 0xaaa0},
192 {0x010e, 0x8aa2},
193 {0x010f, 0x02a2},
194 {0x0110, 0xc000},
195 {0x0111, 0x04a2},
196 {0x0112, 0x2800},
197 {0x0113, 0x0000},
198 {0x0117, 0x0100},
199 {0x0125, 0x0410},
200 {0x0132, 0x6026},
201 {0x0136, 0x5555},
202 {0x0138, 0x3700},
203 {0x013a, 0x2000},
204 {0x013b, 0x2000},
205 {0x013c, 0x2005},
206 {0x013f, 0x0000},
207 {0x0142, 0x0000},
208 {0x0145, 0x0002},
209 {0x0146, 0x0000},
210 {0x0147, 0x0000},
211 {0x0148, 0x0000},
212 {0x0149, 0x0000},
213 {0x0150, 0x79a1},
214 {0x0151, 0x0000},
215 {0x0160, 0x4ec0},
216 {0x0161, 0x0080},
217 {0x0162, 0x0200},
218 {0x0163, 0x0800},
219 {0x0164, 0x0000},
220 {0x0165, 0x0000},
221 {0x0166, 0x0000},
222 {0x0167, 0x000f},
223 {0x0168, 0x000f},
224 {0x0169, 0x0021},
225 {0x0190, 0x413d},
226 {0x0194, 0x0000},
227 {0x0195, 0x0000},
228 {0x0197, 0x0022},
229 {0x0198, 0x0000},
230 {0x0199, 0x0000},
231 {0x01af, 0x0000},
232 {0x01b0, 0x0400},
233 {0x01b1, 0x0000},
234 {0x01b2, 0x0000},
235 {0x01b3, 0x0000},
236 {0x01b4, 0x0000},
237 {0x01b5, 0x0000},
238 {0x01b6, 0x01c3},
239 {0x01b7, 0x02a0},
240 {0x01b8, 0x03e9},
241 {0x01b9, 0x1389},
242 {0x01ba, 0xc351},
243 {0x01bb, 0x0009},
244 {0x01bc, 0x0018},
245 {0x01bd, 0x002a},
246 {0x01be, 0x004c},
247 {0x01bf, 0x0097},
248 {0x01c0, 0x433d},
249 {0x01c1, 0x2800},
250 {0x01c2, 0x0000},
251 {0x01c3, 0x0000},
252 {0x01c4, 0x0000},
253 {0x01c5, 0x0000},
254 {0x01c6, 0x0000},
255 {0x01c7, 0x0000},
256 {0x01c8, 0x40af},
257 {0x01c9, 0x0702},
258 {0x01ca, 0x0000},
259 {0x01cb, 0x0000},
260 {0x01cc, 0x5757},
261 {0x01cd, 0x5757},
262 {0x01ce, 0x5757},
263 {0x01cf, 0x5757},
264 {0x01d0, 0x5757},
265 {0x01d1, 0x5757},
266 {0x01d2, 0x5757},
267 {0x01d3, 0x5757},
268 {0x01d4, 0x5757},
269 {0x01d5, 0x5757},
270 {0x01d6, 0x0000},
271 {0x01d7, 0x0008},
272 {0x01d8, 0x0029},
273 {0x01d9, 0x3333},
274 {0x01da, 0x0000},
275 {0x01db, 0x0004},
276 {0x01dc, 0x0000},
277 {0x01de, 0x7c00},
278 {0x01df, 0x0320},
279 {0x01e0, 0x06a1},
280 {0x01e1, 0x0000},
281 {0x01e2, 0x0000},
282 {0x01e3, 0x0000},
283 {0x01e4, 0x0000},
284 {0x01e6, 0x0001},
285 {0x01e7, 0x0000},
286 {0x01e8, 0x0000},
287 {0x01ea, 0x0000},
288 {0x01eb, 0x0000},
289 {0x01ec, 0x0000},
290 {0x01ed, 0x0000},
291 {0x01ee, 0x0000},
292 {0x01ef, 0x0000},
293 {0x01f0, 0x0000},
294 {0x01f1, 0x0000},
295 {0x01f2, 0x0000},
296 {0x01f3, 0x0000},
297 {0x01f4, 0x0000},
298 {0x0210, 0x6297},
299 {0x0211, 0xa005},
300 {0x0212, 0x824c},
301 {0x0213, 0xf7ff},
302 {0x0214, 0xf24c},
303 {0x0215, 0x0102},
304 {0x0216, 0x00a3},
305 {0x0217, 0x0048},
306 {0x0218, 0xa2c0},
307 {0x0219, 0x0400},
308 {0x021a, 0x00c8},
309 {0x021b, 0x00c0},
310 {0x021c, 0x0000},
311 {0x0250, 0x4500},
312 {0x0251, 0x40b3},
313 {0x0252, 0x0000},
314 {0x0253, 0x0000},
315 {0x0254, 0x0000},
316 {0x0255, 0x0000},
317 {0x0256, 0x0000},
318 {0x0257, 0x0000},
319 {0x0258, 0x0000},
320 {0x0259, 0x0000},
321 {0x025a, 0x0005},
322 {0x0270, 0x0000},
323 {0x02ff, 0x0110},
324 {0x0300, 0x001f},
325 {0x0301, 0x032c},
326 {0x0302, 0x5f21},
327 {0x0303, 0x4000},
328 {0x0304, 0x4000},
329 {0x0305, 0x06d5},
330 {0x0306, 0x8000},
331 {0x0307, 0x0700},
332 {0x0310, 0x4560},
333 {0x0311, 0xa4a8},
334 {0x0312, 0x7418},
335 {0x0313, 0x0000},
336 {0x0314, 0x0006},
337 {0x0315, 0xffff},
338 {0x0316, 0xc400},
339 {0x0317, 0x0000},
340 {0x03c0, 0x7e00},
341 {0x03c1, 0x8000},
342 {0x03c2, 0x8000},
343 {0x03c3, 0x8000},
344 {0x03c4, 0x8000},
345 {0x03c5, 0x8000},
346 {0x03c6, 0x8000},
347 {0x03c7, 0x8000},
348 {0x03c8, 0x8000},
349 {0x03c9, 0x8000},
350 {0x03ca, 0x8000},
351 {0x03cb, 0x8000},
352 {0x03cc, 0x8000},
353 {0x03d0, 0x0000},
354 {0x03d1, 0x0000},
355 {0x03d2, 0x0000},
356 {0x03d3, 0x0000},
357 {0x03d4, 0x2000},
358 {0x03d5, 0x2000},
359 {0x03d6, 0x0000},
360 {0x03d7, 0x0000},
361 {0x03d8, 0x2000},
362 {0x03d9, 0x2000},
363 {0x03da, 0x2000},
364 {0x03db, 0x2000},
365 {0x03dc, 0x0000},
366 {0x03dd, 0x0000},
367 {0x03de, 0x0000},
368 {0x03df, 0x2000},
369 {0x03e0, 0x0000},
370 {0x03e1, 0x0000},
371 {0x03e2, 0x0000},
372 {0x03e3, 0x0000},
373 {0x03e4, 0x0000},
374 {0x03e5, 0x0000},
375 {0x03e6, 0x0000},
376 {0x03e7, 0x0000},
377 {0x03e8, 0x0000},
378 {0x03e9, 0x0000},
379 {0x03ea, 0x0000},
380 {0x03eb, 0x0000},
381 {0x03ec, 0x0000},
382 {0x03ed, 0x0000},
383 {0x03ee, 0x0000},
384 {0x03ef, 0x0000},
385 {0x03f0, 0x0800},
386 {0x03f1, 0x0800},
387 {0x03f2, 0x0800},
388 {0x03f3, 0x0800},
389};
390
391static bool rt5668_volatile_register(struct device *dev, unsigned int reg)
392{
393 switch (reg) {
394 case RT5668_RESET:
395 case RT5668_CBJ_CTRL_2:
396 case RT5668_INT_ST_1:
397 case RT5668_4BTN_IL_CMD_1:
398 case RT5668_AJD1_CTRL:
399 case RT5668_HP_CALIB_CTRL_1:
400 case RT5668_DEVICE_ID:
401 case RT5668_I2C_MODE:
402 case RT5668_HP_CALIB_CTRL_10:
403 case RT5668_EFUSE_CTRL_2:
404 case RT5668_JD_TOP_VC_VTRL:
405 case RT5668_HP_IMP_SENS_CTRL_19:
406 case RT5668_IL_CMD_1:
407 case RT5668_SAR_IL_CMD_2:
408 case RT5668_SAR_IL_CMD_4:
409 case RT5668_SAR_IL_CMD_10:
410 case RT5668_SAR_IL_CMD_11:
411 case RT5668_EFUSE_CTRL_6...RT5668_EFUSE_CTRL_11:
412 case RT5668_HP_CALIB_STA_1...RT5668_HP_CALIB_STA_11:
413 return true;
414 default:
415 return false;
416 }
417}
418
419static bool rt5668_readable_register(struct device *dev, unsigned int reg)
420{
421 switch (reg) {
422 case RT5668_RESET:
423 case RT5668_VERSION_ID:
424 case RT5668_VENDOR_ID:
425 case RT5668_DEVICE_ID:
426 case RT5668_HP_CTRL_1:
427 case RT5668_HP_CTRL_2:
428 case RT5668_HPL_GAIN:
429 case RT5668_HPR_GAIN:
430 case RT5668_I2C_CTRL:
431 case RT5668_CBJ_BST_CTRL:
432 case RT5668_CBJ_CTRL_1:
433 case RT5668_CBJ_CTRL_2:
434 case RT5668_CBJ_CTRL_3:
435 case RT5668_CBJ_CTRL_4:
436 case RT5668_CBJ_CTRL_5:
437 case RT5668_CBJ_CTRL_6:
438 case RT5668_CBJ_CTRL_7:
439 case RT5668_DAC1_DIG_VOL:
440 case RT5668_STO1_ADC_DIG_VOL:
441 case RT5668_STO1_ADC_BOOST:
442 case RT5668_HP_IMP_GAIN_1:
443 case RT5668_HP_IMP_GAIN_2:
444 case RT5668_SIDETONE_CTRL:
445 case RT5668_STO1_ADC_MIXER:
446 case RT5668_AD_DA_MIXER:
447 case RT5668_STO1_DAC_MIXER:
448 case RT5668_A_DAC1_MUX:
449 case RT5668_DIG_INF2_DATA:
450 case RT5668_REC_MIXER:
451 case RT5668_CAL_REC:
452 case RT5668_ALC_BACK_GAIN:
453 case RT5668_PWR_DIG_1:
454 case RT5668_PWR_DIG_2:
455 case RT5668_PWR_ANLG_1:
456 case RT5668_PWR_ANLG_2:
457 case RT5668_PWR_ANLG_3:
458 case RT5668_PWR_MIXER:
459 case RT5668_PWR_VOL:
460 case RT5668_CLK_DET:
461 case RT5668_RESET_LPF_CTRL:
462 case RT5668_RESET_HPF_CTRL:
463 case RT5668_DMIC_CTRL_1:
464 case RT5668_I2S1_SDP:
465 case RT5668_I2S2_SDP:
466 case RT5668_ADDA_CLK_1:
467 case RT5668_ADDA_CLK_2:
468 case RT5668_I2S1_F_DIV_CTRL_1:
469 case RT5668_I2S1_F_DIV_CTRL_2:
470 case RT5668_TDM_CTRL:
471 case RT5668_TDM_ADDA_CTRL_1:
472 case RT5668_TDM_ADDA_CTRL_2:
473 case RT5668_DATA_SEL_CTRL_1:
474 case RT5668_TDM_TCON_CTRL:
475 case RT5668_GLB_CLK:
476 case RT5668_PLL_CTRL_1:
477 case RT5668_PLL_CTRL_2:
478 case RT5668_PLL_TRACK_1:
479 case RT5668_PLL_TRACK_2:
480 case RT5668_PLL_TRACK_3:
481 case RT5668_PLL_TRACK_4:
482 case RT5668_PLL_TRACK_5:
483 case RT5668_PLL_TRACK_6:
484 case RT5668_PLL_TRACK_11:
485 case RT5668_SDW_REF_CLK:
486 case RT5668_DEPOP_1:
487 case RT5668_DEPOP_2:
488 case RT5668_HP_CHARGE_PUMP_1:
489 case RT5668_HP_CHARGE_PUMP_2:
490 case RT5668_MICBIAS_1:
491 case RT5668_MICBIAS_2:
492 case RT5668_PLL_TRACK_12:
493 case RT5668_PLL_TRACK_14:
494 case RT5668_PLL2_CTRL_1:
495 case RT5668_PLL2_CTRL_2:
496 case RT5668_PLL2_CTRL_3:
497 case RT5668_PLL2_CTRL_4:
498 case RT5668_RC_CLK_CTRL:
499 case RT5668_I2S_M_CLK_CTRL_1:
500 case RT5668_I2S2_F_DIV_CTRL_1:
501 case RT5668_I2S2_F_DIV_CTRL_2:
502 case RT5668_EQ_CTRL_1:
503 case RT5668_EQ_CTRL_2:
504 case RT5668_IRQ_CTRL_1:
505 case RT5668_IRQ_CTRL_2:
506 case RT5668_IRQ_CTRL_3:
507 case RT5668_IRQ_CTRL_4:
508 case RT5668_INT_ST_1:
509 case RT5668_GPIO_CTRL_1:
510 case RT5668_GPIO_CTRL_2:
511 case RT5668_GPIO_CTRL_3:
512 case RT5668_HP_AMP_DET_CTRL_1:
513 case RT5668_HP_AMP_DET_CTRL_2:
514 case RT5668_MID_HP_AMP_DET:
515 case RT5668_LOW_HP_AMP_DET:
516 case RT5668_DELAY_BUF_CTRL:
517 case RT5668_SV_ZCD_1:
518 case RT5668_SV_ZCD_2:
519 case RT5668_IL_CMD_1:
520 case RT5668_IL_CMD_2:
521 case RT5668_IL_CMD_3:
522 case RT5668_IL_CMD_4:
523 case RT5668_IL_CMD_5:
524 case RT5668_IL_CMD_6:
525 case RT5668_4BTN_IL_CMD_1:
526 case RT5668_4BTN_IL_CMD_2:
527 case RT5668_4BTN_IL_CMD_3:
528 case RT5668_4BTN_IL_CMD_4:
529 case RT5668_4BTN_IL_CMD_5:
530 case RT5668_4BTN_IL_CMD_6:
531 case RT5668_4BTN_IL_CMD_7:
532 case RT5668_ADC_STO1_HP_CTRL_1:
533 case RT5668_ADC_STO1_HP_CTRL_2:
534 case RT5668_AJD1_CTRL:
535 case RT5668_JD1_THD:
536 case RT5668_JD2_THD:
537 case RT5668_JD_CTRL_1:
538 case RT5668_DUMMY_1:
539 case RT5668_DUMMY_2:
540 case RT5668_DUMMY_3:
541 case RT5668_DAC_ADC_DIG_VOL1:
542 case RT5668_BIAS_CUR_CTRL_2:
543 case RT5668_BIAS_CUR_CTRL_3:
544 case RT5668_BIAS_CUR_CTRL_4:
545 case RT5668_BIAS_CUR_CTRL_5:
546 case RT5668_BIAS_CUR_CTRL_6:
547 case RT5668_BIAS_CUR_CTRL_7:
548 case RT5668_BIAS_CUR_CTRL_8:
549 case RT5668_BIAS_CUR_CTRL_9:
550 case RT5668_BIAS_CUR_CTRL_10:
551 case RT5668_VREF_REC_OP_FB_CAP_CTRL:
552 case RT5668_CHARGE_PUMP_1:
553 case RT5668_DIG_IN_CTRL_1:
554 case RT5668_PAD_DRIVING_CTRL:
555 case RT5668_SOFT_RAMP_DEPOP:
556 case RT5668_CHOP_DAC:
557 case RT5668_CHOP_ADC:
558 case RT5668_CALIB_ADC_CTRL:
559 case RT5668_VOL_TEST:
560 case RT5668_SPKVDD_DET_STA:
561 case RT5668_TEST_MODE_CTRL_1:
562 case RT5668_TEST_MODE_CTRL_2:
563 case RT5668_TEST_MODE_CTRL_3:
564 case RT5668_TEST_MODE_CTRL_4:
565 case RT5668_TEST_MODE_CTRL_5:
566 case RT5668_PLL1_INTERNAL:
567 case RT5668_PLL2_INTERNAL:
568 case RT5668_STO_NG2_CTRL_1:
569 case RT5668_STO_NG2_CTRL_2:
570 case RT5668_STO_NG2_CTRL_3:
571 case RT5668_STO_NG2_CTRL_4:
572 case RT5668_STO_NG2_CTRL_5:
573 case RT5668_STO_NG2_CTRL_6:
574 case RT5668_STO_NG2_CTRL_7:
575 case RT5668_STO_NG2_CTRL_8:
576 case RT5668_STO_NG2_CTRL_9:
577 case RT5668_STO_NG2_CTRL_10:
578 case RT5668_STO1_DAC_SIL_DET:
579 case RT5668_SIL_PSV_CTRL1:
580 case RT5668_SIL_PSV_CTRL2:
581 case RT5668_SIL_PSV_CTRL3:
582 case RT5668_SIL_PSV_CTRL4:
583 case RT5668_SIL_PSV_CTRL5:
584 case RT5668_HP_IMP_SENS_CTRL_01:
585 case RT5668_HP_IMP_SENS_CTRL_02:
586 case RT5668_HP_IMP_SENS_CTRL_03:
587 case RT5668_HP_IMP_SENS_CTRL_04:
588 case RT5668_HP_IMP_SENS_CTRL_05:
589 case RT5668_HP_IMP_SENS_CTRL_06:
590 case RT5668_HP_IMP_SENS_CTRL_07:
591 case RT5668_HP_IMP_SENS_CTRL_08:
592 case RT5668_HP_IMP_SENS_CTRL_09:
593 case RT5668_HP_IMP_SENS_CTRL_10:
594 case RT5668_HP_IMP_SENS_CTRL_11:
595 case RT5668_HP_IMP_SENS_CTRL_12:
596 case RT5668_HP_IMP_SENS_CTRL_13:
597 case RT5668_HP_IMP_SENS_CTRL_14:
598 case RT5668_HP_IMP_SENS_CTRL_15:
599 case RT5668_HP_IMP_SENS_CTRL_16:
600 case RT5668_HP_IMP_SENS_CTRL_17:
601 case RT5668_HP_IMP_SENS_CTRL_18:
602 case RT5668_HP_IMP_SENS_CTRL_19:
603 case RT5668_HP_IMP_SENS_CTRL_20:
604 case RT5668_HP_IMP_SENS_CTRL_21:
605 case RT5668_HP_IMP_SENS_CTRL_22:
606 case RT5668_HP_IMP_SENS_CTRL_23:
607 case RT5668_HP_IMP_SENS_CTRL_24:
608 case RT5668_HP_IMP_SENS_CTRL_25:
609 case RT5668_HP_IMP_SENS_CTRL_26:
610 case RT5668_HP_IMP_SENS_CTRL_27:
611 case RT5668_HP_IMP_SENS_CTRL_28:
612 case RT5668_HP_IMP_SENS_CTRL_29:
613 case RT5668_HP_IMP_SENS_CTRL_30:
614 case RT5668_HP_IMP_SENS_CTRL_31:
615 case RT5668_HP_IMP_SENS_CTRL_32:
616 case RT5668_HP_IMP_SENS_CTRL_33:
617 case RT5668_HP_IMP_SENS_CTRL_34:
618 case RT5668_HP_IMP_SENS_CTRL_35:
619 case RT5668_HP_IMP_SENS_CTRL_36:
620 case RT5668_HP_IMP_SENS_CTRL_37:
621 case RT5668_HP_IMP_SENS_CTRL_38:
622 case RT5668_HP_IMP_SENS_CTRL_39:
623 case RT5668_HP_IMP_SENS_CTRL_40:
624 case RT5668_HP_IMP_SENS_CTRL_41:
625 case RT5668_HP_IMP_SENS_CTRL_42:
626 case RT5668_HP_IMP_SENS_CTRL_43:
627 case RT5668_HP_LOGIC_CTRL_1:
628 case RT5668_HP_LOGIC_CTRL_2:
629 case RT5668_HP_LOGIC_CTRL_3:
630 case RT5668_HP_CALIB_CTRL_1:
631 case RT5668_HP_CALIB_CTRL_2:
632 case RT5668_HP_CALIB_CTRL_3:
633 case RT5668_HP_CALIB_CTRL_4:
634 case RT5668_HP_CALIB_CTRL_5:
635 case RT5668_HP_CALIB_CTRL_6:
636 case RT5668_HP_CALIB_CTRL_7:
637 case RT5668_HP_CALIB_CTRL_9:
638 case RT5668_HP_CALIB_CTRL_10:
639 case RT5668_HP_CALIB_CTRL_11:
640 case RT5668_HP_CALIB_STA_1:
641 case RT5668_HP_CALIB_STA_2:
642 case RT5668_HP_CALIB_STA_3:
643 case RT5668_HP_CALIB_STA_4:
644 case RT5668_HP_CALIB_STA_5:
645 case RT5668_HP_CALIB_STA_6:
646 case RT5668_HP_CALIB_STA_7:
647 case RT5668_HP_CALIB_STA_8:
648 case RT5668_HP_CALIB_STA_9:
649 case RT5668_HP_CALIB_STA_10:
650 case RT5668_HP_CALIB_STA_11:
651 case RT5668_SAR_IL_CMD_1:
652 case RT5668_SAR_IL_CMD_2:
653 case RT5668_SAR_IL_CMD_3:
654 case RT5668_SAR_IL_CMD_4:
655 case RT5668_SAR_IL_CMD_5:
656 case RT5668_SAR_IL_CMD_6:
657 case RT5668_SAR_IL_CMD_7:
658 case RT5668_SAR_IL_CMD_8:
659 case RT5668_SAR_IL_CMD_9:
660 case RT5668_SAR_IL_CMD_10:
661 case RT5668_SAR_IL_CMD_11:
662 case RT5668_SAR_IL_CMD_12:
663 case RT5668_SAR_IL_CMD_13:
664 case RT5668_EFUSE_CTRL_1:
665 case RT5668_EFUSE_CTRL_2:
666 case RT5668_EFUSE_CTRL_3:
667 case RT5668_EFUSE_CTRL_4:
668 case RT5668_EFUSE_CTRL_5:
669 case RT5668_EFUSE_CTRL_6:
670 case RT5668_EFUSE_CTRL_7:
671 case RT5668_EFUSE_CTRL_8:
672 case RT5668_EFUSE_CTRL_9:
673 case RT5668_EFUSE_CTRL_10:
674 case RT5668_EFUSE_CTRL_11:
675 case RT5668_JD_TOP_VC_VTRL:
676 case RT5668_DRC1_CTRL_0:
677 case RT5668_DRC1_CTRL_1:
678 case RT5668_DRC1_CTRL_2:
679 case RT5668_DRC1_CTRL_3:
680 case RT5668_DRC1_CTRL_4:
681 case RT5668_DRC1_CTRL_5:
682 case RT5668_DRC1_CTRL_6:
683 case RT5668_DRC1_HARD_LMT_CTRL_1:
684 case RT5668_DRC1_HARD_LMT_CTRL_2:
685 case RT5668_DRC1_PRIV_1:
686 case RT5668_DRC1_PRIV_2:
687 case RT5668_DRC1_PRIV_3:
688 case RT5668_DRC1_PRIV_4:
689 case RT5668_DRC1_PRIV_5:
690 case RT5668_DRC1_PRIV_6:
691 case RT5668_DRC1_PRIV_7:
692 case RT5668_DRC1_PRIV_8:
693 case RT5668_EQ_AUTO_RCV_CTRL1:
694 case RT5668_EQ_AUTO_RCV_CTRL2:
695 case RT5668_EQ_AUTO_RCV_CTRL3:
696 case RT5668_EQ_AUTO_RCV_CTRL4:
697 case RT5668_EQ_AUTO_RCV_CTRL5:
698 case RT5668_EQ_AUTO_RCV_CTRL6:
699 case RT5668_EQ_AUTO_RCV_CTRL7:
700 case RT5668_EQ_AUTO_RCV_CTRL8:
701 case RT5668_EQ_AUTO_RCV_CTRL9:
702 case RT5668_EQ_AUTO_RCV_CTRL10:
703 case RT5668_EQ_AUTO_RCV_CTRL11:
704 case RT5668_EQ_AUTO_RCV_CTRL12:
705 case RT5668_EQ_AUTO_RCV_CTRL13:
706 case RT5668_ADC_L_EQ_LPF1_A1:
707 case RT5668_R_EQ_LPF1_A1:
708 case RT5668_L_EQ_LPF1_H0:
709 case RT5668_R_EQ_LPF1_H0:
710 case RT5668_L_EQ_BPF1_A1:
711 case RT5668_R_EQ_BPF1_A1:
712 case RT5668_L_EQ_BPF1_A2:
713 case RT5668_R_EQ_BPF1_A2:
714 case RT5668_L_EQ_BPF1_H0:
715 case RT5668_R_EQ_BPF1_H0:
716 case RT5668_L_EQ_BPF2_A1:
717 case RT5668_R_EQ_BPF2_A1:
718 case RT5668_L_EQ_BPF2_A2:
719 case RT5668_R_EQ_BPF2_A2:
720 case RT5668_L_EQ_BPF2_H0:
721 case RT5668_R_EQ_BPF2_H0:
722 case RT5668_L_EQ_BPF3_A1:
723 case RT5668_R_EQ_BPF3_A1:
724 case RT5668_L_EQ_BPF3_A2:
725 case RT5668_R_EQ_BPF3_A2:
726 case RT5668_L_EQ_BPF3_H0:
727 case RT5668_R_EQ_BPF3_H0:
728 case RT5668_L_EQ_BPF4_A1:
729 case RT5668_R_EQ_BPF4_A1:
730 case RT5668_L_EQ_BPF4_A2:
731 case RT5668_R_EQ_BPF4_A2:
732 case RT5668_L_EQ_BPF4_H0:
733 case RT5668_R_EQ_BPF4_H0:
734 case RT5668_L_EQ_HPF1_A1:
735 case RT5668_R_EQ_HPF1_A1:
736 case RT5668_L_EQ_HPF1_H0:
737 case RT5668_R_EQ_HPF1_H0:
738 case RT5668_L_EQ_PRE_VOL:
739 case RT5668_R_EQ_PRE_VOL:
740 case RT5668_L_EQ_POST_VOL:
741 case RT5668_R_EQ_POST_VOL:
742 case RT5668_I2C_MODE:
743 return true;
744 default:
745 return false;
746 }
747}
748
749static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
750static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
751static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
752static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
753
754
755static const DECLARE_TLV_DB_RANGE(bst_tlv,
756 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
757 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
758 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
759 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
760 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
761 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
762 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
763);
764
765
766static const char * const rt5668_data_select[] = {
767 "L/R", "R/L", "L/L", "R/R"
768};
769
770static SOC_ENUM_SINGLE_DECL(rt5668_if2_adc_enum,
771 RT5668_DIG_INF2_DATA, RT5668_IF2_ADC_SEL_SFT, rt5668_data_select);
772
773static SOC_ENUM_SINGLE_DECL(rt5668_if1_01_adc_enum,
774 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC1_SEL_SFT, rt5668_data_select);
775
776static SOC_ENUM_SINGLE_DECL(rt5668_if1_23_adc_enum,
777 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC2_SEL_SFT, rt5668_data_select);
778
779static SOC_ENUM_SINGLE_DECL(rt5668_if1_45_adc_enum,
780 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC3_SEL_SFT, rt5668_data_select);
781
782static SOC_ENUM_SINGLE_DECL(rt5668_if1_67_adc_enum,
783 RT5668_TDM_ADDA_CTRL_1, RT5668_IF1_ADC4_SEL_SFT, rt5668_data_select);
784
785static const struct snd_kcontrol_new rt5668_if2_adc_swap_mux =
786 SOC_DAPM_ENUM("IF2 ADC Swap Mux", rt5668_if2_adc_enum);
787
788static const struct snd_kcontrol_new rt5668_if1_01_adc_swap_mux =
789 SOC_DAPM_ENUM("IF1 01 ADC Swap Mux", rt5668_if1_01_adc_enum);
790
791static const struct snd_kcontrol_new rt5668_if1_23_adc_swap_mux =
792 SOC_DAPM_ENUM("IF1 23 ADC Swap Mux", rt5668_if1_23_adc_enum);
793
794static const struct snd_kcontrol_new rt5668_if1_45_adc_swap_mux =
795 SOC_DAPM_ENUM("IF1 45 ADC Swap Mux", rt5668_if1_45_adc_enum);
796
797static const struct snd_kcontrol_new rt5668_if1_67_adc_swap_mux =
798 SOC_DAPM_ENUM("IF1 67 ADC Swap Mux", rt5668_if1_67_adc_enum);
799
800static void rt5668_reset(struct regmap *regmap)
801{
802 regmap_write(regmap, RT5668_RESET, 0);
803 regmap_write(regmap, RT5668_I2C_MODE, 1);
804}
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819int rt5668_sel_asrc_clk_src(struct snd_soc_component *component,
820 unsigned int filter_mask, unsigned int clk_src)
821{
822
823 switch (clk_src) {
824 case RT5668_CLK_SEL_SYS:
825 case RT5668_CLK_SEL_I2S1_ASRC:
826 case RT5668_CLK_SEL_I2S2_ASRC:
827 break;
828
829 default:
830 return -EINVAL;
831 }
832
833 if (filter_mask & RT5668_DA_STEREO1_FILTER) {
834 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_2,
835 RT5668_FILTER_CLK_SEL_MASK,
836 clk_src << RT5668_FILTER_CLK_SEL_SFT);
837 }
838
839 if (filter_mask & RT5668_AD_STEREO1_FILTER) {
840 snd_soc_component_update_bits(component, RT5668_PLL_TRACK_3,
841 RT5668_FILTER_CLK_SEL_MASK,
842 clk_src << RT5668_FILTER_CLK_SEL_SFT);
843 }
844
845 return 0;
846}
847EXPORT_SYMBOL_GPL(rt5668_sel_asrc_clk_src);
848
849static int rt5668_button_detect(struct snd_soc_component *component)
850{
851 int btn_type, val;
852
853 val = snd_soc_component_read32(component, RT5668_4BTN_IL_CMD_1);
854 btn_type = val & 0xfff0;
855 snd_soc_component_write(component, RT5668_4BTN_IL_CMD_1, val);
856 pr_debug("%s btn_type=%x\n", __func__, btn_type);
857
858 return btn_type;
859}
860
861static void rt5668_enable_push_button_irq(struct snd_soc_component *component,
862 bool enable)
863{
864 if (enable) {
865 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
866 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_EN);
867 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
868 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_BTN);
869 snd_soc_component_write(component, RT5668_IL_CMD_1, 0x0040);
870 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
871 RT5668_4BTN_IL_MASK | RT5668_4BTN_IL_RST_MASK,
872 RT5668_4BTN_IL_EN | RT5668_4BTN_IL_NOR);
873 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
874 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_EN);
875 } else {
876 snd_soc_component_update_bits(component, RT5668_IRQ_CTRL_3,
877 RT5668_IL_IRQ_MASK, RT5668_IL_IRQ_DIS);
878 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
879 RT5668_SAR_BUTT_DET_MASK, RT5668_SAR_BUTT_DET_DIS);
880 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
881 RT5668_4BTN_IL_MASK, RT5668_4BTN_IL_DIS);
882 snd_soc_component_update_bits(component, RT5668_4BTN_IL_CMD_2,
883 RT5668_4BTN_IL_RST_MASK, RT5668_4BTN_IL_RST);
884 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_13,
885 RT5668_SAR_SOUR_MASK, RT5668_SAR_SOUR_TYPE);
886 }
887}
888
889
890
891
892
893
894
895
896
897
898static int rt5668_headset_detect(struct snd_soc_component *component,
899 int jack_insert)
900{
901 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
902 struct snd_soc_dapm_context *dapm =
903 snd_soc_component_get_dapm(component);
904 unsigned int val, count;
905
906 if (jack_insert) {
907 snd_soc_dapm_force_enable_pin(dapm, "CBJ Power");
908 snd_soc_dapm_sync(dapm);
909 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
910 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_HIGH);
911
912 count = 0;
913 val = snd_soc_component_read32(component, RT5668_CBJ_CTRL_2)
914 & RT5668_JACK_TYPE_MASK;
915 while (val == 0 && count < 50) {
916 usleep_range(10000, 15000);
917 val = snd_soc_component_read32(component,
918 RT5668_CBJ_CTRL_2) & RT5668_JACK_TYPE_MASK;
919 count++;
920 }
921
922 switch (val) {
923 case 0x1:
924 case 0x2:
925 rt5668->jack_type = SND_JACK_HEADSET;
926 rt5668_enable_push_button_irq(component, true);
927 break;
928 default:
929 rt5668->jack_type = SND_JACK_HEADPHONE;
930 }
931
932 } else {
933 rt5668_enable_push_button_irq(component, false);
934 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_1,
935 RT5668_TRIG_JD_MASK, RT5668_TRIG_JD_LOW);
936 snd_soc_dapm_disable_pin(dapm, "CBJ Power");
937 snd_soc_dapm_sync(dapm);
938
939 rt5668->jack_type = 0;
940 }
941
942 dev_dbg(component->dev, "jack_type = %d\n", rt5668->jack_type);
943 return rt5668->jack_type;
944}
945
946static irqreturn_t rt5668_irq(int irq, void *data)
947{
948 struct rt5668_priv *rt5668 = data;
949
950 mod_delayed_work(system_power_efficient_wq,
951 &rt5668->jack_detect_work, msecs_to_jiffies(250));
952
953 return IRQ_HANDLED;
954}
955
956static void rt5668_jd_check_handler(struct work_struct *work)
957{
958 struct rt5668_priv *rt5668 = container_of(work, struct rt5668_priv,
959 jd_check_work.work);
960
961 if (snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL)
962 & RT5668_JDH_RS_MASK) {
963
964 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
965
966 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
967 SND_JACK_HEADSET |
968 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
969 SND_JACK_BTN_2 | SND_JACK_BTN_3);
970 } else {
971 schedule_delayed_work(&rt5668->jd_check_work, 500);
972 }
973}
974
975static int rt5668_set_jack_detect(struct snd_soc_component *component,
976 struct snd_soc_jack *hs_jack, void *data)
977{
978 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
979
980 switch (rt5668->pdata.jd_src) {
981 case RT5668_JD1:
982 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_2,
983 RT5668_EXT_JD_SRC, RT5668_EXT_JD_SRC_MANUAL);
984 snd_soc_component_write(component, RT5668_CBJ_CTRL_1, 0xd002);
985 snd_soc_component_update_bits(component, RT5668_CBJ_CTRL_3,
986 RT5668_CBJ_IN_BUF_EN, RT5668_CBJ_IN_BUF_EN);
987 snd_soc_component_update_bits(component, RT5668_SAR_IL_CMD_1,
988 RT5668_SAR_POW_MASK, RT5668_SAR_POW_EN);
989 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
990 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_IRQ);
991 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
992 RT5668_POW_IRQ | RT5668_POW_JDH |
993 RT5668_POW_ANA, RT5668_POW_IRQ |
994 RT5668_POW_JDH | RT5668_POW_ANA);
995 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_2,
996 RT5668_PWR_JDH | RT5668_PWR_JDL,
997 RT5668_PWR_JDH | RT5668_PWR_JDL);
998 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
999 RT5668_JD1_EN_MASK | RT5668_JD1_POL_MASK,
1000 RT5668_JD1_EN | RT5668_JD1_POL_NOR);
1001 mod_delayed_work(system_power_efficient_wq,
1002 &rt5668->jack_detect_work, msecs_to_jiffies(250));
1003 break;
1004
1005 case RT5668_JD_NULL:
1006 regmap_update_bits(rt5668->regmap, RT5668_IRQ_CTRL_2,
1007 RT5668_JD1_EN_MASK, RT5668_JD1_DIS);
1008 regmap_update_bits(rt5668->regmap, RT5668_RC_CLK_CTRL,
1009 RT5668_POW_JDH | RT5668_POW_JDL, 0);
1010 break;
1011
1012 default:
1013 dev_warn(component->dev, "Wrong JD source\n");
1014 break;
1015 }
1016
1017 rt5668->hs_jack = hs_jack;
1018
1019 return 0;
1020}
1021
1022static void rt5668_jack_detect_handler(struct work_struct *work)
1023{
1024 struct rt5668_priv *rt5668 =
1025 container_of(work, struct rt5668_priv, jack_detect_work.work);
1026 int val, btn_type;
1027
1028 while (!rt5668->component)
1029 usleep_range(10000, 15000);
1030
1031 while (!rt5668->component->card->instantiated)
1032 usleep_range(10000, 15000);
1033
1034 mutex_lock(&rt5668->calibrate_mutex);
1035
1036 val = snd_soc_component_read32(rt5668->component, RT5668_AJD1_CTRL)
1037 & RT5668_JDH_RS_MASK;
1038 if (!val) {
1039
1040 if (rt5668->jack_type == 0) {
1041
1042 rt5668->jack_type =
1043 rt5668_headset_detect(rt5668->component, 1);
1044 } else {
1045
1046 rt5668->jack_type = SND_JACK_HEADSET;
1047 btn_type = rt5668_button_detect(rt5668->component);
1048
1049
1050
1051
1052
1053
1054
1055 switch (btn_type) {
1056 case 0x8000:
1057 case 0x4000:
1058 case 0x2000:
1059 rt5668->jack_type |= SND_JACK_BTN_0;
1060 break;
1061 case 0x1000:
1062 case 0x0800:
1063 case 0x0400:
1064 rt5668->jack_type |= SND_JACK_BTN_1;
1065 break;
1066 case 0x0200:
1067 case 0x0100:
1068 case 0x0080:
1069 rt5668->jack_type |= SND_JACK_BTN_2;
1070 break;
1071 case 0x0040:
1072 case 0x0020:
1073 case 0x0010:
1074 rt5668->jack_type |= SND_JACK_BTN_3;
1075 break;
1076 case 0x0000:
1077 break;
1078 default:
1079 btn_type = 0;
1080 dev_err(rt5668->component->dev,
1081 "Unexpected button code 0x%04x\n",
1082 btn_type);
1083 break;
1084 }
1085 }
1086 } else {
1087
1088 rt5668->jack_type = rt5668_headset_detect(rt5668->component, 0);
1089 }
1090
1091 snd_soc_jack_report(rt5668->hs_jack, rt5668->jack_type,
1092 SND_JACK_HEADSET |
1093 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1094 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1095
1096 if (rt5668->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1097 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1098 schedule_delayed_work(&rt5668->jd_check_work, 0);
1099 else
1100 cancel_delayed_work_sync(&rt5668->jd_check_work);
1101
1102 mutex_unlock(&rt5668->calibrate_mutex);
1103}
1104
1105static const struct snd_kcontrol_new rt5668_snd_controls[] = {
1106
1107 SOC_DOUBLE_R_TLV("Headphone Playback Volume", RT5668_HPL_GAIN,
1108 RT5668_HPR_GAIN, RT5668_G_HP_SFT, 15, 1, hp_vol_tlv),
1109
1110
1111 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5668_DAC1_DIG_VOL,
1112 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 175, 0, dac_vol_tlv),
1113
1114
1115 SOC_SINGLE_TLV("CBJ Boost Volume", RT5668_CBJ_BST_CTRL,
1116 RT5668_BST_CBJ_SFT, 8, 0, bst_tlv),
1117
1118
1119 SOC_DOUBLE("STO1 ADC Capture Switch", RT5668_STO1_ADC_DIG_VOL,
1120 RT5668_L_MUTE_SFT, RT5668_R_MUTE_SFT, 1, 1),
1121 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5668_STO1_ADC_DIG_VOL,
1122 RT5668_L_VOL_SFT, RT5668_R_VOL_SFT, 127, 0, adc_vol_tlv),
1123
1124
1125 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5668_STO1_ADC_BOOST,
1126 RT5668_STO1_ADC_L_BST_SFT, RT5668_STO1_ADC_R_BST_SFT,
1127 3, 0, adc_bst_tlv),
1128};
1129
1130
1131static int rt5668_div_sel(struct rt5668_priv *rt5668,
1132 int target, const int div[], int size)
1133{
1134 int i;
1135
1136 if (rt5668->sysclk < target) {
1137 pr_err("sysclk rate %d is too low\n",
1138 rt5668->sysclk);
1139 return 0;
1140 }
1141
1142 for (i = 0; i < size - 1; i++) {
1143 pr_info("div[%d]=%d\n", i, div[i]);
1144 if (target * div[i] == rt5668->sysclk)
1145 return i;
1146 if (target * div[i + 1] > rt5668->sysclk) {
1147 pr_err("can't find div for sysclk %d\n",
1148 rt5668->sysclk);
1149 return i;
1150 }
1151 }
1152
1153 if (target * div[i] < rt5668->sysclk)
1154 pr_err("sysclk rate %d is too high\n",
1155 rt5668->sysclk);
1156
1157 return size - 1;
1158
1159}
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1172 struct snd_kcontrol *kcontrol, int event)
1173{
1174 struct snd_soc_component *component =
1175 snd_soc_dapm_to_component(w->dapm);
1176 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1177 int idx = -EINVAL;
1178 static const int div[] = {2, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128};
1179
1180 idx = rt5668_div_sel(rt5668, 1500000, div, ARRAY_SIZE(div));
1181
1182 snd_soc_component_update_bits(component, RT5668_DMIC_CTRL_1,
1183 RT5668_DMIC_CLK_MASK, idx << RT5668_DMIC_CLK_SFT);
1184
1185 return 0;
1186}
1187
1188static int set_filter_clk(struct snd_soc_dapm_widget *w,
1189 struct snd_kcontrol *kcontrol, int event)
1190{
1191 struct snd_soc_component *component =
1192 snd_soc_dapm_to_component(w->dapm);
1193 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1194 int ref, val, reg, idx = -EINVAL;
1195 static const int div[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48};
1196
1197 val = snd_soc_component_read32(component, RT5668_GPIO_CTRL_1) &
1198 RT5668_GP4_PIN_MASK;
1199 if (w->shift == RT5668_PWR_ADC_S1F_BIT &&
1200 val == RT5668_GP4_PIN_ADCDAT2)
1201 ref = 256 * rt5668->lrck[RT5668_AIF2];
1202 else
1203 ref = 256 * rt5668->lrck[RT5668_AIF1];
1204
1205 idx = rt5668_div_sel(rt5668, ref, div, ARRAY_SIZE(div));
1206
1207 if (w->shift == RT5668_PWR_ADC_S1F_BIT)
1208 reg = RT5668_PLL_TRACK_3;
1209 else
1210 reg = RT5668_PLL_TRACK_2;
1211
1212 snd_soc_component_update_bits(component, reg,
1213 RT5668_FILTER_CLK_SEL_MASK, idx << RT5668_FILTER_CLK_SEL_SFT);
1214
1215 return 0;
1216}
1217
1218static int is_sys_clk_from_pll1(struct snd_soc_dapm_widget *w,
1219 struct snd_soc_dapm_widget *sink)
1220{
1221 unsigned int val;
1222 struct snd_soc_component *component =
1223 snd_soc_dapm_to_component(w->dapm);
1224
1225 val = snd_soc_component_read32(component, RT5668_GLB_CLK);
1226 val &= RT5668_SCLK_SRC_MASK;
1227 if (val == RT5668_SCLK_SRC_PLL1)
1228 return 1;
1229 else
1230 return 0;
1231}
1232
1233static int is_using_asrc(struct snd_soc_dapm_widget *w,
1234 struct snd_soc_dapm_widget *sink)
1235{
1236 unsigned int reg, shift, val;
1237 struct snd_soc_component *component =
1238 snd_soc_dapm_to_component(w->dapm);
1239
1240 switch (w->shift) {
1241 case RT5668_ADC_STO1_ASRC_SFT:
1242 reg = RT5668_PLL_TRACK_3;
1243 shift = RT5668_FILTER_CLK_SEL_SFT;
1244 break;
1245 case RT5668_DAC_STO1_ASRC_SFT:
1246 reg = RT5668_PLL_TRACK_2;
1247 shift = RT5668_FILTER_CLK_SEL_SFT;
1248 break;
1249 default:
1250 return 0;
1251 }
1252
1253 val = (snd_soc_component_read32(component, reg) >> shift) & 0xf;
1254 switch (val) {
1255 case RT5668_CLK_SEL_I2S1_ASRC:
1256 case RT5668_CLK_SEL_I2S2_ASRC:
1257 return 1;
1258 default:
1259 return 0;
1260 }
1261
1262}
1263
1264
1265static const struct snd_kcontrol_new rt5668_sto1_adc_l_mix[] = {
1266 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1267 RT5668_M_STO1_ADC_L1_SFT, 1, 1),
1268 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1269 RT5668_M_STO1_ADC_L2_SFT, 1, 1),
1270};
1271
1272static const struct snd_kcontrol_new rt5668_sto1_adc_r_mix[] = {
1273 SOC_DAPM_SINGLE("ADC1 Switch", RT5668_STO1_ADC_MIXER,
1274 RT5668_M_STO1_ADC_R1_SFT, 1, 1),
1275 SOC_DAPM_SINGLE("ADC2 Switch", RT5668_STO1_ADC_MIXER,
1276 RT5668_M_STO1_ADC_R2_SFT, 1, 1),
1277};
1278
1279static const struct snd_kcontrol_new rt5668_dac_l_mix[] = {
1280 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1281 RT5668_M_ADCMIX_L_SFT, 1, 1),
1282 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1283 RT5668_M_DAC1_L_SFT, 1, 1),
1284};
1285
1286static const struct snd_kcontrol_new rt5668_dac_r_mix[] = {
1287 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5668_AD_DA_MIXER,
1288 RT5668_M_ADCMIX_R_SFT, 1, 1),
1289 SOC_DAPM_SINGLE("DAC1 Switch", RT5668_AD_DA_MIXER,
1290 RT5668_M_DAC1_R_SFT, 1, 1),
1291};
1292
1293static const struct snd_kcontrol_new rt5668_sto1_dac_l_mix[] = {
1294 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1295 RT5668_M_DAC_L1_STO_L_SFT, 1, 1),
1296 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1297 RT5668_M_DAC_R1_STO_L_SFT, 1, 1),
1298};
1299
1300static const struct snd_kcontrol_new rt5668_sto1_dac_r_mix[] = {
1301 SOC_DAPM_SINGLE("DAC L1 Switch", RT5668_STO1_DAC_MIXER,
1302 RT5668_M_DAC_L1_STO_R_SFT, 1, 1),
1303 SOC_DAPM_SINGLE("DAC R1 Switch", RT5668_STO1_DAC_MIXER,
1304 RT5668_M_DAC_R1_STO_R_SFT, 1, 1),
1305};
1306
1307
1308static const struct snd_kcontrol_new rt5668_rec1_l_mix[] = {
1309 SOC_DAPM_SINGLE("CBJ Switch", RT5668_REC_MIXER,
1310 RT5668_M_CBJ_RM1_L_SFT, 1, 1),
1311};
1312
1313
1314
1315static const char * const rt5668_sto1_adc1_src[] = {
1316 "DAC MIX", "ADC"
1317};
1318
1319static SOC_ENUM_SINGLE_DECL(
1320 rt5668_sto1_adc1l_enum, RT5668_STO1_ADC_MIXER,
1321 RT5668_STO1_ADC1L_SRC_SFT, rt5668_sto1_adc1_src);
1322
1323static const struct snd_kcontrol_new rt5668_sto1_adc1l_mux =
1324 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1l_enum);
1325
1326static SOC_ENUM_SINGLE_DECL(
1327 rt5668_sto1_adc1r_enum, RT5668_STO1_ADC_MIXER,
1328 RT5668_STO1_ADC1R_SRC_SFT, rt5668_sto1_adc1_src);
1329
1330static const struct snd_kcontrol_new rt5668_sto1_adc1r_mux =
1331 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5668_sto1_adc1r_enum);
1332
1333
1334
1335static const char * const rt5668_sto1_adc_src[] = {
1336 "ADC1 L", "ADC1 R"
1337};
1338
1339static SOC_ENUM_SINGLE_DECL(
1340 rt5668_sto1_adcl_enum, RT5668_STO1_ADC_MIXER,
1341 RT5668_STO1_ADCL_SRC_SFT, rt5668_sto1_adc_src);
1342
1343static const struct snd_kcontrol_new rt5668_sto1_adcl_mux =
1344 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5668_sto1_adcl_enum);
1345
1346static SOC_ENUM_SINGLE_DECL(
1347 rt5668_sto1_adcr_enum, RT5668_STO1_ADC_MIXER,
1348 RT5668_STO1_ADCR_SRC_SFT, rt5668_sto1_adc_src);
1349
1350static const struct snd_kcontrol_new rt5668_sto1_adcr_mux =
1351 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5668_sto1_adcr_enum);
1352
1353
1354
1355static const char * const rt5668_sto1_adc2_src[] = {
1356 "DAC MIX", "DMIC"
1357};
1358
1359static SOC_ENUM_SINGLE_DECL(
1360 rt5668_sto1_adc2l_enum, RT5668_STO1_ADC_MIXER,
1361 RT5668_STO1_ADC2L_SRC_SFT, rt5668_sto1_adc2_src);
1362
1363static const struct snd_kcontrol_new rt5668_sto1_adc2l_mux =
1364 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5668_sto1_adc2l_enum);
1365
1366static SOC_ENUM_SINGLE_DECL(
1367 rt5668_sto1_adc2r_enum, RT5668_STO1_ADC_MIXER,
1368 RT5668_STO1_ADC2R_SRC_SFT, rt5668_sto1_adc2_src);
1369
1370static const struct snd_kcontrol_new rt5668_sto1_adc2r_mux =
1371 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5668_sto1_adc2r_enum);
1372
1373
1374static const unsigned int rt5668_if1_adc_slot_values[] = {
1375 0,
1376 2,
1377 4,
1378 6,
1379};
1380
1381static const char * const rt5668_if1_adc_slot_src[] = {
1382 "Slot 0", "Slot 2", "Slot 4", "Slot 6"
1383};
1384
1385static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_if1_adc_slot_enum,
1386 RT5668_TDM_CTRL, RT5668_TDM_ADC_LCA_SFT, RT5668_TDM_ADC_LCA_MASK,
1387 rt5668_if1_adc_slot_src, rt5668_if1_adc_slot_values);
1388
1389static const struct snd_kcontrol_new rt5668_if1_adc_slot_mux =
1390 SOC_DAPM_ENUM("IF1 ADC Slot location", rt5668_if1_adc_slot_enum);
1391
1392
1393
1394static const char * const rt5668_alg_dac1_src[] = {
1395 "Stereo1 DAC Mixer", "DAC1"
1396};
1397
1398static SOC_ENUM_SINGLE_DECL(
1399 rt5668_alg_dac_l1_enum, RT5668_A_DAC1_MUX,
1400 RT5668_A_DACL1_SFT, rt5668_alg_dac1_src);
1401
1402static const struct snd_kcontrol_new rt5668_alg_dac_l1_mux =
1403 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5668_alg_dac_l1_enum);
1404
1405static SOC_ENUM_SINGLE_DECL(
1406 rt5668_alg_dac_r1_enum, RT5668_A_DAC1_MUX,
1407 RT5668_A_DACR1_SFT, rt5668_alg_dac1_src);
1408
1409static const struct snd_kcontrol_new rt5668_alg_dac_r1_mux =
1410 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5668_alg_dac_r1_enum);
1411
1412
1413static const struct snd_kcontrol_new hpol_switch =
1414 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1415 RT5668_L_MUTE_SFT, 1, 1);
1416static const struct snd_kcontrol_new hpor_switch =
1417 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5668_HP_CTRL_1,
1418 RT5668_R_MUTE_SFT, 1, 1);
1419
1420static int rt5668_hp_event(struct snd_soc_dapm_widget *w,
1421 struct snd_kcontrol *kcontrol, int event)
1422{
1423 struct snd_soc_component *component =
1424 snd_soc_dapm_to_component(w->dapm);
1425
1426 switch (event) {
1427 case SND_SOC_DAPM_PRE_PMU:
1428 snd_soc_component_write(component,
1429 RT5668_HP_LOGIC_CTRL_2, 0x0012);
1430 snd_soc_component_write(component,
1431 RT5668_HP_CTRL_2, 0x6000);
1432 snd_soc_component_update_bits(component, RT5668_STO_NG2_CTRL_1,
1433 RT5668_NG2_EN_MASK, RT5668_NG2_EN);
1434 snd_soc_component_update_bits(component,
1435 RT5668_DEPOP_1, 0x60, 0x60);
1436 break;
1437
1438 case SND_SOC_DAPM_POST_PMD:
1439 snd_soc_component_update_bits(component,
1440 RT5668_DEPOP_1, 0x60, 0x0);
1441 snd_soc_component_write(component,
1442 RT5668_HP_CTRL_2, 0x0000);
1443 break;
1444
1445 default:
1446 return 0;
1447 }
1448
1449 return 0;
1450
1451}
1452
1453static int set_dmic_power(struct snd_soc_dapm_widget *w,
1454 struct snd_kcontrol *kcontrol, int event)
1455{
1456 switch (event) {
1457 case SND_SOC_DAPM_POST_PMU:
1458
1459 msleep(150);
1460 break;
1461
1462 default:
1463 return 0;
1464 }
1465
1466 return 0;
1467}
1468
1469static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
1470 struct snd_kcontrol *kcontrol, int event)
1471{
1472 struct snd_soc_component *component =
1473 snd_soc_dapm_to_component(w->dapm);
1474
1475 switch (event) {
1476 case SND_SOC_DAPM_PRE_PMU:
1477 switch (w->shift) {
1478 case RT5668_PWR_VREF1_BIT:
1479 snd_soc_component_update_bits(component,
1480 RT5668_PWR_ANLG_1, RT5668_PWR_FV1, 0);
1481 break;
1482
1483 case RT5668_PWR_VREF2_BIT:
1484 snd_soc_component_update_bits(component,
1485 RT5668_PWR_ANLG_1, RT5668_PWR_FV2, 0);
1486 break;
1487
1488 default:
1489 break;
1490 }
1491 break;
1492
1493 case SND_SOC_DAPM_POST_PMU:
1494 usleep_range(15000, 20000);
1495 switch (w->shift) {
1496 case RT5668_PWR_VREF1_BIT:
1497 snd_soc_component_update_bits(component,
1498 RT5668_PWR_ANLG_1, RT5668_PWR_FV1,
1499 RT5668_PWR_FV1);
1500 break;
1501
1502 case RT5668_PWR_VREF2_BIT:
1503 snd_soc_component_update_bits(component,
1504 RT5668_PWR_ANLG_1, RT5668_PWR_FV2,
1505 RT5668_PWR_FV2);
1506 break;
1507
1508 default:
1509 break;
1510 }
1511 break;
1512
1513 default:
1514 return 0;
1515 }
1516
1517 return 0;
1518}
1519
1520static const unsigned int rt5668_adcdat_pin_values[] = {
1521 1,
1522 3,
1523};
1524
1525static const char * const rt5668_adcdat_pin_select[] = {
1526 "ADCDAT1",
1527 "ADCDAT2",
1528};
1529
1530static SOC_VALUE_ENUM_SINGLE_DECL(rt5668_adcdat_pin_enum,
1531 RT5668_GPIO_CTRL_1, RT5668_GP4_PIN_SFT, RT5668_GP4_PIN_MASK,
1532 rt5668_adcdat_pin_select, rt5668_adcdat_pin_values);
1533
1534static const struct snd_kcontrol_new rt5668_adcdat_pin_ctrl =
1535 SOC_DAPM_ENUM("ADCDAT", rt5668_adcdat_pin_enum);
1536
1537static const struct snd_soc_dapm_widget rt5668_dapm_widgets[] = {
1538 SND_SOC_DAPM_SUPPLY("LDO2", RT5668_PWR_ANLG_3, RT5668_PWR_LDO2_BIT,
1539 0, NULL, 0),
1540 SND_SOC_DAPM_SUPPLY("PLL1", RT5668_PWR_ANLG_3, RT5668_PWR_PLL_BIT,
1541 0, NULL, 0),
1542 SND_SOC_DAPM_SUPPLY("PLL2B", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2B_BIT,
1543 0, NULL, 0),
1544 SND_SOC_DAPM_SUPPLY("PLL2F", RT5668_PWR_ANLG_3, RT5668_PWR_PLL2F_BIT,
1545 0, NULL, 0),
1546 SND_SOC_DAPM_SUPPLY("Vref1", RT5668_PWR_ANLG_1, RT5668_PWR_VREF1_BIT, 0,
1547 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1548 SND_SOC_DAPM_SUPPLY("Vref2", RT5668_PWR_ANLG_1, RT5668_PWR_VREF2_BIT, 0,
1549 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
1550
1551
1552 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1553 RT5668_DAC_STO1_ASRC_SFT, 0, NULL, 0),
1554 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5668_PLL_TRACK_1,
1555 RT5668_ADC_STO1_ASRC_SFT, 0, NULL, 0),
1556 SND_SOC_DAPM_SUPPLY_S("AD ASRC", 1, RT5668_PLL_TRACK_1,
1557 RT5668_AD_ASRC_SFT, 0, NULL, 0),
1558 SND_SOC_DAPM_SUPPLY_S("DA ASRC", 1, RT5668_PLL_TRACK_1,
1559 RT5668_DA_ASRC_SFT, 0, NULL, 0),
1560 SND_SOC_DAPM_SUPPLY_S("DMIC ASRC", 1, RT5668_PLL_TRACK_1,
1561 RT5668_DMIC_ASRC_SFT, 0, NULL, 0),
1562
1563
1564 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5668_PWR_ANLG_2, RT5668_PWR_MB1_BIT,
1565 0, NULL, 0),
1566 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5668_PWR_ANLG_2, RT5668_PWR_MB2_BIT,
1567 0, NULL, 0),
1568
1569
1570 SND_SOC_DAPM_INPUT("DMIC L1"),
1571 SND_SOC_DAPM_INPUT("DMIC R1"),
1572
1573 SND_SOC_DAPM_INPUT("IN1P"),
1574
1575 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1576 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1577 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5668_DMIC_CTRL_1,
1578 RT5668_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
1579
1580
1581 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
1582 0, 0, NULL, 0),
1583
1584 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5668_PWR_ANLG_3,
1585 RT5668_PWR_CBJ_BIT, 0, NULL, 0),
1586
1587
1588 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5668_rec1_l_mix,
1589 ARRAY_SIZE(rt5668_rec1_l_mix)),
1590 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5668_PWR_ANLG_2,
1591 RT5668_PWR_RM1_L_BIT, 0, NULL, 0),
1592
1593
1594 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
1595 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
1596
1597 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5668_PWR_DIG_1,
1598 RT5668_PWR_ADC_L1_BIT, 0, NULL, 0),
1599 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5668_PWR_DIG_1,
1600 RT5668_PWR_ADC_R1_BIT, 0, NULL, 0),
1601 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5668_CHOP_ADC,
1602 RT5668_CKGEN_ADC1_SFT, 0, NULL, 0),
1603
1604
1605 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1606 &rt5668_sto1_adc1l_mux),
1607 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1608 &rt5668_sto1_adc1r_mux),
1609 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1610 &rt5668_sto1_adc2l_mux),
1611 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1612 &rt5668_sto1_adc2r_mux),
1613 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
1614 &rt5668_sto1_adcl_mux),
1615 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
1616 &rt5668_sto1_adcr_mux),
1617 SND_SOC_DAPM_MUX("IF1_ADC Mux", SND_SOC_NOPM, 0, 0,
1618 &rt5668_if1_adc_slot_mux),
1619
1620
1621 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5668_PWR_DIG_2,
1622 RT5668_PWR_ADC_S1F_BIT, 0, set_filter_clk,
1623 SND_SOC_DAPM_PRE_PMU),
1624 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5668_STO1_ADC_DIG_VOL,
1625 RT5668_L_MUTE_SFT, 1, rt5668_sto1_adc_l_mix,
1626 ARRAY_SIZE(rt5668_sto1_adc_l_mix)),
1627 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5668_STO1_ADC_DIG_VOL,
1628 RT5668_R_MUTE_SFT, 1, rt5668_sto1_adc_r_mix,
1629 ARRAY_SIZE(rt5668_sto1_adc_r_mix)),
1630
1631
1632 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1633
1634
1635 SND_SOC_DAPM_SUPPLY("I2S1", RT5668_PWR_DIG_1, RT5668_PWR_I2S1_BIT,
1636 0, NULL, 0),
1637 SND_SOC_DAPM_SUPPLY("I2S2", RT5668_PWR_DIG_1, RT5668_PWR_I2S2_BIT,
1638 0, NULL, 0),
1639 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1640 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1641 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1642
1643
1644 SND_SOC_DAPM_MUX("IF1 01 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1645 &rt5668_if1_01_adc_swap_mux),
1646 SND_SOC_DAPM_MUX("IF1 23 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1647 &rt5668_if1_23_adc_swap_mux),
1648 SND_SOC_DAPM_MUX("IF1 45 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1649 &rt5668_if1_45_adc_swap_mux),
1650 SND_SOC_DAPM_MUX("IF1 67 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1651 &rt5668_if1_67_adc_swap_mux),
1652 SND_SOC_DAPM_MUX("IF2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
1653 &rt5668_if2_adc_swap_mux),
1654
1655 SND_SOC_DAPM_MUX("ADCDAT Mux", SND_SOC_NOPM, 0, 0,
1656 &rt5668_adcdat_pin_ctrl),
1657
1658
1659 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0,
1660 RT5668_I2S1_SDP, RT5668_SEL_ADCDAT_SFT, 1),
1661 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0,
1662 RT5668_I2S2_SDP, RT5668_I2S2_PIN_CFG_SFT, 1),
1663 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1664
1665
1666
1667 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1668 rt5668_dac_l_mix, ARRAY_SIZE(rt5668_dac_l_mix)),
1669 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1670 rt5668_dac_r_mix, ARRAY_SIZE(rt5668_dac_r_mix)),
1671
1672
1673 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
1674 &rt5668_alg_dac_l1_mux),
1675 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
1676 &rt5668_alg_dac_r1_mux),
1677
1678
1679 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5668_PWR_DIG_2,
1680 RT5668_PWR_DAC_S1F_BIT, 0, set_filter_clk,
1681 SND_SOC_DAPM_PRE_PMU),
1682 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
1683 rt5668_sto1_dac_l_mix, ARRAY_SIZE(rt5668_sto1_dac_l_mix)),
1684 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
1685 rt5668_sto1_dac_r_mix, ARRAY_SIZE(rt5668_sto1_dac_r_mix)),
1686
1687
1688 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5668_PWR_DIG_1,
1689 RT5668_PWR_DAC_L1_BIT, 0),
1690 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5668_PWR_DIG_1,
1691 RT5668_PWR_DAC_R1_BIT, 0),
1692 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 3, RT5668_CHOP_DAC,
1693 RT5668_CKGEN_DAC1_SFT, 0, NULL, 0),
1694
1695
1696 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5668_hp_event,
1697 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
1698
1699 SND_SOC_DAPM_SUPPLY("HP Amp L", RT5668_PWR_ANLG_1,
1700 RT5668_PWR_HA_L_BIT, 0, NULL, 0),
1701 SND_SOC_DAPM_SUPPLY("HP Amp R", RT5668_PWR_ANLG_1,
1702 RT5668_PWR_HA_R_BIT, 0, NULL, 0),
1703 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 1, RT5668_DEPOP_1,
1704 RT5668_PUMP_EN_SFT, 0, NULL, 0),
1705 SND_SOC_DAPM_SUPPLY_S("Capless", 2, RT5668_DEPOP_1,
1706 RT5668_CAPLESS_EN_SFT, 0, NULL, 0),
1707
1708 SND_SOC_DAPM_SWITCH("HPOL Playback", SND_SOC_NOPM, 0, 0,
1709 &hpol_switch),
1710 SND_SOC_DAPM_SWITCH("HPOR Playback", SND_SOC_NOPM, 0, 0,
1711 &hpor_switch),
1712
1713
1714 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5668_CLK_DET,
1715 RT5668_SYS_CLK_DET_SFT, 0, NULL, 0),
1716 SND_SOC_DAPM_SUPPLY("CLKDET PLL1", RT5668_CLK_DET,
1717 RT5668_PLL1_CLK_DET_SFT, 0, NULL, 0),
1718 SND_SOC_DAPM_SUPPLY("CLKDET PLL2", RT5668_CLK_DET,
1719 RT5668_PLL2_CLK_DET_SFT, 0, NULL, 0),
1720 SND_SOC_DAPM_SUPPLY("CLKDET", RT5668_CLK_DET,
1721 RT5668_POW_CLK_DET_SFT, 0, NULL, 0),
1722
1723
1724 SND_SOC_DAPM_OUTPUT("HPOL"),
1725 SND_SOC_DAPM_OUTPUT("HPOR"),
1726
1727};
1728
1729static const struct snd_soc_dapm_route rt5668_dapm_routes[] = {
1730
1731 {"ADC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1732 {"DAC Stereo1 Filter", NULL, "PLL1", is_sys_clk_from_pll1},
1733
1734
1735 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
1736 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
1737 {"ADC STO1 ASRC", NULL, "AD ASRC"},
1738 {"DAC STO1 ASRC", NULL, "DA ASRC"},
1739
1740
1741 {"MICBIAS1", NULL, "Vref1"},
1742 {"MICBIAS1", NULL, "Vref2"},
1743 {"MICBIAS2", NULL, "Vref1"},
1744 {"MICBIAS2", NULL, "Vref2"},
1745
1746 {"CLKDET SYS", NULL, "CLKDET"},
1747
1748 {"IN1P", NULL, "LDO2"},
1749
1750 {"BST1 CBJ", NULL, "IN1P"},
1751 {"BST1 CBJ", NULL, "CBJ Power"},
1752 {"CBJ Power", NULL, "Vref2"},
1753
1754 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
1755 {"RECMIX1L", NULL, "RECMIX1L Power"},
1756
1757 {"ADC1 L", NULL, "RECMIX1L"},
1758 {"ADC1 L", NULL, "ADC1 L Power"},
1759 {"ADC1 L", NULL, "ADC1 clock"},
1760
1761 {"DMIC L1", NULL, "DMIC CLK"},
1762 {"DMIC L1", NULL, "DMIC1 Power"},
1763 {"DMIC R1", NULL, "DMIC CLK"},
1764 {"DMIC R1", NULL, "DMIC1 Power"},
1765 {"DMIC CLK", NULL, "DMIC ASRC"},
1766
1767 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
1768 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
1769 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
1770 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
1771
1772 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
1773 {"Stereo1 ADC L1 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1774 {"Stereo1 ADC L2 Mux", "DMIC", "DMIC L1"},
1775 {"Stereo1 ADC L2 Mux", "DAC MIX", "Stereo1 DAC MIXL"},
1776
1777 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
1778 {"Stereo1 ADC R1 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1779 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1780 {"Stereo1 ADC R2 Mux", "DAC MIX", "Stereo1 DAC MIXR"},
1781
1782 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
1783 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
1784 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
1785
1786 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
1787 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1788 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
1789
1790 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
1791 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
1792
1793 {"IF1 01 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1794 {"IF1 01 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1795 {"IF1 01 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1796 {"IF1 01 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1797 {"IF1 23 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1798 {"IF1 23 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1799 {"IF1 23 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1800 {"IF1 23 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1801 {"IF1 45 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1802 {"IF1 45 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1803 {"IF1 45 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1804 {"IF1 45 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1805 {"IF1 67 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1806 {"IF1 67 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1807 {"IF1 67 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1808 {"IF1 67 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1809
1810 {"IF1_ADC Mux", "Slot 0", "IF1 01 ADC Swap Mux"},
1811 {"IF1_ADC Mux", "Slot 2", "IF1 23 ADC Swap Mux"},
1812 {"IF1_ADC Mux", "Slot 4", "IF1 45 ADC Swap Mux"},
1813 {"IF1_ADC Mux", "Slot 6", "IF1 67 ADC Swap Mux"},
1814 {"IF1_ADC Mux", NULL, "I2S1"},
1815 {"ADCDAT Mux", "ADCDAT1", "IF1_ADC Mux"},
1816 {"AIF1TX", NULL, "ADCDAT Mux"},
1817 {"IF2 ADC Swap Mux", "L/R", "Stereo1 ADC MIX"},
1818 {"IF2 ADC Swap Mux", "R/L", "Stereo1 ADC MIX"},
1819 {"IF2 ADC Swap Mux", "L/L", "Stereo1 ADC MIX"},
1820 {"IF2 ADC Swap Mux", "R/R", "Stereo1 ADC MIX"},
1821 {"ADCDAT Mux", "ADCDAT2", "IF2 ADC Swap Mux"},
1822 {"AIF2TX", NULL, "ADCDAT Mux"},
1823
1824 {"IF1 DAC1 L", NULL, "AIF1RX"},
1825 {"IF1 DAC1 L", NULL, "I2S1"},
1826 {"IF1 DAC1 L", NULL, "DAC Stereo1 Filter"},
1827 {"IF1 DAC1 R", NULL, "AIF1RX"},
1828 {"IF1 DAC1 R", NULL, "I2S1"},
1829 {"IF1 DAC1 R", NULL, "DAC Stereo1 Filter"},
1830
1831 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
1832 {"DAC1 MIXL", "DAC1 Switch", "IF1 DAC1 L"},
1833 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
1834 {"DAC1 MIXR", "DAC1 Switch", "IF1 DAC1 R"},
1835
1836 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
1837 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
1838
1839 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
1840 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
1841
1842 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
1843 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
1844 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
1845 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
1846
1847 {"DAC L1", NULL, "DAC L1 Source"},
1848 {"DAC R1", NULL, "DAC R1 Source"},
1849
1850 {"DAC L1", NULL, "DAC 1 Clock"},
1851 {"DAC R1", NULL, "DAC 1 Clock"},
1852
1853 {"HP Amp", NULL, "DAC L1"},
1854 {"HP Amp", NULL, "DAC R1"},
1855 {"HP Amp", NULL, "HP Amp L"},
1856 {"HP Amp", NULL, "HP Amp R"},
1857 {"HP Amp", NULL, "Capless"},
1858 {"HP Amp", NULL, "Charge Pump"},
1859 {"HP Amp", NULL, "CLKDET SYS"},
1860 {"HP Amp", NULL, "CBJ Power"},
1861 {"HP Amp", NULL, "Vref2"},
1862 {"HPOL Playback", "Switch", "HP Amp"},
1863 {"HPOR Playback", "Switch", "HP Amp"},
1864 {"HPOL", NULL, "HPOL Playback"},
1865 {"HPOR", NULL, "HPOR Playback"},
1866};
1867
1868static int rt5668_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1869 unsigned int rx_mask, int slots, int slot_width)
1870{
1871 struct snd_soc_component *component = dai->component;
1872 unsigned int val = 0;
1873
1874 switch (slots) {
1875 case 4:
1876 val |= RT5668_TDM_TX_CH_4;
1877 val |= RT5668_TDM_RX_CH_4;
1878 break;
1879 case 6:
1880 val |= RT5668_TDM_TX_CH_6;
1881 val |= RT5668_TDM_RX_CH_6;
1882 break;
1883 case 8:
1884 val |= RT5668_TDM_TX_CH_8;
1885 val |= RT5668_TDM_RX_CH_8;
1886 break;
1887 case 2:
1888 break;
1889 default:
1890 return -EINVAL;
1891 }
1892
1893 snd_soc_component_update_bits(component, RT5668_TDM_CTRL,
1894 RT5668_TDM_TX_CH_MASK | RT5668_TDM_RX_CH_MASK, val);
1895
1896 switch (slot_width) {
1897 case 16:
1898 val = RT5668_TDM_CL_16;
1899 break;
1900 case 20:
1901 val = RT5668_TDM_CL_20;
1902 break;
1903 case 24:
1904 val = RT5668_TDM_CL_24;
1905 break;
1906 case 32:
1907 val = RT5668_TDM_CL_32;
1908 break;
1909 default:
1910 return -EINVAL;
1911 }
1912
1913 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
1914 RT5668_TDM_CL_MASK, val);
1915
1916 return 0;
1917}
1918
1919
1920static int rt5668_hw_params(struct snd_pcm_substream *substream,
1921 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1922{
1923 struct snd_soc_component *component = dai->component;
1924 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
1925 unsigned int len_1 = 0, len_2 = 0;
1926 int pre_div, frame_size;
1927
1928 rt5668->lrck[dai->id] = params_rate(params);
1929 pre_div = rl6231_get_clk_info(rt5668->sysclk, rt5668->lrck[dai->id]);
1930
1931 frame_size = snd_soc_params_to_frame_size(params);
1932 if (frame_size < 0) {
1933 dev_err(component->dev, "Unsupported frame size: %d\n",
1934 frame_size);
1935 return -EINVAL;
1936 }
1937
1938 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1939 rt5668->lrck[dai->id], pre_div, dai->id);
1940
1941 switch (params_width(params)) {
1942 case 16:
1943 break;
1944 case 20:
1945 len_1 |= RT5668_I2S1_DL_20;
1946 len_2 |= RT5668_I2S2_DL_20;
1947 break;
1948 case 24:
1949 len_1 |= RT5668_I2S1_DL_24;
1950 len_2 |= RT5668_I2S2_DL_24;
1951 break;
1952 case 32:
1953 len_1 |= RT5668_I2S1_DL_32;
1954 len_2 |= RT5668_I2S2_DL_24;
1955 break;
1956 case 8:
1957 len_1 |= RT5668_I2S2_DL_8;
1958 len_2 |= RT5668_I2S2_DL_8;
1959 break;
1960 default:
1961 return -EINVAL;
1962 }
1963
1964 switch (dai->id) {
1965 case RT5668_AIF1:
1966 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
1967 RT5668_I2S1_DL_MASK, len_1);
1968 if (rt5668->master[RT5668_AIF1]) {
1969 snd_soc_component_update_bits(component,
1970 RT5668_ADDA_CLK_1, RT5668_I2S_M_DIV_MASK,
1971 pre_div << RT5668_I2S_M_DIV_SFT);
1972 }
1973 if (params_channels(params) == 1)
1974 snd_soc_component_update_bits(component,
1975 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1976 RT5668_I2S1_MONO_EN);
1977 else
1978 snd_soc_component_update_bits(component,
1979 RT5668_I2S1_SDP, RT5668_I2S1_MONO_MASK,
1980 RT5668_I2S1_MONO_DIS);
1981 break;
1982 case RT5668_AIF2:
1983 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
1984 RT5668_I2S2_DL_MASK, len_2);
1985 if (rt5668->master[RT5668_AIF2]) {
1986 snd_soc_component_update_bits(component,
1987 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_M_PD_MASK,
1988 pre_div << RT5668_I2S2_M_PD_SFT);
1989 }
1990 if (params_channels(params) == 1)
1991 snd_soc_component_update_bits(component,
1992 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1993 RT5668_I2S2_MONO_EN);
1994 else
1995 snd_soc_component_update_bits(component,
1996 RT5668_I2S2_SDP, RT5668_I2S2_MONO_MASK,
1997 RT5668_I2S2_MONO_DIS);
1998 break;
1999 default:
2000 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2001 return -EINVAL;
2002 }
2003
2004 return 0;
2005}
2006
2007static int rt5668_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2008{
2009 struct snd_soc_component *component = dai->component;
2010 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2011 unsigned int reg_val = 0, tdm_ctrl = 0;
2012
2013 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2014 case SND_SOC_DAIFMT_CBM_CFM:
2015 rt5668->master[dai->id] = 1;
2016 break;
2017 case SND_SOC_DAIFMT_CBS_CFS:
2018 rt5668->master[dai->id] = 0;
2019 break;
2020 default:
2021 return -EINVAL;
2022 }
2023
2024 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2025 case SND_SOC_DAIFMT_NB_NF:
2026 break;
2027 case SND_SOC_DAIFMT_IB_NF:
2028 reg_val |= RT5668_I2S_BP_INV;
2029 tdm_ctrl |= RT5668_TDM_S_BP_INV;
2030 break;
2031 case SND_SOC_DAIFMT_NB_IF:
2032 if (dai->id == RT5668_AIF1)
2033 tdm_ctrl |= RT5668_TDM_S_LP_INV | RT5668_TDM_M_BP_INV;
2034 else
2035 return -EINVAL;
2036 break;
2037 case SND_SOC_DAIFMT_IB_IF:
2038 if (dai->id == RT5668_AIF1)
2039 tdm_ctrl |= RT5668_TDM_S_BP_INV | RT5668_TDM_S_LP_INV |
2040 RT5668_TDM_M_BP_INV | RT5668_TDM_M_LP_INV;
2041 else
2042 return -EINVAL;
2043 break;
2044 default:
2045 return -EINVAL;
2046 }
2047
2048 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2049 case SND_SOC_DAIFMT_I2S:
2050 break;
2051 case SND_SOC_DAIFMT_LEFT_J:
2052 reg_val |= RT5668_I2S_DF_LEFT;
2053 tdm_ctrl |= RT5668_TDM_DF_LEFT;
2054 break;
2055 case SND_SOC_DAIFMT_DSP_A:
2056 reg_val |= RT5668_I2S_DF_PCM_A;
2057 tdm_ctrl |= RT5668_TDM_DF_PCM_A;
2058 break;
2059 case SND_SOC_DAIFMT_DSP_B:
2060 reg_val |= RT5668_I2S_DF_PCM_B;
2061 tdm_ctrl |= RT5668_TDM_DF_PCM_B;
2062 break;
2063 default:
2064 return -EINVAL;
2065 }
2066
2067 switch (dai->id) {
2068 case RT5668_AIF1:
2069 snd_soc_component_update_bits(component, RT5668_I2S1_SDP,
2070 RT5668_I2S_DF_MASK, reg_val);
2071 snd_soc_component_update_bits(component, RT5668_TDM_TCON_CTRL,
2072 RT5668_TDM_MS_MASK | RT5668_TDM_S_BP_MASK |
2073 RT5668_TDM_DF_MASK | RT5668_TDM_M_BP_MASK |
2074 RT5668_TDM_M_LP_MASK | RT5668_TDM_S_LP_MASK,
2075 tdm_ctrl | rt5668->master[dai->id]);
2076 break;
2077 case RT5668_AIF2:
2078 if (rt5668->master[dai->id] == 0)
2079 reg_val |= RT5668_I2S2_MS_S;
2080 snd_soc_component_update_bits(component, RT5668_I2S2_SDP,
2081 RT5668_I2S2_MS_MASK | RT5668_I2S_BP_MASK |
2082 RT5668_I2S_DF_MASK, reg_val);
2083 break;
2084 default:
2085 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2086 return -EINVAL;
2087 }
2088 return 0;
2089}
2090
2091static int rt5668_set_component_sysclk(struct snd_soc_component *component,
2092 int clk_id, int source, unsigned int freq, int dir)
2093{
2094 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2095 unsigned int reg_val = 0, src = 0;
2096
2097 if (freq == rt5668->sysclk && clk_id == rt5668->sysclk_src)
2098 return 0;
2099
2100 switch (clk_id) {
2101 case RT5668_SCLK_S_MCLK:
2102 reg_val |= RT5668_SCLK_SRC_MCLK;
2103 src = RT5668_CLK_SRC_MCLK;
2104 break;
2105 case RT5668_SCLK_S_PLL1:
2106 reg_val |= RT5668_SCLK_SRC_PLL1;
2107 src = RT5668_CLK_SRC_PLL1;
2108 break;
2109 case RT5668_SCLK_S_PLL2:
2110 reg_val |= RT5668_SCLK_SRC_PLL2;
2111 src = RT5668_CLK_SRC_PLL2;
2112 break;
2113 case RT5668_SCLK_S_RCCLK:
2114 reg_val |= RT5668_SCLK_SRC_RCCLK;
2115 src = RT5668_CLK_SRC_RCCLK;
2116 break;
2117 default:
2118 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2119 return -EINVAL;
2120 }
2121 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2122 RT5668_SCLK_SRC_MASK, reg_val);
2123
2124 if (rt5668->master[RT5668_AIF2]) {
2125 snd_soc_component_update_bits(component,
2126 RT5668_I2S_M_CLK_CTRL_1, RT5668_I2S2_SRC_MASK,
2127 src << RT5668_I2S2_SRC_SFT);
2128 }
2129
2130 rt5668->sysclk = freq;
2131 rt5668->sysclk_src = clk_id;
2132
2133 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
2134 freq, clk_id);
2135
2136 return 0;
2137}
2138
2139static int rt5668_set_component_pll(struct snd_soc_component *component,
2140 int pll_id, int source, unsigned int freq_in,
2141 unsigned int freq_out)
2142{
2143 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2144 struct rl6231_pll_code pll_code;
2145 int ret;
2146
2147 if (source == rt5668->pll_src && freq_in == rt5668->pll_in &&
2148 freq_out == rt5668->pll_out)
2149 return 0;
2150
2151 if (!freq_in || !freq_out) {
2152 dev_dbg(component->dev, "PLL disabled\n");
2153
2154 rt5668->pll_in = 0;
2155 rt5668->pll_out = 0;
2156 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2157 RT5668_SCLK_SRC_MASK, RT5668_SCLK_SRC_MCLK);
2158 return 0;
2159 }
2160
2161 switch (source) {
2162 case RT5668_PLL1_S_MCLK:
2163 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2164 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_MCLK);
2165 break;
2166 case RT5668_PLL1_S_BCLK1:
2167 snd_soc_component_update_bits(component, RT5668_GLB_CLK,
2168 RT5668_PLL1_SRC_MASK, RT5668_PLL1_SRC_BCLK1);
2169 break;
2170 default:
2171 dev_err(component->dev, "Unknown PLL Source %d\n", source);
2172 return -EINVAL;
2173 }
2174
2175 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2176 if (ret < 0) {
2177 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2178 return ret;
2179 }
2180
2181 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2182 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2183 pll_code.n_code, pll_code.k_code);
2184
2185 snd_soc_component_write(component, RT5668_PLL_CTRL_1,
2186 pll_code.n_code << RT5668_PLL_N_SFT | pll_code.k_code);
2187 snd_soc_component_write(component, RT5668_PLL_CTRL_2,
2188 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5668_PLL_M_SFT |
2189 pll_code.m_bp << RT5668_PLL_M_BP_SFT);
2190
2191 rt5668->pll_in = freq_in;
2192 rt5668->pll_out = freq_out;
2193 rt5668->pll_src = source;
2194
2195 return 0;
2196}
2197
2198static int rt5668_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
2199{
2200 struct snd_soc_component *component = dai->component;
2201 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2202
2203 rt5668->bclk[dai->id] = ratio;
2204
2205 switch (ratio) {
2206 case 64:
2207 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2208 RT5668_I2S2_BCLK_MS2_MASK,
2209 RT5668_I2S2_BCLK_MS2_64);
2210 break;
2211 case 32:
2212 snd_soc_component_update_bits(component, RT5668_ADDA_CLK_2,
2213 RT5668_I2S2_BCLK_MS2_MASK,
2214 RT5668_I2S2_BCLK_MS2_32);
2215 break;
2216 default:
2217 dev_err(dai->dev, "Invalid bclk ratio %d\n", ratio);
2218 return -EINVAL;
2219 }
2220
2221 return 0;
2222}
2223
2224static int rt5668_set_bias_level(struct snd_soc_component *component,
2225 enum snd_soc_bias_level level)
2226{
2227 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2228
2229 switch (level) {
2230 case SND_SOC_BIAS_PREPARE:
2231 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2232 RT5668_PWR_MB | RT5668_PWR_BG,
2233 RT5668_PWR_MB | RT5668_PWR_BG);
2234 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2235 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO,
2236 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO);
2237 break;
2238
2239 case SND_SOC_BIAS_STANDBY:
2240 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2241 RT5668_PWR_MB, RT5668_PWR_MB);
2242 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2243 RT5668_DIG_GATE_CTRL, RT5668_DIG_GATE_CTRL);
2244 break;
2245 case SND_SOC_BIAS_OFF:
2246 regmap_update_bits(rt5668->regmap, RT5668_PWR_DIG_1,
2247 RT5668_DIG_GATE_CTRL | RT5668_PWR_LDO, 0);
2248 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2249 RT5668_PWR_MB | RT5668_PWR_BG, 0);
2250 break;
2251
2252 default:
2253 break;
2254 }
2255
2256 return 0;
2257}
2258
2259static int rt5668_probe(struct snd_soc_component *component)
2260{
2261 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2262
2263 rt5668->component = component;
2264
2265 return 0;
2266}
2267
2268static void rt5668_remove(struct snd_soc_component *component)
2269{
2270 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2271
2272 rt5668_reset(rt5668->regmap);
2273}
2274
2275#ifdef CONFIG_PM
2276static int rt5668_suspend(struct snd_soc_component *component)
2277{
2278 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2279
2280 regcache_cache_only(rt5668->regmap, true);
2281 regcache_mark_dirty(rt5668->regmap);
2282 return 0;
2283}
2284
2285static int rt5668_resume(struct snd_soc_component *component)
2286{
2287 struct rt5668_priv *rt5668 = snd_soc_component_get_drvdata(component);
2288
2289 regcache_cache_only(rt5668->regmap, false);
2290 regcache_sync(rt5668->regmap);
2291
2292 return 0;
2293}
2294#else
2295#define rt5668_suspend NULL
2296#define rt5668_resume NULL
2297#endif
2298
2299#define RT5668_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2300#define RT5668_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2301 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2302
2303static const struct snd_soc_dai_ops rt5668_aif1_dai_ops = {
2304 .hw_params = rt5668_hw_params,
2305 .set_fmt = rt5668_set_dai_fmt,
2306 .set_tdm_slot = rt5668_set_tdm_slot,
2307};
2308
2309static const struct snd_soc_dai_ops rt5668_aif2_dai_ops = {
2310 .hw_params = rt5668_hw_params,
2311 .set_fmt = rt5668_set_dai_fmt,
2312 .set_bclk_ratio = rt5668_set_bclk_ratio,
2313};
2314
2315static struct snd_soc_dai_driver rt5668_dai[] = {
2316 {
2317 .name = "rt5668-aif1",
2318 .id = RT5668_AIF1,
2319 .playback = {
2320 .stream_name = "AIF1 Playback",
2321 .channels_min = 1,
2322 .channels_max = 2,
2323 .rates = RT5668_STEREO_RATES,
2324 .formats = RT5668_FORMATS,
2325 },
2326 .capture = {
2327 .stream_name = "AIF1 Capture",
2328 .channels_min = 1,
2329 .channels_max = 2,
2330 .rates = RT5668_STEREO_RATES,
2331 .formats = RT5668_FORMATS,
2332 },
2333 .ops = &rt5668_aif1_dai_ops,
2334 },
2335 {
2336 .name = "rt5668-aif2",
2337 .id = RT5668_AIF2,
2338 .capture = {
2339 .stream_name = "AIF2 Capture",
2340 .channels_min = 1,
2341 .channels_max = 2,
2342 .rates = RT5668_STEREO_RATES,
2343 .formats = RT5668_FORMATS,
2344 },
2345 .ops = &rt5668_aif2_dai_ops,
2346 },
2347};
2348
2349static const struct snd_soc_component_driver soc_component_dev_rt5668 = {
2350 .probe = rt5668_probe,
2351 .remove = rt5668_remove,
2352 .suspend = rt5668_suspend,
2353 .resume = rt5668_resume,
2354 .set_bias_level = rt5668_set_bias_level,
2355 .controls = rt5668_snd_controls,
2356 .num_controls = ARRAY_SIZE(rt5668_snd_controls),
2357 .dapm_widgets = rt5668_dapm_widgets,
2358 .num_dapm_widgets = ARRAY_SIZE(rt5668_dapm_widgets),
2359 .dapm_routes = rt5668_dapm_routes,
2360 .num_dapm_routes = ARRAY_SIZE(rt5668_dapm_routes),
2361 .set_sysclk = rt5668_set_component_sysclk,
2362 .set_pll = rt5668_set_component_pll,
2363 .set_jack = rt5668_set_jack_detect,
2364 .use_pmdown_time = 1,
2365 .endianness = 1,
2366 .non_legacy_dai_naming = 1,
2367};
2368
2369static const struct regmap_config rt5668_regmap = {
2370 .reg_bits = 16,
2371 .val_bits = 16,
2372 .max_register = RT5668_I2C_MODE,
2373 .volatile_reg = rt5668_volatile_register,
2374 .readable_reg = rt5668_readable_register,
2375 .cache_type = REGCACHE_RBTREE,
2376 .reg_defaults = rt5668_reg,
2377 .num_reg_defaults = ARRAY_SIZE(rt5668_reg),
2378 .use_single_rw = true,
2379};
2380
2381static const struct i2c_device_id rt5668_i2c_id[] = {
2382 {"rt5668b", 0},
2383 {}
2384};
2385MODULE_DEVICE_TABLE(i2c, rt5668_i2c_id);
2386
2387static int rt5668_parse_dt(struct rt5668_priv *rt5668, struct device *dev)
2388{
2389
2390 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
2391 &rt5668->pdata.dmic1_data_pin);
2392 of_property_read_u32(dev->of_node, "realtek,dmic1-clk-pin",
2393 &rt5668->pdata.dmic1_clk_pin);
2394 of_property_read_u32(dev->of_node, "realtek,jd-src",
2395 &rt5668->pdata.jd_src);
2396
2397 rt5668->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
2398 "realtek,ldo1-en-gpios", 0);
2399
2400 return 0;
2401}
2402
2403static void rt5668_calibrate(struct rt5668_priv *rt5668)
2404{
2405 int value, count;
2406
2407 mutex_lock(&rt5668->calibrate_mutex);
2408
2409 rt5668_reset(rt5668->regmap);
2410 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xa2bf);
2411 usleep_range(15000, 20000);
2412 regmap_write(rt5668->regmap, RT5668_PWR_ANLG_1, 0xf2bf);
2413 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2414 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8001);
2415 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2416 regmap_write(rt5668->regmap, RT5668_STO1_DAC_MIXER, 0x2080);
2417 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x4040);
2418 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0069);
2419 regmap_write(rt5668->regmap, RT5668_CHOP_DAC, 0x3000);
2420 regmap_write(rt5668->regmap, RT5668_HP_CTRL_2, 0x6000);
2421 regmap_write(rt5668->regmap, RT5668_HP_CHARGE_PUMP_1, 0x0f26);
2422 regmap_write(rt5668->regmap, RT5668_CALIB_ADC_CTRL, 0x7f05);
2423 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0x686c);
2424 regmap_write(rt5668->regmap, RT5668_CAL_REC, 0x0d0d);
2425 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_9, 0x000f);
2426 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x8d01);
2427 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_2, 0x0321);
2428 regmap_write(rt5668->regmap, RT5668_HP_LOGIC_CTRL_2, 0x0004);
2429 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0x7c00);
2430 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_3, 0x06a1);
2431 regmap_write(rt5668->regmap, RT5668_A_DAC1_MUX, 0x0311);
2432 regmap_write(rt5668->regmap, RT5668_RESET_HPF_CTRL, 0x0000);
2433 regmap_write(rt5668->regmap, RT5668_ADC_STO1_HP_CTRL_1, 0x3320);
2434
2435 regmap_write(rt5668->regmap, RT5668_HP_CALIB_CTRL_1, 0xfc00);
2436
2437 for (count = 0; count < 60; count++) {
2438 regmap_read(rt5668->regmap, RT5668_HP_CALIB_STA_1, &value);
2439 if (!(value & 0x8000))
2440 break;
2441
2442 usleep_range(10000, 10005);
2443 }
2444
2445 if (count >= 60)
2446 pr_err("HP Calibration Failure\n");
2447
2448
2449 regmap_write(rt5668->regmap, RT5668_STO1_ADC_MIXER, 0xc0c4);
2450 regmap_write(rt5668->regmap, RT5668_PWR_DIG_1, 0x0000);
2451
2452 mutex_unlock(&rt5668->calibrate_mutex);
2453
2454}
2455
2456static int rt5668_i2c_probe(struct i2c_client *i2c,
2457 const struct i2c_device_id *id)
2458{
2459 struct rt5668_platform_data *pdata = dev_get_platdata(&i2c->dev);
2460 struct rt5668_priv *rt5668;
2461 int i, ret;
2462 unsigned int val;
2463
2464 rt5668 = devm_kzalloc(&i2c->dev, sizeof(struct rt5668_priv),
2465 GFP_KERNEL);
2466
2467 if (rt5668 == NULL)
2468 return -ENOMEM;
2469
2470 i2c_set_clientdata(i2c, rt5668);
2471
2472 if (pdata)
2473 rt5668->pdata = *pdata;
2474 else
2475 rt5668_parse_dt(rt5668, &i2c->dev);
2476
2477 rt5668->regmap = devm_regmap_init_i2c(i2c, &rt5668_regmap);
2478 if (IS_ERR(rt5668->regmap)) {
2479 ret = PTR_ERR(rt5668->regmap);
2480 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2481 ret);
2482 return ret;
2483 }
2484
2485 for (i = 0; i < ARRAY_SIZE(rt5668->supplies); i++)
2486 rt5668->supplies[i].supply = rt5668_supply_names[i];
2487
2488 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5668->supplies),
2489 rt5668->supplies);
2490 if (ret != 0) {
2491 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2492 return ret;
2493 }
2494
2495 ret = regulator_bulk_enable(ARRAY_SIZE(rt5668->supplies),
2496 rt5668->supplies);
2497 if (ret != 0) {
2498 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2499 return ret;
2500 }
2501
2502 if (gpio_is_valid(rt5668->pdata.ldo1_en)) {
2503 if (devm_gpio_request_one(&i2c->dev, rt5668->pdata.ldo1_en,
2504 GPIOF_OUT_INIT_HIGH, "rt5668"))
2505 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
2506 }
2507
2508
2509 usleep_range(300000, 350000);
2510
2511 regmap_write(rt5668->regmap, RT5668_I2C_MODE, 0x1);
2512 usleep_range(10000, 15000);
2513
2514 regmap_read(rt5668->regmap, RT5668_DEVICE_ID, &val);
2515 if (val != DEVICE_ID) {
2516 pr_err("Device with ID register %x is not rt5668\n", val);
2517 return -ENODEV;
2518 }
2519
2520 rt5668_reset(rt5668->regmap);
2521
2522 rt5668_calibrate(rt5668);
2523
2524 regmap_write(rt5668->regmap, RT5668_DEPOP_1, 0x0000);
2525
2526
2527 if (rt5668->pdata.dmic1_data_pin != RT5668_DMIC1_NULL) {
2528 switch (rt5668->pdata.dmic1_data_pin) {
2529 case RT5668_DMIC1_DATA_GPIO2:
2530 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2531 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO2);
2532 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2533 RT5668_GP2_PIN_MASK, RT5668_GP2_PIN_DMIC_SDA);
2534 break;
2535
2536 case RT5668_DMIC1_DATA_GPIO5:
2537 regmap_update_bits(rt5668->regmap, RT5668_DMIC_CTRL_1,
2538 RT5668_DMIC_1_DP_MASK, RT5668_DMIC_1_DP_GPIO5);
2539 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2540 RT5668_GP5_PIN_MASK, RT5668_GP5_PIN_DMIC_SDA);
2541 break;
2542
2543 default:
2544 dev_dbg(&i2c->dev, "invalid DMIC_DAT pin\n");
2545 break;
2546 }
2547
2548 switch (rt5668->pdata.dmic1_clk_pin) {
2549 case RT5668_DMIC1_CLK_GPIO1:
2550 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2551 RT5668_GP1_PIN_MASK, RT5668_GP1_PIN_DMIC_CLK);
2552 break;
2553
2554 case RT5668_DMIC1_CLK_GPIO3:
2555 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2556 RT5668_GP3_PIN_MASK, RT5668_GP3_PIN_DMIC_CLK);
2557 break;
2558
2559 default:
2560 dev_dbg(&i2c->dev, "invalid DMIC_CLK pin\n");
2561 break;
2562 }
2563 }
2564
2565 regmap_update_bits(rt5668->regmap, RT5668_PWR_ANLG_1,
2566 RT5668_LDO1_DVO_MASK | RT5668_HP_DRIVER_MASK,
2567 RT5668_LDO1_DVO_14 | RT5668_HP_DRIVER_5X);
2568 regmap_write(rt5668->regmap, RT5668_MICBIAS_2, 0x0380);
2569 regmap_update_bits(rt5668->regmap, RT5668_GPIO_CTRL_1,
2570 RT5668_GP4_PIN_MASK | RT5668_GP5_PIN_MASK,
2571 RT5668_GP4_PIN_ADCDAT1 | RT5668_GP5_PIN_DACDAT1);
2572 regmap_write(rt5668->regmap, RT5668_TEST_MODE_CTRL_1, 0x0000);
2573
2574 INIT_DELAYED_WORK(&rt5668->jack_detect_work,
2575 rt5668_jack_detect_handler);
2576 INIT_DELAYED_WORK(&rt5668->jd_check_work,
2577 rt5668_jd_check_handler);
2578
2579 mutex_init(&rt5668->calibrate_mutex);
2580
2581 if (i2c->irq) {
2582 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2583 rt5668_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2584 | IRQF_ONESHOT, "rt5668", rt5668);
2585 if (ret)
2586 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2587
2588 }
2589
2590 return snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5668,
2591 rt5668_dai, ARRAY_SIZE(rt5668_dai));
2592}
2593
2594static int rt5668_i2c_remove(struct i2c_client *i2c)
2595{
2596 snd_soc_unregister_component(&i2c->dev);
2597
2598 return 0;
2599}
2600
2601static void rt5668_i2c_shutdown(struct i2c_client *client)
2602{
2603 struct rt5668_priv *rt5668 = i2c_get_clientdata(client);
2604
2605 rt5668_reset(rt5668->regmap);
2606}
2607
2608#ifdef CONFIG_OF
2609static const struct of_device_id rt5668_of_match[] = {
2610 {.compatible = "realtek,rt5668b"},
2611 {},
2612};
2613MODULE_DEVICE_TABLE(of, rt5668_of_match);
2614#endif
2615
2616#ifdef CONFIG_ACPI
2617static const struct acpi_device_id rt5668_acpi_match[] = {
2618 {"10EC5668", 0,},
2619 {},
2620};
2621MODULE_DEVICE_TABLE(acpi, rt5668_acpi_match);
2622#endif
2623
2624static struct i2c_driver rt5668_i2c_driver = {
2625 .driver = {
2626 .name = "rt5668b",
2627 .of_match_table = of_match_ptr(rt5668_of_match),
2628 .acpi_match_table = ACPI_PTR(rt5668_acpi_match),
2629 },
2630 .probe = rt5668_i2c_probe,
2631 .remove = rt5668_i2c_remove,
2632 .shutdown = rt5668_i2c_shutdown,
2633 .id_table = rt5668_i2c_id,
2634};
2635module_i2c_driver(rt5668_i2c_driver);
2636
2637MODULE_DESCRIPTION("ASoC RT5668B driver");
2638MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2639MODULE_LICENSE("GPL v2");
2640
