LXR linux/arch/arm/mach-prima2/rstc.c

   1/*
   2 * reset controller for CSR SiRFprimaII
   3 *
   4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5 *
   6 * Licensed under GPLv2 or later.
   7 */
   8
   9#include <linux/kernel.h>
  10#include <linux/mutex.h>
  11#include <linux/io.h>
  12#include <linux/delay.h>
  13#include <linux/device.h>
  14#include <linux/of.h>
  15#include <linux/of_address.h>
  16#include <linux/platform_device.h>
  17#include <linux/reboot.h>
  18#include <linux/reset-controller.h>
  19
  20#include <asm/system_misc.h>
  21
  22#define SIRFSOC_RSTBIT_NUM      64
  23
  24static void __iomem *sirfsoc_rstc_base;
  25static DEFINE_MUTEX(rstc_lock);
  26
  27static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
  28                                        unsigned long sw_reset_idx)
  29{
  30        u32 reset_bit = sw_reset_idx;
  31
  32        if (reset_bit >= SIRFSOC_RSTBIT_NUM)
  33                return -EINVAL;
  34
  35        mutex_lock(&rstc_lock);
  36
  37        /*
  38         * Writing 1 to this bit resets corresponding block.
  39         * Writing 0 to this bit de-asserts reset signal of the
  40         * corresponding block. datasheet doesn't require explicit
  41         * delay between the set and clear of reset bit. it could
  42         * be shorter if tests pass.
  43         */
  44        writel(readl(sirfsoc_rstc_base +
  45                        (reset_bit / 32) * 4) | (1 << reset_bit),
  46                sirfsoc_rstc_base + (reset_bit / 32) * 4);
  47        msleep(20);
  48        writel(readl(sirfsoc_rstc_base +
  49                        (reset_bit / 32) * 4) & ~(1 << reset_bit),
  50                sirfsoc_rstc_base + (reset_bit / 32) * 4);
  51
  52        mutex_unlock(&rstc_lock);
  53
  54        return 0;
  55}
  56
  57static struct reset_control_ops sirfsoc_rstc_ops = {
  58        .reset = sirfsoc_reset_module,
  59};
  60
  61static struct reset_controller_dev sirfsoc_reset_controller = {
  62        .ops = &sirfsoc_rstc_ops,
  63        .nr_resets = SIRFSOC_RSTBIT_NUM,
  64};
  65
  66#define SIRFSOC_SYS_RST_BIT  BIT(31)
  67
  68static void sirfsoc_restart(enum reboot_mode mode, const char *cmd)
  69{
  70        writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
  71}
  72
  73static int sirfsoc_rstc_probe(struct platform_device *pdev)
  74{
  75        struct device_node *np = pdev->dev.of_node;
  76        sirfsoc_rstc_base = of_iomap(np, 0);
  77        if (!sirfsoc_rstc_base) {
  78                dev_err(&pdev->dev, "unable to map rstc cpu registers\n");
  79                return -ENOMEM;
  80        }
  81
  82        sirfsoc_reset_controller.of_node = np;
  83        arm_pm_restart = sirfsoc_restart;
  84
  85        if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
  86                reset_controller_register(&sirfsoc_reset_controller);
  87
  88        return 0;
  89}
  90
  91static const struct of_device_id rstc_ids[]  = {
  92        { .compatible = "sirf,prima2-rstc" },
  93        {},
  94};
  95
  96static struct platform_driver sirfsoc_rstc_driver = {
  97        .probe          = sirfsoc_rstc_probe,
  98        .driver         = {
  99                .name   = "sirfsoc_rstc",
 100                .of_match_table = rstc_ids,
 101        },
 102};
 103
 104static int __init sirfsoc_rstc_init(void)
 105{
 106        return platform_driver_register(&sirfsoc_rstc_driver);
 107}
 108subsys_initcall(sirfsoc_rstc_init);
 109