LXR linux/arch/mips/loongson64/lemote-2f/irq.c

   1/*
   2 * Copyright (C) 2007 Lemote Inc.
   3 * Author: Fuxin Zhang, zhangfx@lemote.com
   4 *
   5 *  This program is free software; you can redistribute  it and/or modify it
   6 *  under  the terms of  the GNU General  Public License as published by the
   7 *  Free Software Foundation;  either version 2 of the  License, or (at your
   8 *  option) any later version.
   9 */
  10
  11#include <linux/export.h>
  12#include <linux/init.h>
  13#include <linux/interrupt.h>
  14
  15#include <asm/irq_cpu.h>
  16#include <asm/i8259.h>
  17#include <asm/mipsregs.h>
  18
  19#include <loongson.h>
  20#include <machine.h>
  21
  22#define LOONGSON_TIMER_IRQ      (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
  23#define LOONGSON_NORTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 6) /* bonito */
  24#define LOONGSON_UART_IRQ       (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
  25#define LOONGSON_SOUTH_BRIDGE_IRQ       (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
  26
  27#define LOONGSON_INT_BIT_INT0           (1 << 11)
  28#define LOONGSON_INT_BIT_INT1           (1 << 12)
  29
  30/*
  31 * The generic i8259_irq() make the kernel hang on booting.  Since we cannot
  32 * get the irq via the IRR directly, we access the ISR instead.
  33 */
  34int mach_i8259_irq(void)
  35{
  36        int irq, isr;
  37
  38        irq = -1;
  39
  40        if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
  41                raw_spin_lock(&i8259A_lock);
  42                isr = inb(PIC_MASTER_CMD) &
  43                        ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
  44                if (!isr)
  45                        isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8;
  46                irq = ffs(isr) - 1;
  47                if (unlikely(irq == 7)) {
  48                        /*
  49                         * This may be a spurious interrupt.
  50                         *
  51                         * Read the interrupt status register (ISR). If the most
  52                         * significant bit is not set then there is no valid
  53                         * interrupt.
  54                         */
  55                        outb(0x0B, PIC_MASTER_ISR);     /* ISR register */
  56                        if (~inb(PIC_MASTER_ISR) & 0x80)
  57                                irq = -1;
  58                }
  59                raw_spin_unlock(&i8259A_lock);
  60        }
  61
  62        return irq;
  63}
  64EXPORT_SYMBOL(mach_i8259_irq);
  65
  66static void i8259_irqdispatch(void)
  67{
  68        int irq;
  69
  70        irq = mach_i8259_irq();
  71        if (irq >= 0)
  72                do_IRQ(irq);
  73        else
  74                spurious_interrupt();
  75}
  76
  77void mach_irq_dispatch(unsigned int pending)
  78{
  79        if (pending & CAUSEF_IP7)
  80                do_IRQ(LOONGSON_TIMER_IRQ);
  81        else if (pending & CAUSEF_IP6) {        /* North Bridge, Perf counter */
  82                do_perfcnt_IRQ();
  83                bonito_irqdispatch();
  84        } else if (pending & CAUSEF_IP3)        /* CPU UART */
  85                do_IRQ(LOONGSON_UART_IRQ);
  86        else if (pending & CAUSEF_IP2)  /* South Bridge */
  87                i8259_irqdispatch();
  88        else
  89                spurious_interrupt();
  90}
  91
  92static irqreturn_t ip6_action(int cpl, void *dev_id)
  93{
  94        return IRQ_HANDLED;
  95}
  96
  97static struct irqaction ip6_irqaction = {
  98        .handler = ip6_action,
  99        .name = "cascade",
 100        .flags = IRQF_SHARED | IRQF_NO_THREAD,
 101};
 102
 103static struct irqaction cascade_irqaction = {
 104        .handler = no_action,
 105        .name = "cascade",
 106        .flags = IRQF_NO_THREAD,
 107};
 108
 109void __init mach_init_irq(void)
 110{
 111        /* init all controller
 112         *   0-15         ------> i8259 interrupt
 113         *   16-23        ------> mips cpu interrupt
 114         *   32-63        ------> bonito irq
 115         */
 116
 117        /* setup cs5536 as high level trigger */
 118        LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1;
 119        LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1);
 120
 121        /* Sets the first-level interrupt dispatcher. */
 122        mips_cpu_irq_init();
 123        init_i8259_irqs();
 124        bonito_irq_init();
 125
 126        /* setup north bridge irq (bonito) */
 127        setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction);
 128        /* setup source bridge irq (i8259) */
 129        setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction);
 130}
 131