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9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/vmalloc.h>
16#include <linux/clk.h>
17#include <linux/of_platform.h>
18#include <linux/of_gpio.h>
19#include <linux/of_irq.h>
20#include <linux/of_pci.h>
21
22#include <asm/addrspace.h>
23
24#include <lantiq_soc.h>
25#include <lantiq_irq.h>
26
27#include "pci-lantiq.h"
28
29#define PCI_CR_FCI_ADDR_MAP0 0x00C0
30#define PCI_CR_FCI_ADDR_MAP1 0x00C4
31#define PCI_CR_FCI_ADDR_MAP2 0x00C8
32#define PCI_CR_FCI_ADDR_MAP3 0x00CC
33#define PCI_CR_FCI_ADDR_MAP4 0x00D0
34#define PCI_CR_FCI_ADDR_MAP5 0x00D4
35#define PCI_CR_FCI_ADDR_MAP6 0x00D8
36#define PCI_CR_FCI_ADDR_MAP7 0x00DC
37#define PCI_CR_CLK_CTRL 0x0000
38#define PCI_CR_PCI_MOD 0x0030
39#define PCI_CR_PC_ARB 0x0080
40#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
41#define PCI_CR_BAR11MASK 0x0044
42#define PCI_CR_BAR12MASK 0x0048
43#define PCI_CR_BAR13MASK 0x004C
44#define PCI_CS_BASE_ADDR1 0x0010
45#define PCI_CR_PCI_ADDR_MAP11 0x0064
46#define PCI_CR_FCI_BURST_LENGTH 0x00E8
47#define PCI_CR_PCI_EOI 0x002C
48#define PCI_CS_STS_CMD 0x0004
49
50#define PCI_MASTER0_REQ_MASK_2BITS 8
51#define PCI_MASTER1_REQ_MASK_2BITS 10
52#define PCI_MASTER2_REQ_MASK_2BITS 12
53#define INTERNAL_ARB_ENABLE_BIT 0
54
55#define LTQ_CGU_IFCCR 0x0018
56#define LTQ_CGU_PCICR 0x0034
57
58#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
59#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
60
61#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
62#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
63
64__iomem void *ltq_pci_mapped_cfg;
65static __iomem void *ltq_pci_membase;
66
67static int reset_gpio;
68static struct clk *clk_pci, *clk_external;
69static struct resource pci_io_resource;
70static struct resource pci_mem_resource;
71static struct pci_ops pci_ops = {
72 .read = ltq_pci_read_config_dword,
73 .write = ltq_pci_write_config_dword
74};
75
76static struct pci_controller pci_controller = {
77 .pci_ops = &pci_ops,
78 .mem_resource = &pci_mem_resource,
79 .mem_offset = 0x00000000UL,
80 .io_resource = &pci_io_resource,
81 .io_offset = 0x00000000UL,
82};
83
84static inline u32 ltq_calc_bar11mask(void)
85{
86 u32 mem, bar11mask;
87
88
89 mem = get_num_physpages() * PAGE_SIZE;
90 bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
91
92 return bar11mask;
93}
94
95static int ltq_pci_startup(struct platform_device *pdev)
96{
97 struct device_node *node = pdev->dev.of_node;
98 const __be32 *req_mask, *bus_clk;
99 u32 temp_buffer;
100
101
102 clk_pci = clk_get(&pdev->dev, NULL);
103 if (IS_ERR(clk_pci)) {
104 dev_err(&pdev->dev, "failed to get pci clock\n");
105 return PTR_ERR(clk_pci);
106 }
107
108 clk_external = clk_get(&pdev->dev, "external");
109 if (IS_ERR(clk_external)) {
110 clk_put(clk_pci);
111 dev_err(&pdev->dev, "failed to get external pci clock\n");
112 return PTR_ERR(clk_external);
113 }
114
115
116 bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
117 if (bus_clk)
118 clk_set_rate(clk_pci, *bus_clk);
119
120
121 clk_enable(clk_pci);
122 if (of_find_property(node, "lantiq,external-clock", NULL))
123 clk_enable(clk_external);
124 else
125 clk_disable(clk_external);
126
127
128 reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
129 if (gpio_is_valid(reset_gpio)) {
130 int ret = devm_gpio_request(&pdev->dev,
131 reset_gpio, "pci-reset");
132 if (ret) {
133 dev_err(&pdev->dev,
134 "failed to request gpio %d\n", reset_gpio);
135 return ret;
136 }
137 gpio_direction_output(reset_gpio, 1);
138 }
139
140
141 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
142
143
144 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
145 wmb();
146
147 ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
148
149
150 temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
151
152 req_mask = of_get_property(node, "req-mask", NULL);
153 if (req_mask)
154 temp_buffer &= ~((*req_mask & 0xf) << 16);
155 else
156 temp_buffer &= ~0xf0000;
157
158 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
159
160 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
161
162
163 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
164
165
166 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
167 ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
168 wmb();
169
170
171 ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
172 ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
173 ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
174 ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
175 ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
176 ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
177 ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
178 ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
179 ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
180 ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
181 ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
182 ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
183
184 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
185 wmb();
186 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
187 PCI_CR_BAR12MASK);
188 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
189 PCI_CR_BAR13MASK);
190
191 ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
192 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
193 wmb();
194
195
196 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
197 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
198
199
200 if (gpio_is_valid(reset_gpio)) {
201 __gpio_set_value(reset_gpio, 0);
202 wmb();
203 mdelay(1);
204 __gpio_set_value(reset_gpio, 1);
205 }
206 return 0;
207}
208
209static int ltq_pci_probe(struct platform_device *pdev)
210{
211 struct resource *res_cfg, *res_bridge;
212
213 pci_clear_flags(PCI_PROBE_ONLY);
214
215 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
216 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
217 if (IS_ERR(ltq_pci_membase))
218 return PTR_ERR(ltq_pci_membase);
219
220 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
221 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
222 if (IS_ERR(ltq_pci_mapped_cfg))
223 return PTR_ERR(ltq_pci_mapped_cfg);
224
225 ltq_pci_startup(pdev);
226
227 pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
228 register_pci_controller(&pci_controller);
229 return 0;
230}
231
232static const struct of_device_id ltq_pci_match[] = {
233 { .compatible = "lantiq,pci-xway" },
234 {},
235};
236
237static struct platform_driver ltq_pci_driver = {
238 .probe = ltq_pci_probe,
239 .driver = {
240 .name = "pci-xway",
241 .of_match_table = ltq_pci_match,
242 },
243};
244
245int __init pcibios_init(void)
246{
247 int ret = platform_driver_register(<q_pci_driver);
248 if (ret)
249 pr_info("pci-xway: Error registering platform driver!");
250 return ret;
251}
252
253arch_initcall(pcibios_init);
254
