LXR linux/arch/sh/include/asm/io.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2#ifndef __ASM_SH_IO_H
   3#define __ASM_SH_IO_H
   4
   5/*
   6 * Convention:
   7 *    read{b,w,l,q}/write{b,w,l,q} are for PCI,
   8 *    while in{b,w,l}/out{b,w,l} are for ISA
   9 *
  10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
  11 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
  12 *
  13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
  14 * automatically, there are also __raw versions, which do not.
  15 */
  16#include <linux/errno.h>
  17#include <asm/cache.h>
  18#include <asm/addrspace.h>
  19#include <asm/machvec.h>
  20#include <asm/pgtable.h>
  21#include <asm-generic/iomap.h>
  22
  23#ifdef __KERNEL__
  24#define __IO_PREFIX     generic
  25#include <asm/io_generic.h>
  26#include <asm/io_trapped.h>
  27#include <mach/mangle-port.h>
  28
  29#define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile u8  __force *)(a) = (v))
  30#define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
  31#define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
  32#define __raw_writeq(v,a)       (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
  33
  34#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile u8  __force *)(a))
  35#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile u16 __force *)(a))
  36#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile u32 __force *)(a))
  37#define __raw_readq(a)          (__chk_io_ptr(a), *(volatile u64 __force *)(a))
  38
  39#define readb_relaxed(c)        ({ u8  __v = ioswabb(__raw_readb(c)); __v; })
  40#define readw_relaxed(c)        ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
  41#define readl_relaxed(c)        ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
  42#define readq_relaxed(c)        ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
  43
  44#define writeb_relaxed(v,c)     ((void)__raw_writeb((__force  u8)ioswabb(v),c))
  45#define writew_relaxed(v,c)     ((void)__raw_writew((__force u16)ioswabw(v),c))
  46#define writel_relaxed(v,c)     ((void)__raw_writel((__force u32)ioswabl(v),c))
  47#define writeq_relaxed(v,c)     ((void)__raw_writeq((__force u64)ioswabq(v),c))
  48
  49#define readb(a)                ({ u8  r_ = readb_relaxed(a); rmb(); r_; })
  50#define readw(a)                ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
  51#define readl(a)                ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
  52#define readq(a)                ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
  53
  54#define writeb(v,a)             ({ wmb(); writeb_relaxed((v),(a)); })
  55#define writew(v,a)             ({ wmb(); writew_relaxed((v),(a)); })
  56#define writel(v,a)             ({ wmb(); writel_relaxed((v),(a)); })
  57#define writeq(v,a)             ({ wmb(); writeq_relaxed((v),(a)); })
  58
  59#define readsb(p,d,l)           __raw_readsb(p,d,l)
  60#define readsw(p,d,l)           __raw_readsw(p,d,l)
  61#define readsl(p,d,l)           __raw_readsl(p,d,l)
  62
  63#define writesb(p,d,l)          __raw_writesb(p,d,l)
  64#define writesw(p,d,l)          __raw_writesw(p,d,l)
  65#define writesl(p,d,l)          __raw_writesl(p,d,l)
  66
  67#define __BUILD_UNCACHED_IO(bwlq, type)                                 \
  68static inline type read##bwlq##_uncached(unsigned long addr)            \
  69{                                                                       \
  70        type ret;                                                       \
  71        jump_to_uncached();                                             \
  72        ret = __raw_read##bwlq(addr);                                   \
  73        back_to_cached();                                               \
  74        return ret;                                                     \
  75}                                                                       \
  76                                                                        \
  77static inline void write##bwlq##_uncached(type v, unsigned long addr)   \
  78{                                                                       \
  79        jump_to_uncached();                                             \
  80        __raw_write##bwlq(v, addr);                                     \
  81        back_to_cached();                                               \
  82}
  83
  84__BUILD_UNCACHED_IO(b, u8)
  85__BUILD_UNCACHED_IO(w, u16)
  86__BUILD_UNCACHED_IO(l, u32)
  87__BUILD_UNCACHED_IO(q, u64)
  88
  89#define __BUILD_MEMORY_STRING(pfx, bwlq, type)                          \
  90                                                                        \
  91static inline void                                                      \
  92pfx##writes##bwlq(volatile void __iomem *mem, const void *addr,         \
  93                  unsigned int count)                                   \
  94{                                                                       \
  95        const volatile type *__addr = addr;                             \
  96                                                                        \
  97        while (count--) {                                               \
  98                __raw_write##bwlq(*__addr, mem);                        \
  99                __addr++;                                               \
 100        }                                                               \
 101}                                                                       \
 102                                                                        \
 103static inline void pfx##reads##bwlq(volatile void __iomem *mem,         \
 104                                    void *addr, unsigned int count)     \
 105{                                                                       \
 106        volatile type *__addr = addr;                                   \
 107                                                                        \
 108        while (count--) {                                               \
 109                *__addr = __raw_read##bwlq(mem);                        \
 110                __addr++;                                               \
 111        }                                                               \
 112}
 113
 114__BUILD_MEMORY_STRING(__raw_, b, u8)
 115__BUILD_MEMORY_STRING(__raw_, w, u16)
 116
 117#ifdef CONFIG_SUPERH32
 118void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 119void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 120#else
 121__BUILD_MEMORY_STRING(__raw_, l, u32)
 122#endif
 123
 124__BUILD_MEMORY_STRING(__raw_, q, u64)
 125
 126#ifdef CONFIG_HAS_IOPORT_MAP
 127
 128/*
 129 * Slowdown I/O port space accesses for antique hardware.
 130 */
 131#undef CONF_SLOWDOWN_IO
 132
 133/*
 134 * On SuperH I/O ports are memory mapped, so we access them using normal
 135 * load/store instructions. sh_io_port_base is the virtual address to
 136 * which all ports are being mapped.
 137 */
 138extern unsigned long sh_io_port_base;
 139
 140static inline void __set_io_port_base(unsigned long pbase)
 141{
 142        *(unsigned long *)&sh_io_port_base = pbase;
 143        barrier();
 144}
 145
 146#ifdef CONFIG_GENERIC_IOMAP
 147#define __ioport_map ioport_map
 148#else
 149extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
 150#endif
 151
 152#ifdef CONF_SLOWDOWN_IO
 153#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
 154#else
 155#define SLOW_DOWN_IO
 156#endif
 157
 158#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
 159                                                                        \
 160static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
 161{                                                                       \
 162        volatile type *__addr;                                          \
 163                                                                        \
 164        __addr = __ioport_map(port, sizeof(type));                      \
 165        *__addr = val;                                                  \
 166        slow;                                                           \
 167}                                                                       \
 168                                                                        \
 169static inline type pfx##in##bwlq##p(unsigned long port)                 \
 170{                                                                       \
 171        volatile type *__addr;                                          \
 172        type __val;                                                     \
 173                                                                        \
 174        __addr = __ioport_map(port, sizeof(type));                      \
 175        __val = *__addr;                                                \
 176        slow;                                                           \
 177                                                                        \
 178        return __val;                                                   \
 179}
 180
 181#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
 182        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
 183        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
 184
 185#define BUILDIO_IOPORT(bwlq, type)                                      \
 186        __BUILD_IOPORT_PFX(, bwlq, type)
 187
 188BUILDIO_IOPORT(b, u8)
 189BUILDIO_IOPORT(w, u16)
 190BUILDIO_IOPORT(l, u32)
 191BUILDIO_IOPORT(q, u64)
 192
 193#define __BUILD_IOPORT_STRING(bwlq, type)                               \
 194                                                                        \
 195static inline void outs##bwlq(unsigned long port, const void *addr,     \
 196                              unsigned int count)                       \
 197{                                                                       \
 198        const volatile type *__addr = addr;                             \
 199                                                                        \
 200        while (count--) {                                               \
 201                out##bwlq(*__addr, port);                               \
 202                __addr++;                                               \
 203        }                                                               \
 204}                                                                       \
 205                                                                        \
 206static inline void ins##bwlq(unsigned long port, void *addr,            \
 207                             unsigned int count)                        \
 208{                                                                       \
 209        volatile type *__addr = addr;                                   \
 210                                                                        \
 211        while (count--) {                                               \
 212                *__addr = in##bwlq(port);                               \
 213                __addr++;                                               \
 214        }                                                               \
 215}
 216
 217__BUILD_IOPORT_STRING(b, u8)
 218__BUILD_IOPORT_STRING(w, u16)
 219__BUILD_IOPORT_STRING(l, u32)
 220__BUILD_IOPORT_STRING(q, u64)
 221
 222#else /* !CONFIG_HAS_IOPORT_MAP */
 223
 224#include <asm/io_noioport.h>
 225
 226#endif
 227
 228
 229#define IO_SPACE_LIMIT 0xffffffff
 230
 231/* synco on SH-4A, otherwise a nop */
 232#define mmiowb()                wmb()
 233
 234/* We really want to try and get these to memcpy etc */
 235void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
 236void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
 237void memset_io(volatile void __iomem *, int, unsigned long);
 238
 239/* Quad-word real-mode I/O, don't ask.. */
 240unsigned long long peek_real_address_q(unsigned long long addr);
 241unsigned long long poke_real_address_q(unsigned long long addr,
 242                                       unsigned long long val);
 243
 244#if !defined(CONFIG_MMU)
 245#define virt_to_phys(address)   ((unsigned long)(address))
 246#define phys_to_virt(address)   ((void *)(address))
 247#else
 248#define virt_to_phys(address)   (__pa(address))
 249#define phys_to_virt(address)   (__va(address))
 250#endif
 251
 252/*
 253 * On 32-bit SH, we traditionally have the whole physical address space
 254 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
 255 * not need to do anything but place the address in the proper segment.
 256 * This is true for P1 and P2 addresses, as well as some P3 ones.
 257 * However, most of the P3 addresses and newer cores using extended
 258 * addressing need to map through page tables, so the ioremap()
 259 * implementation becomes a bit more complicated.
 260 *
 261 * See arch/sh/mm/ioremap.c for additional notes on this.
 262 *
 263 * We cheat a bit and always return uncachable areas until we've fixed
 264 * the drivers to handle caching properly.
 265 *
 266 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
 267 * doesn't exist, so everything must go through page tables.
 268 */
 269#ifdef CONFIG_MMU
 270void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
 271                               pgprot_t prot, void *caller);
 272void __iounmap(void __iomem *addr);
 273
 274static inline void __iomem *
 275__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
 276{
 277        return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
 278}
 279
 280static inline void __iomem *
 281__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
 282{
 283#ifdef CONFIG_29BIT
 284        phys_addr_t last_addr = offset + size - 1;
 285
 286        /*
 287         * For P1 and P2 space this is trivial, as everything is already
 288         * mapped. Uncached access for P1 addresses are done through P2.
 289         * In the P3 case or for addresses outside of the 29-bit space,
 290         * mapping must be done by the PMB or by using page tables.
 291         */
 292        if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
 293                u64 flags = pgprot_val(prot);
 294
 295                /*
 296                 * Anything using the legacy PTEA space attributes needs
 297                 * to be kicked down to page table mappings.
 298                 */
 299                if (unlikely(flags & _PAGE_PCC_MASK))
 300                        return NULL;
 301                if (unlikely(flags & _PAGE_CACHABLE))
 302                        return (void __iomem *)P1SEGADDR(offset);
 303
 304                return (void __iomem *)P2SEGADDR(offset);
 305        }
 306
 307        /* P4 above the store queues are always mapped. */
 308        if (unlikely(offset >= P3_ADDR_MAX))
 309                return (void __iomem *)P4SEGADDR(offset);
 310#endif
 311
 312        return NULL;
 313}
 314
 315static inline void __iomem *
 316__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
 317{
 318        void __iomem *ret;
 319
 320        ret = __ioremap_trapped(offset, size);
 321        if (ret)
 322                return ret;
 323
 324        ret = __ioremap_29bit(offset, size, prot);
 325        if (ret)
 326                return ret;
 327
 328        return __ioremap(offset, size, prot);
 329}
 330#else
 331#define __ioremap(offset, size, prot)           ((void __iomem *)(offset))
 332#define __ioremap_mode(offset, size, prot)      ((void __iomem *)(offset))
 333#define __iounmap(addr)                         do { } while (0)
 334#endif /* CONFIG_MMU */
 335
 336static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
 337{
 338        return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
 339}
 340
 341static inline void __iomem *
 342ioremap_cache(phys_addr_t offset, unsigned long size)
 343{
 344        return __ioremap_mode(offset, size, PAGE_KERNEL);
 345}
 346#define ioremap_cache ioremap_cache
 347
 348#ifdef CONFIG_HAVE_IOREMAP_PROT
 349static inline void __iomem *
 350ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
 351{
 352        return __ioremap_mode(offset, size, __pgprot(flags));
 353}
 354#endif
 355
 356#ifdef CONFIG_IOREMAP_FIXED
 357extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
 358extern int iounmap_fixed(void __iomem *);
 359extern void ioremap_fixed_init(void);
 360#else
 361static inline void __iomem *
 362ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
 363{
 364        BUG();
 365        return NULL;
 366}
 367
 368static inline void ioremap_fixed_init(void) { }
 369static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
 370#endif
 371
 372#define ioremap_nocache ioremap
 373#define ioremap_uc      ioremap
 374#define iounmap         __iounmap
 375
 376/*
 377 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 378 * access
 379 */
 380#define xlate_dev_mem_ptr(p)    __va(p)
 381
 382/*
 383 * Convert a virtual cached pointer to an uncached pointer
 384 */
 385#define xlate_dev_kmem_ptr(p)   p
 386
 387#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 388int valid_phys_addr_range(phys_addr_t addr, size_t size);
 389int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 390
 391#endif /* __KERNEL__ */
 392
 393#endif /* __ASM_SH_IO_H */
 394