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92#include <linux/module.h>
93#include <linux/slab.h>
94#include <linux/perf_event.h>
95#include <linux/nospec.h>
96#include <asm/cpu_device_id.h>
97#include <asm/intel-family.h>
98#include "../perf_event.h"
99
100MODULE_LICENSE("GPL");
101
102#define DEFINE_CSTATE_FORMAT_ATTR(_var, _name, _format) \
103static ssize_t __cstate_##_var##_show(struct kobject *kobj, \
104 struct kobj_attribute *attr, \
105 char *page) \
106{ \
107 BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \
108 return sprintf(page, _format "\n"); \
109} \
110static struct kobj_attribute format_attr_##_var = \
111 __ATTR(_name, 0444, __cstate_##_var##_show, NULL)
112
113static ssize_t cstate_get_attr_cpumask(struct device *dev,
114 struct device_attribute *attr,
115 char *buf);
116
117
118struct cstate_model {
119 unsigned long core_events;
120 unsigned long pkg_events;
121 unsigned long quirks;
122};
123
124
125#define SLM_PKG_C6_USE_C7_MSR (1UL << 0)
126#define KNL_CORE_C6_MSR (1UL << 1)
127
128struct perf_cstate_msr {
129 u64 msr;
130 struct perf_pmu_events_attr *attr;
131};
132
133
134
135static struct pmu cstate_core_pmu;
136static bool has_cstate_core;
137
138enum perf_cstate_core_events {
139 PERF_CSTATE_CORE_C1_RES = 0,
140 PERF_CSTATE_CORE_C3_RES,
141 PERF_CSTATE_CORE_C6_RES,
142 PERF_CSTATE_CORE_C7_RES,
143
144 PERF_CSTATE_CORE_EVENT_MAX,
145};
146
147PMU_EVENT_ATTR_STRING(c1-residency, evattr_cstate_core_c1, "event=0x00");
148PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_core_c3, "event=0x01");
149PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_core_c6, "event=0x02");
150PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_core_c7, "event=0x03");
151
152static struct perf_cstate_msr core_msr[] = {
153 [PERF_CSTATE_CORE_C1_RES] = { MSR_CORE_C1_RES, &evattr_cstate_core_c1 },
154 [PERF_CSTATE_CORE_C3_RES] = { MSR_CORE_C3_RESIDENCY, &evattr_cstate_core_c3 },
155 [PERF_CSTATE_CORE_C6_RES] = { MSR_CORE_C6_RESIDENCY, &evattr_cstate_core_c6 },
156 [PERF_CSTATE_CORE_C7_RES] = { MSR_CORE_C7_RESIDENCY, &evattr_cstate_core_c7 },
157};
158
159static struct attribute *core_events_attrs[PERF_CSTATE_CORE_EVENT_MAX + 1] = {
160 NULL,
161};
162
163static struct attribute_group core_events_attr_group = {
164 .name = "events",
165 .attrs = core_events_attrs,
166};
167
168DEFINE_CSTATE_FORMAT_ATTR(core_event, event, "config:0-63");
169static struct attribute *core_format_attrs[] = {
170 &format_attr_core_event.attr,
171 NULL,
172};
173
174static struct attribute_group core_format_attr_group = {
175 .name = "format",
176 .attrs = core_format_attrs,
177};
178
179static cpumask_t cstate_core_cpu_mask;
180static DEVICE_ATTR(cpumask, S_IRUGO, cstate_get_attr_cpumask, NULL);
181
182static struct attribute *cstate_cpumask_attrs[] = {
183 &dev_attr_cpumask.attr,
184 NULL,
185};
186
187static struct attribute_group cpumask_attr_group = {
188 .attrs = cstate_cpumask_attrs,
189};
190
191static const struct attribute_group *core_attr_groups[] = {
192 &core_events_attr_group,
193 &core_format_attr_group,
194 &cpumask_attr_group,
195 NULL,
196};
197
198
199static struct pmu cstate_pkg_pmu;
200static bool has_cstate_pkg;
201
202enum perf_cstate_pkg_events {
203 PERF_CSTATE_PKG_C2_RES = 0,
204 PERF_CSTATE_PKG_C3_RES,
205 PERF_CSTATE_PKG_C6_RES,
206 PERF_CSTATE_PKG_C7_RES,
207 PERF_CSTATE_PKG_C8_RES,
208 PERF_CSTATE_PKG_C9_RES,
209 PERF_CSTATE_PKG_C10_RES,
210
211 PERF_CSTATE_PKG_EVENT_MAX,
212};
213
214PMU_EVENT_ATTR_STRING(c2-residency, evattr_cstate_pkg_c2, "event=0x00");
215PMU_EVENT_ATTR_STRING(c3-residency, evattr_cstate_pkg_c3, "event=0x01");
216PMU_EVENT_ATTR_STRING(c6-residency, evattr_cstate_pkg_c6, "event=0x02");
217PMU_EVENT_ATTR_STRING(c7-residency, evattr_cstate_pkg_c7, "event=0x03");
218PMU_EVENT_ATTR_STRING(c8-residency, evattr_cstate_pkg_c8, "event=0x04");
219PMU_EVENT_ATTR_STRING(c9-residency, evattr_cstate_pkg_c9, "event=0x05");
220PMU_EVENT_ATTR_STRING(c10-residency, evattr_cstate_pkg_c10, "event=0x06");
221
222static struct perf_cstate_msr pkg_msr[] = {
223 [PERF_CSTATE_PKG_C2_RES] = { MSR_PKG_C2_RESIDENCY, &evattr_cstate_pkg_c2 },
224 [PERF_CSTATE_PKG_C3_RES] = { MSR_PKG_C3_RESIDENCY, &evattr_cstate_pkg_c3 },
225 [PERF_CSTATE_PKG_C6_RES] = { MSR_PKG_C6_RESIDENCY, &evattr_cstate_pkg_c6 },
226 [PERF_CSTATE_PKG_C7_RES] = { MSR_PKG_C7_RESIDENCY, &evattr_cstate_pkg_c7 },
227 [PERF_CSTATE_PKG_C8_RES] = { MSR_PKG_C8_RESIDENCY, &evattr_cstate_pkg_c8 },
228 [PERF_CSTATE_PKG_C9_RES] = { MSR_PKG_C9_RESIDENCY, &evattr_cstate_pkg_c9 },
229 [PERF_CSTATE_PKG_C10_RES] = { MSR_PKG_C10_RESIDENCY, &evattr_cstate_pkg_c10 },
230};
231
232static struct attribute *pkg_events_attrs[PERF_CSTATE_PKG_EVENT_MAX + 1] = {
233 NULL,
234};
235
236static struct attribute_group pkg_events_attr_group = {
237 .name = "events",
238 .attrs = pkg_events_attrs,
239};
240
241DEFINE_CSTATE_FORMAT_ATTR(pkg_event, event, "config:0-63");
242static struct attribute *pkg_format_attrs[] = {
243 &format_attr_pkg_event.attr,
244 NULL,
245};
246static struct attribute_group pkg_format_attr_group = {
247 .name = "format",
248 .attrs = pkg_format_attrs,
249};
250
251static cpumask_t cstate_pkg_cpu_mask;
252
253static const struct attribute_group *pkg_attr_groups[] = {
254 &pkg_events_attr_group,
255 &pkg_format_attr_group,
256 &cpumask_attr_group,
257 NULL,
258};
259
260static ssize_t cstate_get_attr_cpumask(struct device *dev,
261 struct device_attribute *attr,
262 char *buf)
263{
264 struct pmu *pmu = dev_get_drvdata(dev);
265
266 if (pmu == &cstate_core_pmu)
267 return cpumap_print_to_pagebuf(true, buf, &cstate_core_cpu_mask);
268 else if (pmu == &cstate_pkg_pmu)
269 return cpumap_print_to_pagebuf(true, buf, &cstate_pkg_cpu_mask);
270 else
271 return 0;
272}
273
274static int cstate_pmu_event_init(struct perf_event *event)
275{
276 u64 cfg = event->attr.config;
277 int cpu;
278
279 if (event->attr.type != event->pmu->type)
280 return -ENOENT;
281
282
283 if (event->attr.exclude_user ||
284 event->attr.exclude_kernel ||
285 event->attr.exclude_hv ||
286 event->attr.exclude_idle ||
287 event->attr.exclude_host ||
288 event->attr.exclude_guest ||
289 event->attr.sample_period)
290 return -EINVAL;
291
292 if (event->cpu < 0)
293 return -EINVAL;
294
295 if (event->pmu == &cstate_core_pmu) {
296 if (cfg >= PERF_CSTATE_CORE_EVENT_MAX)
297 return -EINVAL;
298 if (!core_msr[cfg].attr)
299 return -EINVAL;
300 event->hw.event_base = core_msr[cfg].msr;
301 cpu = cpumask_any_and(&cstate_core_cpu_mask,
302 topology_sibling_cpumask(event->cpu));
303 } else if (event->pmu == &cstate_pkg_pmu) {
304 if (cfg >= PERF_CSTATE_PKG_EVENT_MAX)
305 return -EINVAL;
306 cfg = array_index_nospec((unsigned long)cfg, PERF_CSTATE_PKG_EVENT_MAX);
307 if (!pkg_msr[cfg].attr)
308 return -EINVAL;
309 event->hw.event_base = pkg_msr[cfg].msr;
310 cpu = cpumask_any_and(&cstate_pkg_cpu_mask,
311 topology_core_cpumask(event->cpu));
312 } else {
313 return -ENOENT;
314 }
315
316 if (cpu >= nr_cpu_ids)
317 return -ENODEV;
318
319 event->cpu = cpu;
320 event->hw.config = cfg;
321 event->hw.idx = -1;
322 return 0;
323}
324
325static inline u64 cstate_pmu_read_counter(struct perf_event *event)
326{
327 u64 val;
328
329 rdmsrl(event->hw.event_base, val);
330 return val;
331}
332
333static void cstate_pmu_event_update(struct perf_event *event)
334{
335 struct hw_perf_event *hwc = &event->hw;
336 u64 prev_raw_count, new_raw_count;
337
338again:
339 prev_raw_count = local64_read(&hwc->prev_count);
340 new_raw_count = cstate_pmu_read_counter(event);
341
342 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
343 new_raw_count) != prev_raw_count)
344 goto again;
345
346 local64_add(new_raw_count - prev_raw_count, &event->count);
347}
348
349static void cstate_pmu_event_start(struct perf_event *event, int mode)
350{
351 local64_set(&event->hw.prev_count, cstate_pmu_read_counter(event));
352}
353
354static void cstate_pmu_event_stop(struct perf_event *event, int mode)
355{
356 cstate_pmu_event_update(event);
357}
358
359static void cstate_pmu_event_del(struct perf_event *event, int mode)
360{
361 cstate_pmu_event_stop(event, PERF_EF_UPDATE);
362}
363
364static int cstate_pmu_event_add(struct perf_event *event, int mode)
365{
366 if (mode & PERF_EF_START)
367 cstate_pmu_event_start(event, mode);
368
369 return 0;
370}
371
372
373
374
375
376static int cstate_cpu_exit(unsigned int cpu)
377{
378 unsigned int target;
379
380 if (has_cstate_core &&
381 cpumask_test_and_clear_cpu(cpu, &cstate_core_cpu_mask)) {
382
383 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
384
385 if (target < nr_cpu_ids) {
386 cpumask_set_cpu(target, &cstate_core_cpu_mask);
387 perf_pmu_migrate_context(&cstate_core_pmu, cpu, target);
388 }
389 }
390
391 if (has_cstate_pkg &&
392 cpumask_test_and_clear_cpu(cpu, &cstate_pkg_cpu_mask)) {
393
394 target = cpumask_any_but(topology_core_cpumask(cpu), cpu);
395
396 if (target < nr_cpu_ids) {
397 cpumask_set_cpu(target, &cstate_pkg_cpu_mask);
398 perf_pmu_migrate_context(&cstate_pkg_pmu, cpu, target);
399 }
400 }
401 return 0;
402}
403
404static int cstate_cpu_init(unsigned int cpu)
405{
406 unsigned int target;
407
408
409
410
411
412 target = cpumask_any_and(&cstate_core_cpu_mask,
413 topology_sibling_cpumask(cpu));
414
415 if (has_cstate_core && target >= nr_cpu_ids)
416 cpumask_set_cpu(cpu, &cstate_core_cpu_mask);
417
418
419
420
421
422 target = cpumask_any_and(&cstate_pkg_cpu_mask,
423 topology_core_cpumask(cpu));
424 if (has_cstate_pkg && target >= nr_cpu_ids)
425 cpumask_set_cpu(cpu, &cstate_pkg_cpu_mask);
426
427 return 0;
428}
429
430static struct pmu cstate_core_pmu = {
431 .attr_groups = core_attr_groups,
432 .name = "cstate_core",
433 .task_ctx_nr = perf_invalid_context,
434 .event_init = cstate_pmu_event_init,
435 .add = cstate_pmu_event_add,
436 .del = cstate_pmu_event_del,
437 .start = cstate_pmu_event_start,
438 .stop = cstate_pmu_event_stop,
439 .read = cstate_pmu_event_update,
440 .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
441 .module = THIS_MODULE,
442};
443
444static struct pmu cstate_pkg_pmu = {
445 .attr_groups = pkg_attr_groups,
446 .name = "cstate_pkg",
447 .task_ctx_nr = perf_invalid_context,
448 .event_init = cstate_pmu_event_init,
449 .add = cstate_pmu_event_add,
450 .del = cstate_pmu_event_del,
451 .start = cstate_pmu_event_start,
452 .stop = cstate_pmu_event_stop,
453 .read = cstate_pmu_event_update,
454 .capabilities = PERF_PMU_CAP_NO_INTERRUPT,
455 .module = THIS_MODULE,
456};
457
458static const struct cstate_model nhm_cstates __initconst = {
459 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) |
460 BIT(PERF_CSTATE_CORE_C6_RES),
461
462 .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) |
463 BIT(PERF_CSTATE_PKG_C6_RES) |
464 BIT(PERF_CSTATE_PKG_C7_RES),
465};
466
467static const struct cstate_model snb_cstates __initconst = {
468 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) |
469 BIT(PERF_CSTATE_CORE_C6_RES) |
470 BIT(PERF_CSTATE_CORE_C7_RES),
471
472 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
473 BIT(PERF_CSTATE_PKG_C3_RES) |
474 BIT(PERF_CSTATE_PKG_C6_RES) |
475 BIT(PERF_CSTATE_PKG_C7_RES),
476};
477
478static const struct cstate_model hswult_cstates __initconst = {
479 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) |
480 BIT(PERF_CSTATE_CORE_C6_RES) |
481 BIT(PERF_CSTATE_CORE_C7_RES),
482
483 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
484 BIT(PERF_CSTATE_PKG_C3_RES) |
485 BIT(PERF_CSTATE_PKG_C6_RES) |
486 BIT(PERF_CSTATE_PKG_C7_RES) |
487 BIT(PERF_CSTATE_PKG_C8_RES) |
488 BIT(PERF_CSTATE_PKG_C9_RES) |
489 BIT(PERF_CSTATE_PKG_C10_RES),
490};
491
492static const struct cstate_model cnl_cstates __initconst = {
493 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
494 BIT(PERF_CSTATE_CORE_C3_RES) |
495 BIT(PERF_CSTATE_CORE_C6_RES) |
496 BIT(PERF_CSTATE_CORE_C7_RES),
497
498 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
499 BIT(PERF_CSTATE_PKG_C3_RES) |
500 BIT(PERF_CSTATE_PKG_C6_RES) |
501 BIT(PERF_CSTATE_PKG_C7_RES) |
502 BIT(PERF_CSTATE_PKG_C8_RES) |
503 BIT(PERF_CSTATE_PKG_C9_RES) |
504 BIT(PERF_CSTATE_PKG_C10_RES),
505};
506
507static const struct cstate_model slm_cstates __initconst = {
508 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
509 BIT(PERF_CSTATE_CORE_C6_RES),
510
511 .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES),
512 .quirks = SLM_PKG_C6_USE_C7_MSR,
513};
514
515
516static const struct cstate_model knl_cstates __initconst = {
517 .core_events = BIT(PERF_CSTATE_CORE_C6_RES),
518
519 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
520 BIT(PERF_CSTATE_PKG_C3_RES) |
521 BIT(PERF_CSTATE_PKG_C6_RES),
522 .quirks = KNL_CORE_C6_MSR,
523};
524
525
526static const struct cstate_model glm_cstates __initconst = {
527 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) |
528 BIT(PERF_CSTATE_CORE_C3_RES) |
529 BIT(PERF_CSTATE_CORE_C6_RES),
530
531 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |
532 BIT(PERF_CSTATE_PKG_C3_RES) |
533 BIT(PERF_CSTATE_PKG_C6_RES) |
534 BIT(PERF_CSTATE_PKG_C10_RES),
535};
536
537
538#define X86_CSTATES_MODEL(model, states) \
539 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
540
541static const struct x86_cpu_id intel_cstates_match[] __initconst = {
542 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM, nhm_cstates),
543 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EP, nhm_cstates),
544 X86_CSTATES_MODEL(INTEL_FAM6_NEHALEM_EX, nhm_cstates),
545
546 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE, nhm_cstates),
547 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EP, nhm_cstates),
548 X86_CSTATES_MODEL(INTEL_FAM6_WESTMERE_EX, nhm_cstates),
549
550 X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE, snb_cstates),
551 X86_CSTATES_MODEL(INTEL_FAM6_SANDYBRIDGE_X, snb_cstates),
552
553 X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE, snb_cstates),
554 X86_CSTATES_MODEL(INTEL_FAM6_IVYBRIDGE_X, snb_cstates),
555
556 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_CORE, snb_cstates),
557 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_X, snb_cstates),
558 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_GT3E, snb_cstates),
559
560 X86_CSTATES_MODEL(INTEL_FAM6_HASWELL_ULT, hswult_cstates),
561
562 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT1, slm_cstates),
563 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_SILVERMONT2, slm_cstates),
564 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_AIRMONT, slm_cstates),
565
566 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_CORE, snb_cstates),
567 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_XEON_D, snb_cstates),
568 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_GT3E, snb_cstates),
569 X86_CSTATES_MODEL(INTEL_FAM6_BROADWELL_X, snb_cstates),
570
571 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_MOBILE, snb_cstates),
572 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_DESKTOP, snb_cstates),
573 X86_CSTATES_MODEL(INTEL_FAM6_SKYLAKE_X, snb_cstates),
574
575 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_MOBILE, snb_cstates),
576 X86_CSTATES_MODEL(INTEL_FAM6_KABYLAKE_DESKTOP, snb_cstates),
577
578 X86_CSTATES_MODEL(INTEL_FAM6_CANNONLAKE_MOBILE, cnl_cstates),
579
580 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNL, knl_cstates),
581 X86_CSTATES_MODEL(INTEL_FAM6_XEON_PHI_KNM, knl_cstates),
582
583 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates),
584 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_DENVERTON, glm_cstates),
585
586 X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GEMINI_LAKE, glm_cstates),
587 { },
588};
589MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
590
591
592
593
594
595static bool __init cstate_probe_msr(const unsigned long evmsk, int max,
596 struct perf_cstate_msr *msr,
597 struct attribute **attrs)
598{
599 bool found = false;
600 unsigned int bit;
601 u64 val;
602
603 for (bit = 0; bit < max; bit++) {
604 if (test_bit(bit, &evmsk) && !rdmsrl_safe(msr[bit].msr, &val)) {
605 *attrs++ = &msr[bit].attr->attr.attr;
606 found = true;
607 } else {
608 msr[bit].attr = NULL;
609 }
610 }
611 *attrs = NULL;
612
613 return found;
614}
615
616static int __init cstate_probe(const struct cstate_model *cm)
617{
618
619 if (cm->quirks & SLM_PKG_C6_USE_C7_MSR)
620 pkg_msr[PERF_CSTATE_PKG_C6_RES].msr = MSR_PKG_C7_RESIDENCY;
621
622
623 if (cm->quirks & KNL_CORE_C6_MSR)
624 pkg_msr[PERF_CSTATE_CORE_C6_RES].msr = MSR_KNL_CORE_C6_RESIDENCY;
625
626
627 has_cstate_core = cstate_probe_msr(cm->core_events,
628 PERF_CSTATE_CORE_EVENT_MAX,
629 core_msr, core_events_attrs);
630
631 has_cstate_pkg = cstate_probe_msr(cm->pkg_events,
632 PERF_CSTATE_PKG_EVENT_MAX,
633 pkg_msr, pkg_events_attrs);
634
635 return (has_cstate_core || has_cstate_pkg) ? 0 : -ENODEV;
636}
637
638static inline void cstate_cleanup(void)
639{
640 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_ONLINE);
641 cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_CSTATE_STARTING);
642
643 if (has_cstate_core)
644 perf_pmu_unregister(&cstate_core_pmu);
645
646 if (has_cstate_pkg)
647 perf_pmu_unregister(&cstate_pkg_pmu);
648}
649
650static int __init cstate_init(void)
651{
652 int err;
653
654 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_STARTING,
655 "perf/x86/cstate:starting", cstate_cpu_init, NULL);
656 cpuhp_setup_state(CPUHP_AP_PERF_X86_CSTATE_ONLINE,
657 "perf/x86/cstate:online", NULL, cstate_cpu_exit);
658
659 if (has_cstate_core) {
660 err = perf_pmu_register(&cstate_core_pmu, cstate_core_pmu.name, -1);
661 if (err) {
662 has_cstate_core = false;
663 pr_info("Failed to register cstate core pmu\n");
664 cstate_cleanup();
665 return err;
666 }
667 }
668
669 if (has_cstate_pkg) {
670 err = perf_pmu_register(&cstate_pkg_pmu, cstate_pkg_pmu.name, -1);
671 if (err) {
672 has_cstate_pkg = false;
673 pr_info("Failed to register cstate pkg pmu\n");
674 cstate_cleanup();
675 return err;
676 }
677 }
678 return 0;
679}
680
681static int __init cstate_pmu_init(void)
682{
683 const struct x86_cpu_id *id;
684 int err;
685
686 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
687 return -ENODEV;
688
689 id = x86_match_cpu(intel_cstates_match);
690 if (!id)
691 return -ENODEV;
692
693 err = cstate_probe((const struct cstate_model *) id->driver_data);
694 if (err)
695 return err;
696
697 return cstate_init();
698}
699module_init(cstate_pmu_init);
700
701static void __exit cstate_pmu_exit(void)
702{
703 cstate_cleanup();
704}
705module_exit(cstate_pmu_exit);
706