1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _ASM_X86_MSR_INDEX_H 3#define _ASM_X86_MSR_INDEX_H 4 5/* 6 * CPU model specific register (MSR) numbers. 7 * 8 * Do not add new entries to this file unless the definitions are shared 9 * between multiple compilation units. 10 */ 11 12/* x86-64 specific MSRs */ 13#define MSR_EFER 0xc0000080 /* extended feature register */ 14#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */ 15#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */ 16#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */ 17#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */ 18#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */ 19#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */ 20#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */ 21#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */ 22 23/* EFER bits: */ 24#define _EFER_SCE 0 /* SYSCALL/SYSRET */ 25#define _EFER_LME 8 /* Long mode enable */ 26#define _EFER_LMA 10 /* Long mode active (read-only) */ 27#define _EFER_NX 11 /* No execute enable */ 28#define _EFER_SVME 12 /* Enable virtualization */ 29#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ 30#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ 31 32#define EFER_SCE (1<<_EFER_SCE) 33#define EFER_LME (1<<_EFER_LME) 34#define EFER_LMA (1<<_EFER_LMA) 35#define EFER_NX (1<<_EFER_NX) 36#define EFER_SVME (1<<_EFER_SVME) 37#define EFER_LMSLE (1<<_EFER_LMSLE) 38#define EFER_FFXSR (1<<_EFER_FFXSR) 39 40/* Intel MSRs. Some also available on other CPUs */ 41 42#define MSR_IA32_SPEC_CTRL 0x00000048 /* Speculation Control */ 43#define SPEC_CTRL_IBRS (1 << 0) /* Indirect Branch Restricted Speculation */ 44#define SPEC_CTRL_STIBP (1 << 1) /* Single Thread Indirect Branch Predictors */ 45#define SPEC_CTRL_SSBD_SHIFT 2 /* Speculative Store Bypass Disable bit */ 46#define SPEC_CTRL_SSBD (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */ 47 48#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ 49#define PRED_CMD_IBPB (1 << 0) /* Indirect Branch Prediction Barrier */ 50 51#define MSR_PPIN_CTL 0x0000004e 52#define MSR_PPIN 0x0000004f 53 54#define MSR_IA32_PERFCTR0 0x000000c1 55#define MSR_IA32_PERFCTR1 0x000000c2 56#define MSR_FSB_FREQ 0x000000cd 57#define MSR_PLATFORM_INFO 0x000000ce 58#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT 31 59#define MSR_PLATFORM_INFO_CPUID_FAULT BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT) 60 61#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2 62#define NHM_C3_AUTO_DEMOTE (1UL << 25) 63#define NHM_C1_AUTO_DEMOTE (1UL << 26) 64#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) 65#define SNB_C3_AUTO_UNDEMOTE (1UL << 27) 66#define SNB_C1_AUTO_UNDEMOTE (1UL << 28) 67 68#define MSR_MTRRcap 0x000000fe 69 70#define MSR_IA32_ARCH_CAPABILITIES 0x0000010a 71#define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ 72#define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ 73#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */ 74#define ARCH_CAP_SSB_NO (1 << 4) /* 75 * Not susceptible to Speculative Store Bypass 76 * attack, so no Speculative Store Bypass 77 * control required. 78 */ 79 80#define MSR_IA32_FLUSH_CMD 0x0000010b 81#define L1D_FLUSH (1 << 0) /* 82 * Writeback and invalidate the 83 * L1 data cache. 84 */ 85 86#define MSR_IA32_BBL_CR_CTL 0x00000119 87#define MSR_IA32_BBL_CR_CTL3 0x0000011e 88 89#define MSR_IA32_SYSENTER_CS 0x00000174 90#define MSR_IA32_SYSENTER_ESP 0x00000175 91#define MSR_IA32_SYSENTER_EIP 0x00000176 92 93#define MSR_IA32_MCG_CAP 0x00000179 94#define MSR_IA32_MCG_STATUS 0x0000017a 95#define MSR_IA32_MCG_CTL 0x0000017b 96#define MSR_IA32_MCG_EXT_CTL 0x000004d0 97 98#define MSR_OFFCORE_RSP_0 0x000001a6 99#define MSR_OFFCORE_RSP_1 0x000001a7 100#define MSR_TURBO_RATIO_LIMIT 0x000001ad 101#define MSR_TURBO_RATIO_LIMIT1 0x000001ae 102#define MSR_TURBO_RATIO_LIMIT2 0x000001af 103 104#define MSR_LBR_SELECT 0x000001c8 105#define MSR_LBR_TOS 0x000001c9 106#define MSR_LBR_NHM_FROM 0x00000680 107#define MSR_LBR_NHM_TO 0x000006c0 108#define MSR_LBR_CORE_FROM 0x00000040 109#define MSR_LBR_CORE_TO 0x00000060 110 111#define MSR_LBR_INFO_0 0x00000dc0 /* ... 0xddf for _31 */ 112#define LBR_INFO_MISPRED BIT_ULL(63) 113#define LBR_INFO_IN_TX BIT_ULL(62) 114#define LBR_INFO_ABORT BIT_ULL(61) 115#define LBR_INFO_CYCLES 0xffff 116 117#define MSR_IA32_PEBS_ENABLE 0x000003f1 118#define MSR_IA32_DS_AREA 0x00000600 119#define MSR_IA32_PERF_CAPABILITIES 0x00000345 120#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 121 122#define MSR_IA32_RTIT_CTL 0x00000570 123#define MSR_IA32_RTIT_STATUS 0x00000571 124#define MSR_IA32_RTIT_ADDR0_A 0x00000580 125#define MSR_IA32_RTIT_ADDR0_B 0x00000581 126#define MSR_IA32_RTIT_ADDR1_A 0x00000582 127#define MSR_IA32_RTIT_ADDR1_B 0x00000583 128#define MSR_IA32_RTIT_ADDR2_A 0x00000584 129#define MSR_IA32_RTIT_ADDR2_B 0x00000585 130#define MSR_IA32_RTIT_ADDR3_A 0x00000586 131#define MSR_IA32_RTIT_ADDR3_B 0x00000587 132#define MSR_IA32_RTIT_CR3_MATCH 0x00000572 133#define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560 134#define MSR_IA32_RTIT_OUTPUT_MASK 0x00000561 135 136#define MSR_MTRRfix64K_00000 0x00000250 137#define MSR_MTRRfix16K_80000 0x00000258 138#define MSR_MTRRfix16K_A0000 0x00000259 139#define MSR_MTRRfix4K_C0000 0x00000268 140#define MSR_MTRRfix4K_C8000 0x00000269 141#define MSR_MTRRfix4K_D0000 0x0000026a 142#define MSR_MTRRfix4K_D8000 0x0000026b 143#define MSR_MTRRfix4K_E0000 0x0000026c 144#define MSR_MTRRfix4K_E8000 0x0000026d 145#define MSR_MTRRfix4K_F0000 0x0000026e 146#define MSR_MTRRfix4K_F8000 0x0000026f 147#define MSR_MTRRdefType 0x000002ff 148 149#define MSR_IA32_CR_PAT 0x00000277 150 151#define MSR_IA32_DEBUGCTLMSR 0x000001d9 152#define MSR_IA32_LASTBRANCHFROMIP 0x000001db 153#define MSR_IA32_LASTBRANCHTOIP 0x000001dc 154#define MSR_IA32_LASTINTFROMIP 0x000001dd 155#define MSR_IA32_LASTINTTOIP 0x000001de 156 157/* DEBUGCTLMSR bits (others vary by model): */ 158#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ 159#define DEBUGCTLMSR_BTF_SHIFT 1 160#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ 161#define DEBUGCTLMSR_TR (1UL << 6) 162#define DEBUGCTLMSR_BTS (1UL << 7) 163#define DEBUGCTLMSR_BTINT (1UL << 8) 164#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9) 165#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) 166#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) 167#define DEBUGCTLMSR_FREEZE_IN_SMM_BIT 14 168#define DEBUGCTLMSR_FREEZE_IN_SMM (1UL << DEBUGCTLMSR_FREEZE_IN_SMM_BIT) 169 170#define MSR_PEBS_FRONTEND 0x000003f7 171 172#define MSR_IA32_POWER_CTL 0x000001fc 173 174#define MSR_IA32_MC0_CTL 0x00000400 175#define MSR_IA32_MC0_STATUS 0x00000401 176#define MSR_IA32_MC0_ADDR 0x00000402 177#define MSR_IA32_MC0_MISC 0x00000403 178 179/* C-state Residency Counters */ 180#define MSR_PKG_C3_RESIDENCY 0x000003f8 181#define MSR_PKG_C6_RESIDENCY 0x000003f9 182#define MSR_ATOM_PKG_C6_RESIDENCY 0x000003fa 183#define MSR_PKG_C7_RESIDENCY 0x000003fa 184#define MSR_CORE_C3_RESIDENCY 0x000003fc 185#define MSR_CORE_C6_RESIDENCY 0x000003fd 186#define MSR_CORE_C7_RESIDENCY 0x000003fe 187#define MSR_KNL_CORE_C6_RESIDENCY 0x000003ff 188#define MSR_PKG_C2_RESIDENCY 0x0000060d 189#define MSR_PKG_C8_RESIDENCY 0x00000630 190#define MSR_PKG_C9_RESIDENCY 0x00000631 191#define MSR_PKG_C10_RESIDENCY 0x00000632 192 193/* Interrupt Response Limit */ 194#define MSR_PKGC3_IRTL 0x0000060a 195#define MSR_PKGC6_IRTL 0x0000060b 196#define MSR_PKGC7_IRTL 0x0000060c 197#define MSR_PKGC8_IRTL 0x00000633 198#define MSR_PKGC9_IRTL 0x00000634 199#define MSR_PKGC10_IRTL 0x00000635 200 201/* Run Time Average Power Limiting (RAPL) Interface */ 202 203#define MSR_RAPL_POWER_UNIT 0x00000606 204 205#define MSR_PKG_POWER_LIMIT 0x00000610 206#define MSR_PKG_ENERGY_STATUS 0x00000611 207#define MSR_PKG_PERF_STATUS 0x00000613 208#define MSR_PKG_POWER_INFO 0x00000614 209 210#define MSR_DRAM_POWER_LIMIT 0x00000618 211#define MSR_DRAM_ENERGY_STATUS 0x00000619 212#define MSR_DRAM_PERF_STATUS 0x0000061b 213#define MSR_DRAM_POWER_INFO 0x0000061c 214 215#define MSR_PP0_POWER_LIMIT 0x00000638 216#define MSR_PP0_ENERGY_STATUS 0x00000639 217#define MSR_PP0_POLICY 0x0000063a 218#define MSR_PP0_PERF_STATUS 0x0000063b 219 220#define MSR_PP1_POWER_LIMIT 0x00000640 221#define MSR_PP1_ENERGY_STATUS 0x00000641 222#define MSR_PP1_POLICY 0x00000642 223 224/* Config TDP MSRs */ 225#define MSR_CONFIG_TDP_NOMINAL 0x00000648 226#define MSR_CONFIG_TDP_LEVEL_1 0x00000649 227#define MSR_CONFIG_TDP_LEVEL_2 0x0000064A 228#define MSR_CONFIG_TDP_CONTROL 0x0000064B 229#define MSR_TURBO_ACTIVATION_RATIO 0x0000064C 230 231#define MSR_PLATFORM_ENERGY_STATUS 0x0000064D 232 233#define MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 234#define MSR_PKG_ANY_CORE_C0_RES 0x00000659 235#define MSR_PKG_ANY_GFXE_C0_RES 0x0000065A 236#define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B 237 238#define MSR_CORE_C1_RES 0x00000660 239#define MSR_MODULE_C6_RES_MS 0x00000664 240 241#define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668 242#define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669 243 244#define MSR_ATOM_CORE_RATIOS 0x0000066a 245#define MSR_ATOM_CORE_VIDS 0x0000066b 246#define MSR_ATOM_CORE_TURBO_RATIOS 0x0000066c 247#define MSR_ATOM_CORE_TURBO_VIDS 0x0000066d 248 249 250#define MSR_CORE_PERF_LIMIT_REASONS 0x00000690 251#define MSR_GFX_PERF_LIMIT_REASONS 0x000006B0 252#define MSR_RING_PERF_LIMIT_REASONS 0x000006B1 253 254/* Hardware P state interface */ 255#define MSR_PPERF 0x0000064e 256#define MSR_PERF_LIMIT_REASONS 0x0000064f 257#define MSR_PM_ENABLE 0x00000770 258#define MSR_HWP_CAPABILITIES 0x00000771 259#define MSR_HWP_REQUEST_PKG 0x00000772 260#define MSR_HWP_INTERRUPT 0x00000773 261#define MSR_HWP_REQUEST 0x00000774 262#define MSR_HWP_STATUS 0x00000777 263 264/* CPUID.6.EAX */ 265#define HWP_BASE_BIT (1<<7) 266#define HWP_NOTIFICATIONS_BIT (1<<8) 267#define HWP_ACTIVITY_WINDOW_BIT (1<<9) 268#define HWP_ENERGY_PERF_PREFERENCE_BIT (1<<10) 269#define HWP_PACKAGE_LEVEL_REQUEST_BIT (1<<11) 270 271/* IA32_HWP_CAPABILITIES */ 272#define HWP_HIGHEST_PERF(x) (((x) >> 0) & 0xff) 273#define HWP_GUARANTEED_PERF(x) (((x) >> 8) & 0xff) 274#define HWP_MOSTEFFICIENT_PERF(x) (((x) >> 16) & 0xff) 275#define HWP_LOWEST_PERF(x) (((x) >> 24) & 0xff) 276 277/* IA32_HWP_REQUEST */ 278#define HWP_MIN_PERF(x) (x & 0xff) 279#define HWP_MAX_PERF(x) ((x & 0xff) << 8) 280#define HWP_DESIRED_PERF(x) ((x & 0xff) << 16) 281#define HWP_ENERGY_PERF_PREFERENCE(x) (((unsigned long long) x & 0xff) << 24) 282#define HWP_EPP_PERFORMANCE 0x00 283#define HWP_EPP_BALANCE_PERFORMANCE 0x80 284#define HWP_EPP_BALANCE_POWERSAVE 0xC0 285#define HWP_EPP_POWERSAVE 0xFF 286#define HWP_ACTIVITY_WINDOW(x) ((unsigned long long)(x & 0xff3) << 32) 287#define HWP_PACKAGE_CONTROL(x) ((unsigned long long)(x & 0x1) << 42) 288 289/* IA32_HWP_STATUS */ 290#define HWP_GUARANTEED_CHANGE(x) (x & 0x1) 291#define HWP_EXCURSION_TO_MINIMUM(x) (x & 0x4) 292 293/* IA32_HWP_INTERRUPT */ 294#define HWP_CHANGE_TO_GUARANTEED_INT(x) (x & 0x1) 295#define HWP_EXCURSION_TO_MINIMUM_INT(x) (x & 0x2) 296 297#define MSR_AMD64_MC0_MASK 0xc0010044 298 299#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) 300#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x)) 301#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x)) 302#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x)) 303 304#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x)) 305 306/* These are consecutive and not in the normal 4er MCE bank block */ 307#define MSR_IA32_MC0_CTL2 0x00000280 308#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x)) 309 310#define MSR_P6_PERFCTR0 0x000000c1 311#define MSR_P6_PERFCTR1 0x000000c2 312#define MSR_P6_EVNTSEL0 0x00000186 313#define MSR_P6_EVNTSEL1 0x00000187 314 315#define MSR_KNC_PERFCTR0 0x00000020 316#define MSR_KNC_PERFCTR1 0x00000021 317#define MSR_KNC_EVNTSEL0 0x00000028 318#define MSR_KNC_EVNTSEL1 0x00000029 319 320/* Alternative perfctr range with full access. */ 321#define MSR_IA32_PMC0 0x000004c1 322 323/* AMD64 MSRs. Not complete. See the architecture manual for a more 324 complete list. */ 325 326#define MSR_AMD64_PATCH_LEVEL 0x0000008b 327#define MSR_AMD64_TSC_RATIO 0xc0000104 328#define MSR_AMD64_NB_CFG 0xc001001f 329#define MSR_AMD64_PATCH_LOADER 0xc0010020 330#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 331#define MSR_AMD64_OSVW_STATUS 0xc0010141 332#define MSR_AMD64_LS_CFG 0xc0011020 333#define MSR_AMD64_DC_CFG 0xc0011022 334#define MSR_AMD64_BU_CFG2 0xc001102a 335#define MSR_AMD64_IBSFETCHCTL 0xc0011030 336#define MSR_AMD64_IBSFETCHLINAD 0xc0011031 337#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 338#define MSR_AMD64_IBSFETCH_REG_COUNT 3 339#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) 340#define MSR_AMD64_IBSOPCTL 0xc0011033 341#define MSR_AMD64_IBSOPRIP 0xc0011034 342#define MSR_AMD64_IBSOPDATA 0xc0011035 343#define MSR_AMD64_IBSOPDATA2 0xc0011036 344#define MSR_AMD64_IBSOPDATA3 0xc0011037 345#define MSR_AMD64_IBSDCLINAD 0xc0011038 346#define MSR_AMD64_IBSDCPHYSAD 0xc0011039 347#define MSR_AMD64_IBSOP_REG_COUNT 7 348#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) 349#define MSR_AMD64_IBSCTL 0xc001103a 350#define MSR_AMD64_IBSBRTARGET 0xc001103b 351#define MSR_AMD64_IBSOPDATA4 0xc001103d 352#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ 353#define MSR_AMD64_SEV 0xc0010131 354#define MSR_AMD64_SEV_ENABLED_BIT 0 355#define MSR_AMD64_SEV_ENABLED BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT) 356 357#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f 358 359/* Fam 17h MSRs */ 360#define MSR_F17H_IRPERF 0xc00000e9 361 362/* Fam 16h MSRs */ 363#define MSR_F16H_L2I_PERF_CTL 0xc0010230 364#define MSR_F16H_L2I_PERF_CTR 0xc0010231 365#define MSR_F16H_DR1_ADDR_MASK 0xc0011019 366#define MSR_F16H_DR2_ADDR_MASK 0xc001101a 367#define MSR_F16H_DR3_ADDR_MASK 0xc001101b 368#define MSR_F16H_DR0_ADDR_MASK 0xc0011027 369 370/* Fam 15h MSRs */ 371#define MSR_F15H_PERF_CTL 0xc0010200 372#define MSR_F15H_PERF_CTL0 MSR_F15H_PERF_CTL 373#define MSR_F15H_PERF_CTL1 (MSR_F15H_PERF_CTL + 2) 374#define MSR_F15H_PERF_CTL2 (MSR_F15H_PERF_CTL + 4) 375#define MSR_F15H_PERF_CTL3 (MSR_F15H_PERF_CTL + 6) 376#define MSR_F15H_PERF_CTL4 (MSR_F15H_PERF_CTL + 8) 377#define MSR_F15H_PERF_CTL5 (MSR_F15H_PERF_CTL + 10) 378 379#define MSR_F15H_PERF_CTR 0xc0010201 380#define MSR_F15H_PERF_CTR0 MSR_F15H_PERF_CTR 381#define MSR_F15H_PERF_CTR1 (MSR_F15H_PERF_CTR + 2) 382#define MSR_F15H_PERF_CTR2 (MSR_F15H_PERF_CTR + 4) 383#define MSR_F15H_PERF_CTR3 (MSR_F15H_PERF_CTR + 6) 384#define MSR_F15H_PERF_CTR4 (MSR_F15H_PERF_CTR + 8) 385#define MSR_F15H_PERF_CTR5 (MSR_F15H_PERF_CTR + 10) 386 387#define MSR_F15H_NB_PERF_CTL 0xc0010240 388#define MSR_F15H_NB_PERF_CTR 0xc0010241 389#define MSR_F15H_PTSC 0xc0010280 390#define MSR_F15H_IC_CFG 0xc0011021 391 392/* Fam 10h MSRs */ 393#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 394#define FAM10H_MMIO_CONF_ENABLE (1<<0) 395#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf 396#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2 397#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL 398#define FAM10H_MMIO_CONF_BASE_SHIFT 20 399#define MSR_FAM10H_NODE_ID 0xc001100c 400#define MSR_F10H_DECFG 0xc0011029 401#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT 1 402#define MSR_F10H_DECFG_LFENCE_SERIALIZE BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT) 403 404/* K8 MSRs */ 405#define MSR_K8_TOP_MEM1 0xc001001a 406#define MSR_K8_TOP_MEM2 0xc001001d 407#define MSR_K8_SYSCFG 0xc0010010 408#define MSR_K8_SYSCFG_MEM_ENCRYPT_BIT 23 409#define MSR_K8_SYSCFG_MEM_ENCRYPT BIT_ULL(MSR_K8_SYSCFG_MEM_ENCRYPT_BIT) 410#define MSR_K8_INT_PENDING_MSG 0xc0010055 411/* C1E active bits in int pending message */ 412#define K8_INTP_C1E_ACTIVE_MASK 0x18000000 413#define MSR_K8_TSEG_ADDR 0xc0010112 414#define MSR_K8_TSEG_MASK 0xc0010113 415#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 416#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 417#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */ 418 419/* K7 MSRs */ 420#define MSR_K7_EVNTSEL0 0xc0010000 421#define MSR_K7_PERFCTR0 0xc0010004 422#define MSR_K7_EVNTSEL1 0xc0010001 423#define MSR_K7_PERFCTR1 0xc0010005 424#define MSR_K7_EVNTSEL2 0xc0010002 425#define MSR_K7_PERFCTR2 0xc0010006 426#define MSR_K7_EVNTSEL3 0xc0010003 427#define MSR_K7_PERFCTR3 0xc0010007 428#define MSR_K7_CLK_CTL 0xc001001b 429#define MSR_K7_HWCR 0xc0010015 430#define MSR_K7_HWCR_SMMLOCK_BIT 0 431#define MSR_K7_HWCR_SMMLOCK BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT) 432#define MSR_K7_FID_VID_CTL 0xc0010041 433#define MSR_K7_FID_VID_STATUS 0xc0010042 434 435/* K6 MSRs */ 436#define MSR_K6_WHCR 0xc0000082 437#define MSR_K6_UWCCR 0xc0000085 438#define MSR_K6_EPMR 0xc0000086 439#define MSR_K6_PSOR 0xc0000087 440#define MSR_K6_PFIR 0xc0000088 441 442/* Centaur-Hauls/IDT defined MSRs. */ 443#define MSR_IDT_FCR1 0x00000107 444#define MSR_IDT_FCR2 0x00000108 445#define MSR_IDT_FCR3 0x00000109 446#define MSR_IDT_FCR4 0x0000010a 447 448#define MSR_IDT_MCR0 0x00000110 449#define MSR_IDT_MCR1 0x00000111 450#define MSR_IDT_MCR2 0x00000112 451#define MSR_IDT_MCR3 0x00000113 452#define MSR_IDT_MCR4 0x00000114 453#define MSR_IDT_MCR5 0x00000115 454#define MSR_IDT_MCR6 0x00000116 455#define MSR_IDT_MCR7 0x00000117 456#define MSR_IDT_MCR_CTRL 0x00000120 457 458/* VIA Cyrix defined MSRs*/ 459#define MSR_VIA_FCR 0x00001107 460#define MSR_VIA_LONGHAUL 0x0000110a 461#define MSR_VIA_RNG 0x0000110b 462#define MSR_VIA_BCR2 0x00001147 463 464/* Transmeta defined MSRs */ 465#define MSR_TMTA_LONGRUN_CTRL 0x80868010 466#define MSR_TMTA_LONGRUN_FLAGS 0x80868011 467#define MSR_TMTA_LRTI_READOUT 0x80868018 468#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a 469 470/* Intel defined MSRs. */ 471#define MSR_IA32_P5_MC_ADDR 0x00000000 472#define MSR_IA32_P5_MC_TYPE 0x00000001 473#define MSR_IA32_TSC 0x00000010 474#define MSR_IA32_PLATFORM_ID 0x00000017 475#define MSR_IA32_EBL_CR_POWERON 0x0000002a 476#define MSR_EBC_FREQUENCY_ID 0x0000002c 477#define MSR_SMI_COUNT 0x00000034 478#define MSR_IA32_FEATURE_CONTROL 0x0000003a 479#define MSR_IA32_TSC_ADJUST 0x0000003b 480#define MSR_IA32_BNDCFGS 0x00000d90 481 482#define MSR_IA32_BNDCFGS_RSVD 0x00000ffc 483 484#define MSR_IA32_XSS 0x00000da0 485 486#define FEATURE_CONTROL_LOCKED (1<<0) 487#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) 488#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2) 489#define FEATURE_CONTROL_LMCE (1<<20) 490 491#define MSR_IA32_APICBASE 0x0000001b 492#define MSR_IA32_APICBASE_BSP (1<<8) 493#define MSR_IA32_APICBASE_ENABLE (1<<11) 494#define MSR_IA32_APICBASE_BASE (0xfffff<<12) 495 496#define MSR_IA32_TSCDEADLINE 0x000006e0 497 498#define MSR_IA32_UCODE_WRITE 0x00000079 499#define MSR_IA32_UCODE_REV 0x0000008b 500 501#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b 502#define MSR_IA32_SMBASE 0x0000009e 503 504#define MSR_IA32_PERF_STATUS 0x00000198 505#define MSR_IA32_PERF_CTL 0x00000199 506#define INTEL_PERF_CTL_MASK 0xffff 507#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 508#define MSR_AMD_PERF_STATUS 0xc0010063 509#define MSR_AMD_PERF_CTL 0xc0010062 510 511#define MSR_IA32_MPERF 0x000000e7 512#define MSR_IA32_APERF 0x000000e8 513 514#define MSR_IA32_THERM_CONTROL 0x0000019a 515#define MSR_IA32_THERM_INTERRUPT 0x0000019b 516 517#define THERM_INT_HIGH_ENABLE (1 << 0) 518#define THERM_INT_LOW_ENABLE (1 << 1) 519#define THERM_INT_PLN_ENABLE (1 << 24) 520 521#define MSR_IA32_THERM_STATUS 0x0000019c 522 523#define THERM_STATUS_PROCHOT (1 << 0) 524#define THERM_STATUS_POWER_LIMIT (1 << 10) 525 526#define MSR_THERM2_CTL 0x0000019d 527 528#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16) 529 530#define MSR_IA32_MISC_ENABLE 0x000001a0 531 532#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 533 534#define MSR_MISC_FEATURE_CONTROL 0x000001a4 535#define MSR_MISC_PWR_MGMT 0x000001aa 536 537#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 538#define ENERGY_PERF_BIAS_PERFORMANCE 0 539#define ENERGY_PERF_BIAS_BALANCE_PERFORMANCE 4 540#define ENERGY_PERF_BIAS_NORMAL 6 541#define ENERGY_PERF_BIAS_BALANCE_POWERSAVE 8 542#define ENERGY_PERF_BIAS_POWERSAVE 15 543 544#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 545 546#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0) 547#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10) 548 549#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2 550 551#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0) 552#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1) 553#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24) 554 555/* Thermal Thresholds Support */ 556#define THERM_INT_THRESHOLD0_ENABLE (1 << 15) 557#define THERM_SHIFT_THRESHOLD0 8 558#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0) 559#define THERM_INT_THRESHOLD1_ENABLE (1 << 23) 560#define THERM_SHIFT_THRESHOLD1 16 561#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1) 562#define THERM_STATUS_THRESHOLD0 (1 << 6) 563#define THERM_LOG_THRESHOLD0 (1 << 7) 564#define THERM_STATUS_THRESHOLD1 (1 << 8) 565#define THERM_LOG_THRESHOLD1 (1 << 9) 566 567/* MISC_ENABLE bits: architectural */ 568#define MSR_IA32_MISC_ENABLE_FAST_STRING_BIT 0 569#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) 570#define MSR_IA32_MISC_ENABLE_TCC_BIT 1 571#define MSR_IA32_MISC_ENABLE_TCC (1ULL << MSR_IA32_MISC_ENABLE_TCC_BIT) 572#define MSR_IA32_MISC_ENABLE_EMON_BIT 7 573#define MSR_IA32_MISC_ENABLE_EMON (1ULL << MSR_IA32_MISC_ENABLE_EMON_BIT) 574#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT 11 575#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_BTS_UNAVAIL_BIT) 576#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT 12 577#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL_BIT) 578#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT 16 579#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP_BIT) 580#define MSR_IA32_MISC_ENABLE_MWAIT_BIT 18 581#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << MSR_IA32_MISC_ENABLE_MWAIT_BIT) 582#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT 22 583#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) 584#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT 23 585#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XTPR_DISABLE_BIT) 586#define MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT 34 587#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_XD_DISABLE_BIT) 588 589/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */ 590#define MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT 2 591#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << MSR_IA32_MISC_ENABLE_X87_COMPAT_BIT) 592#define MSR_IA32_MISC_ENABLE_TM1_BIT 3 593#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << MSR_IA32_MISC_ENABLE_TM1_BIT) 594#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT 4 595#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE_BIT) 596#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT 6 597#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE_BIT) 598#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT 8 599#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK_BIT) 600#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT 9 601#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) 602#define MSR_IA32_MISC_ENABLE_FERR_BIT 10 603#define MSR_IA32_MISC_ENABLE_FERR (1ULL << MSR_IA32_MISC_ENABLE_FERR_BIT) 604#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT 10 605#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX_BIT) 606#define MSR_IA32_MISC_ENABLE_TM2_BIT 13 607#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << MSR_IA32_MISC_ENABLE_TM2_BIT) 608#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT 19 609#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE_BIT) 610#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT 20 611#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK_BIT) 612#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT 24 613#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << MSR_IA32_MISC_ENABLE_L1D_CONTEXT_BIT) 614#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT 37 615#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE_BIT) 616#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT 38 617#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_TURBO_DISABLE_BIT) 618#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 619#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) 620 621/* MISC_FEATURES_ENABLES non-architectural features */ 622#define MSR_MISC_FEATURES_ENABLES 0x00000140 623 624#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT 0 625#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT) 626#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT 1 627 628#define MSR_IA32_TSC_DEADLINE 0x000006E0 629 630/* P4/Xeon+ specific */ 631#define MSR_IA32_MCG_EAX 0x00000180 632#define MSR_IA32_MCG_EBX 0x00000181 633#define MSR_IA32_MCG_ECX 0x00000182 634#define MSR_IA32_MCG_EDX 0x00000183 635#define MSR_IA32_MCG_ESI 0x00000184 636#define MSR_IA32_MCG_EDI 0x00000185 637#define MSR_IA32_MCG_EBP 0x00000186 638#define MSR_IA32_MCG_ESP 0x00000187 639#define MSR_IA32_MCG_EFLAGS 0x00000188 640#define MSR_IA32_MCG_EIP 0x00000189 641#define MSR_IA32_MCG_RESERVED 0x0000018a 642 643/* Pentium IV performance counter MSRs */ 644#define MSR_P4_BPU_PERFCTR0 0x00000300 645#define MSR_P4_BPU_PERFCTR1 0x00000301 646#define MSR_P4_BPU_PERFCTR2 0x00000302 647#define MSR_P4_BPU_PERFCTR3 0x00000303 648#define MSR_P4_MS_PERFCTR0 0x00000304 649#define MSR_P4_MS_PERFCTR1 0x00000305 650#define MSR_P4_MS_PERFCTR2 0x00000306 651#define MSR_P4_MS_PERFCTR3 0x00000307 652#define MSR_P4_FLAME_PERFCTR0 0x00000308 653#define MSR_P4_FLAME_PERFCTR1 0x00000309 654#define MSR_P4_FLAME_PERFCTR2 0x0000030a 655#define MSR_P4_FLAME_PERFCTR3 0x0000030b 656#define MSR_P4_IQ_PERFCTR0 0x0000030c 657#define MSR_P4_IQ_PERFCTR1 0x0000030d 658#define MSR_P4_IQ_PERFCTR2 0x0000030e 659#define MSR_P4_IQ_PERFCTR3 0x0000030f 660#define MSR_P4_IQ_PERFCTR4 0x00000310 661#define MSR_P4_IQ_PERFCTR5 0x00000311 662#define MSR_P4_BPU_CCCR0 0x00000360 663#define MSR_P4_BPU_CCCR1 0x00000361 664#define MSR_P4_BPU_CCCR2 0x00000362 665#define MSR_P4_BPU_CCCR3 0x00000363 666#define MSR_P4_MS_CCCR0 0x00000364 667#define MSR_P4_MS_CCCR1 0x00000365 668#define MSR_P4_MS_CCCR2 0x00000366 669#define MSR_P4_MS_CCCR3 0x00000367 670#define MSR_P4_FLAME_CCCR0 0x00000368 671#define MSR_P4_FLAME_CCCR1 0x00000369 672#define MSR_P4_FLAME_CCCR2 0x0000036a 673#define MSR_P4_FLAME_CCCR3 0x0000036b 674#define MSR_P4_IQ_CCCR0 0x0000036c 675#define MSR_P4_IQ_CCCR1 0x0000036d 676#define MSR_P4_IQ_CCCR2 0x0000036e 677#define MSR_P4_IQ_CCCR3 0x0000036f 678#define MSR_P4_IQ_CCCR4 0x00000370 679#define MSR_P4_IQ_CCCR5 0x00000371 680#define MSR_P4_ALF_ESCR0 0x000003ca 681#define MSR_P4_ALF_ESCR1 0x000003cb 682#define MSR_P4_BPU_ESCR0 0x000003b2 683#define MSR_P4_BPU_ESCR1 0x000003b3 684#define MSR_P4_BSU_ESCR0 0x000003a0 685#define MSR_P4_BSU_ESCR1 0x000003a1 686#define MSR_P4_CRU_ESCR0 0x000003b8 687#define MSR_P4_CRU_ESCR1 0x000003b9 688#define MSR_P4_CRU_ESCR2 0x000003cc 689#define MSR_P4_CRU_ESCR3 0x000003cd 690#define MSR_P4_CRU_ESCR4 0x000003e0 691#define MSR_P4_CRU_ESCR5 0x000003e1 692#define MSR_P4_DAC_ESCR0 0x000003a8 693#define MSR_P4_DAC_ESCR1 0x000003a9 694#define MSR_P4_FIRM_ESCR0 0x000003a4 695#define MSR_P4_FIRM_ESCR1 0x000003a5 696#define MSR_P4_FLAME_ESCR0 0x000003a6 697#define MSR_P4_FLAME_ESCR1 0x000003a7 698#define MSR_P4_FSB_ESCR0 0x000003a2 699#define MSR_P4_FSB_ESCR1 0x000003a3 700#define MSR_P4_IQ_ESCR0 0x000003ba 701#define MSR_P4_IQ_ESCR1 0x000003bb 702#define MSR_P4_IS_ESCR0 0x000003b4 703#define MSR_P4_IS_ESCR1 0x000003b5 704#define MSR_P4_ITLB_ESCR0 0x000003b6 705#define MSR_P4_ITLB_ESCR1 0x000003b7 706#define MSR_P4_IX_ESCR0 0x000003c8 707#define MSR_P4_IX_ESCR1 0x000003c9 708#define MSR_P4_MOB_ESCR0 0x000003aa 709#define MSR_P4_MOB_ESCR1 0x000003ab 710#define MSR_P4_MS_ESCR0 0x000003c0 711#define MSR_P4_MS_ESCR1 0x000003c1 712#define MSR_P4_PMH_ESCR0 0x000003ac 713#define MSR_P4_PMH_ESCR1 0x000003ad 714#define MSR_P4_RAT_ESCR0 0x000003bc 715#define MSR_P4_RAT_ESCR1 0x000003bd 716#define MSR_P4_SAAT_ESCR0 0x000003ae 717#define MSR_P4_SAAT_ESCR1 0x000003af 718#define MSR_P4_SSU_ESCR0 0x000003be 719#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */ 720 721#define MSR_P4_TBPU_ESCR0 0x000003c2 722#define MSR_P4_TBPU_ESCR1 0x000003c3 723#define MSR_P4_TC_ESCR0 0x000003c4 724#define MSR_P4_TC_ESCR1 0x000003c5 725#define MSR_P4_U2L_ESCR0 0x000003b0 726#define MSR_P4_U2L_ESCR1 0x000003b1 727 728#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2 729 730/* Intel Core-based CPU performance counters */ 731#define MSR_CORE_PERF_FIXED_CTR0 0x00000309 732#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a 733#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b 734#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d 735#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e 736#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f 737#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390 738 739/* Geode defined MSRs */ 740#define MSR_GEODE_BUSCONT_CONF0 0x00001900 741 742/* Intel VT MSRs */ 743#define MSR_IA32_VMX_BASIC 0x00000480 744#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481 745#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482 746#define MSR_IA32_VMX_EXIT_CTLS 0x00000483 747#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484 748#define MSR_IA32_VMX_MISC 0x00000485 749#define MSR_IA32_VMX_CR0_FIXED0 0x00000486 750#define MSR_IA32_VMX_CR0_FIXED1 0x00000487 751#define MSR_IA32_VMX_CR4_FIXED0 0x00000488 752#define MSR_IA32_VMX_CR4_FIXED1 0x00000489 753#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a 754#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b 755#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c 756#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d 757#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e 758#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f 759#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 760#define MSR_IA32_VMX_VMFUNC 0x00000491 761 762/* VMX_BASIC bits and bitmasks */ 763#define VMX_BASIC_VMCS_SIZE_SHIFT 32 764#define VMX_BASIC_TRUE_CTLS (1ULL << 55) 765#define VMX_BASIC_64 0x0001000000000000LLU 766#define VMX_BASIC_MEM_TYPE_SHIFT 50 767#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU 768#define VMX_BASIC_MEM_TYPE_WB 6LLU 769#define VMX_BASIC_INOUT 0x0040000000000000LLU 770 771/* MSR_IA32_VMX_MISC bits */ 772#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) 773#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F 774/* AMD-V MSRs */ 775 776#define MSR_VM_CR 0xc0010114 777#define MSR_VM_IGNNE 0xc0010115 778#define MSR_VM_HSAVE_PA 0xc0010117 779 780#endif /* _ASM_X86_MSR_INDEX_H */ 781