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21#include <linux/clk/zynq.h>
22#include <linux/clk-provider.h>
23#include <linux/slab.h>
24#include <linux/io.h>
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34
35struct zynq_pll {
36 struct clk_hw hw;
37 void __iomem *pll_ctrl;
38 void __iomem *pll_status;
39 spinlock_t *lock;
40 u8 lockbit;
41};
42#define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw)
43
44
45#define PLLCTRL_FBDIV_MASK 0x7f000
46#define PLLCTRL_FBDIV_SHIFT 12
47#define PLLCTRL_BPQUAL_MASK (1 << 3)
48#define PLLCTRL_PWRDWN_MASK 2
49#define PLLCTRL_PWRDWN_SHIFT 1
50#define PLLCTRL_RESET_MASK 1
51#define PLLCTRL_RESET_SHIFT 0
52
53#define PLL_FBDIV_MIN 13
54#define PLL_FBDIV_MAX 66
55
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61
62
63static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
64 unsigned long *prate)
65{
66 u32 fbdiv;
67
68 fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
69 if (fbdiv < PLL_FBDIV_MIN)
70 fbdiv = PLL_FBDIV_MIN;
71 else if (fbdiv > PLL_FBDIV_MAX)
72 fbdiv = PLL_FBDIV_MAX;
73
74 return *prate * fbdiv;
75}
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81
82
83static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
84 unsigned long parent_rate)
85{
86 struct zynq_pll *clk = to_zynq_pll(hw);
87 u32 fbdiv;
88
89
90
91
92
93 fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
94 PLLCTRL_FBDIV_SHIFT;
95
96 return parent_rate * fbdiv;
97}
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106
107static int zynq_pll_is_enabled(struct clk_hw *hw)
108{
109 unsigned long flags = 0;
110 u32 reg;
111 struct zynq_pll *clk = to_zynq_pll(hw);
112
113 spin_lock_irqsave(clk->lock, flags);
114
115 reg = clk_readl(clk->pll_ctrl);
116
117 spin_unlock_irqrestore(clk->lock, flags);
118
119 return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
120}
121
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123
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125
126
127static int zynq_pll_enable(struct clk_hw *hw)
128{
129 unsigned long flags = 0;
130 u32 reg;
131 struct zynq_pll *clk = to_zynq_pll(hw);
132
133 if (zynq_pll_is_enabled(hw))
134 return 0;
135
136 pr_info("PLL: enable\n");
137
138
139 spin_lock_irqsave(clk->lock, flags);
140
141 reg = clk_readl(clk->pll_ctrl);
142 reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
143 clk_writel(reg, clk->pll_ctrl);
144 while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
145 ;
146
147 spin_unlock_irqrestore(clk->lock, flags);
148
149 return 0;
150}
151
152
153
154
155
156
157static void zynq_pll_disable(struct clk_hw *hw)
158{
159 unsigned long flags = 0;
160 u32 reg;
161 struct zynq_pll *clk = to_zynq_pll(hw);
162
163 if (!zynq_pll_is_enabled(hw))
164 return;
165
166 pr_info("PLL: shutdown\n");
167
168
169 spin_lock_irqsave(clk->lock, flags);
170
171 reg = clk_readl(clk->pll_ctrl);
172 reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
173 clk_writel(reg, clk->pll_ctrl);
174
175 spin_unlock_irqrestore(clk->lock, flags);
176}
177
178static const struct clk_ops zynq_pll_ops = {
179 .enable = zynq_pll_enable,
180 .disable = zynq_pll_disable,
181 .is_enabled = zynq_pll_is_enabled,
182 .round_rate = zynq_pll_round_rate,
183 .recalc_rate = zynq_pll_recalc_rate
184};
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195
196struct clk *clk_register_zynq_pll(const char *name, const char *parent,
197 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
198 spinlock_t *lock)
199{
200 struct zynq_pll *pll;
201 struct clk *clk;
202 u32 reg;
203 const char *parent_arr[1] = {parent};
204 unsigned long flags = 0;
205 struct clk_init_data initd = {
206 .name = name,
207 .parent_names = parent_arr,
208 .ops = &zynq_pll_ops,
209 .num_parents = 1,
210 .flags = 0
211 };
212
213 pll = kmalloc(sizeof(*pll), GFP_KERNEL);
214 if (!pll)
215 return ERR_PTR(-ENOMEM);
216
217
218 pll->hw.init = &initd;
219 pll->pll_ctrl = pll_ctrl;
220 pll->pll_status = pll_status;
221 pll->lockbit = lock_index;
222 pll->lock = lock;
223
224 spin_lock_irqsave(pll->lock, flags);
225
226 reg = clk_readl(pll->pll_ctrl);
227 reg &= ~PLLCTRL_BPQUAL_MASK;
228 clk_writel(reg, pll->pll_ctrl);
229
230 spin_unlock_irqrestore(pll->lock, flags);
231
232 clk = clk_register(NULL, &pll->hw);
233 if (WARN_ON(IS_ERR(clk)))
234 goto free_pll;
235
236 return clk;
237
238free_pll:
239 kfree(pll);
240
241 return clk;
242}
243