1/* 2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Zhiyuan Lv <zhiyuan.lv@intel.com> 25 * Zhi Wang <zhi.a.wang@intel.com> 26 * 27 * Contributors: 28 * Min He <min.he@intel.com> 29 * Bing Niu <bing.niu@intel.com> 30 * Ping Gao <ping.a.gao@intel.com> 31 * Tina Zhang <tina.zhang@intel.com> 32 * 33 */ 34 35#ifndef _GVT_EXECLIST_H_ 36#define _GVT_EXECLIST_H_ 37 38struct execlist_ctx_descriptor_format { 39 union { 40 u32 ldw; 41 struct { 42 u32 valid : 1; 43 u32 force_pd_restore : 1; 44 u32 force_restore : 1; 45 u32 addressing_mode : 2; 46 u32 llc_coherency : 1; 47 u32 fault_handling : 2; 48 u32 privilege_access : 1; 49 u32 reserved : 3; 50 u32 lrca : 20; 51 }; 52 }; 53 union { 54 u32 udw; 55 u32 context_id; 56 }; 57}; 58 59struct execlist_status_format { 60 union { 61 u32 ldw; 62 struct { 63 u32 current_execlist_pointer :1; 64 u32 execlist_write_pointer :1; 65 u32 execlist_queue_full :1; 66 u32 execlist_1_valid :1; 67 u32 execlist_0_valid :1; 68 u32 last_ctx_switch_reason :9; 69 u32 current_active_elm_status :2; 70 u32 arbitration_enable :1; 71 u32 execlist_1_active :1; 72 u32 execlist_0_active :1; 73 u32 reserved :13; 74 }; 75 }; 76 union { 77 u32 udw; 78 u32 context_id; 79 }; 80}; 81 82struct execlist_context_status_pointer_format { 83 union { 84 u32 dw; 85 struct { 86 u32 write_ptr :3; 87 u32 reserved :5; 88 u32 read_ptr :3; 89 u32 reserved2 :5; 90 u32 mask :16; 91 }; 92 }; 93}; 94 95struct execlist_context_status_format { 96 union { 97 u32 ldw; 98 struct { 99 u32 idle_to_active :1; 100 u32 preempted :1; 101 u32 element_switch :1; 102 u32 active_to_idle :1; 103 u32 context_complete :1; 104 u32 wait_on_sync_flip :1; 105 u32 wait_on_vblank :1; 106 u32 wait_on_semaphore :1; 107 u32 wait_on_scanline :1; 108 u32 reserved :2; 109 u32 semaphore_wait_mode :1; 110 u32 display_plane :3; 111 u32 lite_restore :1; 112 u32 reserved_2 :16; 113 }; 114 }; 115 union { 116 u32 udw; 117 u32 context_id; 118 }; 119}; 120 121struct execlist_mmio_pair { 122 u32 addr; 123 u32 val; 124}; 125 126/* The first 52 dwords in register state context */ 127struct execlist_ring_context { 128 u32 nop1; 129 u32 lri_cmd_1; 130 struct execlist_mmio_pair ctx_ctrl; 131 struct execlist_mmio_pair ring_header; 132 struct execlist_mmio_pair ring_tail; 133 struct execlist_mmio_pair rb_start; 134 struct execlist_mmio_pair rb_ctrl; 135 struct execlist_mmio_pair bb_cur_head_UDW; 136 struct execlist_mmio_pair bb_cur_head_LDW; 137 struct execlist_mmio_pair bb_state; 138 struct execlist_mmio_pair second_bb_addr_UDW; 139 struct execlist_mmio_pair second_bb_addr_LDW; 140 struct execlist_mmio_pair second_bb_state; 141 struct execlist_mmio_pair bb_per_ctx_ptr; 142 struct execlist_mmio_pair rcs_indirect_ctx; 143 struct execlist_mmio_pair rcs_indirect_ctx_offset; 144 u32 nop2; 145 u32 nop3; 146 u32 nop4; 147 u32 lri_cmd_2; 148 struct execlist_mmio_pair ctx_timestamp; 149 /* 150 * pdps[8]={ pdp3_UDW, pdp3_LDW, pdp2_UDW, pdp2_LDW, 151 * pdp1_UDW, pdp1_LDW, pdp0_UDW, pdp0_LDW} 152 */ 153 struct execlist_mmio_pair pdps[8]; 154}; 155 156struct intel_vgpu_elsp_dwords { 157 u32 data[4]; 158 u32 index; 159}; 160 161struct intel_vgpu_execlist_slot { 162 struct execlist_ctx_descriptor_format ctx[2]; 163 u32 index; 164}; 165 166struct intel_vgpu_execlist { 167 struct intel_vgpu_execlist_slot slot[2]; 168 struct intel_vgpu_execlist_slot *running_slot; 169 struct intel_vgpu_execlist_slot *pending_slot; 170 struct execlist_ctx_descriptor_format *running_context; 171 int ring_id; 172 struct intel_vgpu *vgpu; 173 struct intel_vgpu_elsp_dwords elsp_dwords; 174}; 175 176void intel_vgpu_clean_execlist(struct intel_vgpu *vgpu); 177 178int intel_vgpu_init_execlist(struct intel_vgpu *vgpu); 179 180int intel_vgpu_submit_execlist(struct intel_vgpu *vgpu, int ring_id); 181 182void intel_vgpu_reset_execlist(struct intel_vgpu *vgpu, 183 unsigned long engine_mask); 184 185#endif /*_GVT_EXECLIST_H_*/ 186