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30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
33#include <uapi/drm/i915_drm.h>
34#include <uapi/drm/drm_fourcc.h>
35
36#include <linux/io-mapping.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <linux/backlight.h>
40#include <linux/hash.h>
41#include <linux/intel-iommu.h>
42#include <linux/kref.h>
43#include <linux/mm_types.h>
44#include <linux/perf_event.h>
45#include <linux/pm_qos.h>
46#include <linux/reservation.h>
47#include <linux/shmem_fs.h>
48
49#include <drm/drmP.h>
50#include <drm/intel-gtt.h>
51#include <drm/drm_legacy.h>
52#include <drm/drm_gem.h>
53#include <drm/drm_auth.h>
54#include <drm/drm_cache.h>
55
56#include "i915_params.h"
57#include "i915_reg.h"
58#include "i915_utils.h"
59
60#include "intel_bios.h"
61#include "intel_device_info.h"
62#include "intel_display.h"
63#include "intel_dpll_mgr.h"
64#include "intel_lrc.h"
65#include "intel_opregion.h"
66#include "intel_ringbuffer.h"
67#include "intel_uncore.h"
68#include "intel_wopcm.h"
69#include "intel_uc.h"
70
71#include "i915_gem.h"
72#include "i915_gem_context.h"
73#include "i915_gem_fence_reg.h"
74#include "i915_gem_object.h"
75#include "i915_gem_gtt.h"
76#include "i915_gpu_error.h"
77#include "i915_request.h"
78#include "i915_scheduler.h"
79#include "i915_timeline.h"
80#include "i915_vma.h"
81
82#include "intel_gvt.h"
83
84
85
86
87#define DRIVER_NAME "i915"
88#define DRIVER_DESC "Intel Graphics"
89#define DRIVER_DATE "20180719"
90#define DRIVER_TIMESTAMP 1532015279
91
92
93
94
95
96
97
98
99#define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915_modparams.verbose_state_checks, format)) \
103 DRM_ERROR(format); \
104 unlikely(__ret_warn_on); \
105})
106
107#define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
109
110#if IS_ENABLED(CONFIG_DRM_I915_DEBUG)
111
112bool __i915_inject_load_failure(const char *func, int line);
113#define i915_inject_load_failure() \
114 __i915_inject_load_failure(__func__, __LINE__)
115
116bool i915_error_injected(void);
117
118#else
119
120#define i915_inject_load_failure() false
121#define i915_error_injected() false
122
123#endif
124
125#define i915_load_error(i915, fmt, ...) \
126 __i915_printk(i915, i915_error_injected() ? KERN_DEBUG : KERN_ERR, \
127 fmt, ##__VA_ARGS__)
128
129typedef struct {
130 uint32_t val;
131} uint_fixed_16_16_t;
132
133#define FP_16_16_MAX ({ \
134 uint_fixed_16_16_t fp; \
135 fp.val = UINT_MAX; \
136 fp; \
137})
138
139static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
140{
141 if (val.val == 0)
142 return true;
143 return false;
144}
145
146static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
147{
148 uint_fixed_16_16_t fp;
149
150 WARN_ON(val > U16_MAX);
151
152 fp.val = val << 16;
153 return fp;
154}
155
156static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
157{
158 return DIV_ROUND_UP(fp.val, 1 << 16);
159}
160
161static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
162{
163 return fp.val >> 16;
164}
165
166static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
167 uint_fixed_16_16_t min2)
168{
169 uint_fixed_16_16_t min;
170
171 min.val = min(min1.val, min2.val);
172 return min;
173}
174
175static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
176 uint_fixed_16_16_t max2)
177{
178 uint_fixed_16_16_t max;
179
180 max.val = max(max1.val, max2.val);
181 return max;
182}
183
184static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
185{
186 uint_fixed_16_16_t fp;
187 WARN_ON(val > U32_MAX);
188 fp.val = (uint32_t) val;
189 return fp;
190}
191
192static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
193 uint_fixed_16_16_t d)
194{
195 return DIV_ROUND_UP(val.val, d.val);
196}
197
198static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
199 uint_fixed_16_16_t mul)
200{
201 uint64_t intermediate_val;
202
203 intermediate_val = (uint64_t) val * mul.val;
204 intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
205 WARN_ON(intermediate_val > U32_MAX);
206 return (uint32_t) intermediate_val;
207}
208
209static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
210 uint_fixed_16_16_t mul)
211{
212 uint64_t intermediate_val;
213
214 intermediate_val = (uint64_t) val.val * mul.val;
215 intermediate_val = intermediate_val >> 16;
216 return clamp_u64_to_fixed16(intermediate_val);
217}
218
219static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
220{
221 uint64_t interm_val;
222
223 interm_val = (uint64_t)val << 16;
224 interm_val = DIV_ROUND_UP_ULL(interm_val, d);
225 return clamp_u64_to_fixed16(interm_val);
226}
227
228static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
229 uint_fixed_16_16_t d)
230{
231 uint64_t interm_val;
232
233 interm_val = (uint64_t)val << 16;
234 interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
235 WARN_ON(interm_val > U32_MAX);
236 return (uint32_t) interm_val;
237}
238
239static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
240 uint_fixed_16_16_t mul)
241{
242 uint64_t intermediate_val;
243
244 intermediate_val = (uint64_t) val * mul.val;
245 return clamp_u64_to_fixed16(intermediate_val);
246}
247
248static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
249 uint_fixed_16_16_t add2)
250{
251 uint64_t interm_sum;
252
253 interm_sum = (uint64_t) add1.val + add2.val;
254 return clamp_u64_to_fixed16(interm_sum);
255}
256
257static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
258 uint32_t add2)
259{
260 uint64_t interm_sum;
261 uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
262
263 interm_sum = (uint64_t) add1.val + interm_add2.val;
264 return clamp_u64_to_fixed16(interm_sum);
265}
266
267enum hpd_pin {
268 HPD_NONE = 0,
269 HPD_TV = HPD_NONE,
270 HPD_CRT,
271 HPD_SDVO_B,
272 HPD_SDVO_C,
273 HPD_PORT_A,
274 HPD_PORT_B,
275 HPD_PORT_C,
276 HPD_PORT_D,
277 HPD_PORT_E,
278 HPD_PORT_F,
279 HPD_NUM_PINS
280};
281
282#define for_each_hpd_pin(__pin) \
283 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
284
285#define HPD_STORM_DEFAULT_THRESHOLD 5
286
287struct i915_hotplug {
288 struct work_struct hotplug_work;
289
290 struct {
291 unsigned long last_jiffies;
292 int count;
293 enum {
294 HPD_ENABLED = 0,
295 HPD_DISABLED = 1,
296 HPD_MARK_DISABLED = 2
297 } state;
298 } stats[HPD_NUM_PINS];
299 u32 event_bits;
300 struct delayed_work reenable_work;
301
302 u32 long_port_mask;
303 u32 short_port_mask;
304 struct work_struct dig_port_work;
305
306 struct work_struct poll_init_work;
307 bool poll_enabled;
308
309 unsigned int hpd_storm_threshold;
310
311
312
313
314
315
316
317
318 struct workqueue_struct *dp_wq;
319};
320
321#define I915_GEM_GPU_DOMAINS \
322 (I915_GEM_DOMAIN_RENDER | \
323 I915_GEM_DOMAIN_SAMPLER | \
324 I915_GEM_DOMAIN_COMMAND | \
325 I915_GEM_DOMAIN_INSTRUCTION | \
326 I915_GEM_DOMAIN_VERTEX)
327
328struct drm_i915_private;
329struct i915_mm_struct;
330struct i915_mmu_object;
331
332struct drm_i915_file_private {
333 struct drm_i915_private *dev_priv;
334 struct drm_file *file;
335
336 struct {
337 spinlock_t lock;
338 struct list_head request_list;
339
340
341
342
343
344#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
345 } mm;
346 struct idr context_idr;
347
348 struct intel_rps_client {
349 atomic_t boosts;
350 } rps_client;
351
352 unsigned int bsd_engine;
353
354
355
356
357
358
359
360
361
362#define I915_CLIENT_SCORE_HANG_FAST 1
363#define I915_CLIENT_FAST_HANG_JIFFIES (60 * HZ)
364#define I915_CLIENT_SCORE_CONTEXT_BAN 3
365#define I915_CLIENT_SCORE_BANNED 9
366
367 atomic_t ban_score;
368 unsigned long hang_timestamp;
369};
370
371
372
373
374
375
376
377
378
379
380
381#define DRIVER_MAJOR 1
382#define DRIVER_MINOR 6
383#define DRIVER_PATCHLEVEL 0
384
385struct intel_overlay;
386struct intel_overlay_error_state;
387
388struct sdvo_device_mapping {
389 u8 initialized;
390 u8 dvo_port;
391 u8 slave_addr;
392 u8 dvo_wiring;
393 u8 i2c_pin;
394 u8 ddc_pin;
395};
396
397struct intel_connector;
398struct intel_encoder;
399struct intel_atomic_state;
400struct intel_crtc_state;
401struct intel_initial_plane_config;
402struct intel_crtc;
403struct intel_limit;
404struct dpll;
405struct intel_cdclk_state;
406
407struct drm_i915_display_funcs {
408 void (*get_cdclk)(struct drm_i915_private *dev_priv,
409 struct intel_cdclk_state *cdclk_state);
410 void (*set_cdclk)(struct drm_i915_private *dev_priv,
411 const struct intel_cdclk_state *cdclk_state);
412 int (*get_fifo_size)(struct drm_i915_private *dev_priv,
413 enum i9xx_plane_id i9xx_plane);
414 int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
415 int (*compute_intermediate_wm)(struct drm_device *dev,
416 struct intel_crtc *intel_crtc,
417 struct intel_crtc_state *newstate);
418 void (*initial_watermarks)(struct intel_atomic_state *state,
419 struct intel_crtc_state *cstate);
420 void (*atomic_update_watermarks)(struct intel_atomic_state *state,
421 struct intel_crtc_state *cstate);
422 void (*optimize_watermarks)(struct intel_atomic_state *state,
423 struct intel_crtc_state *cstate);
424 int (*compute_global_watermarks)(struct drm_atomic_state *state);
425 void (*update_wm)(struct intel_crtc *crtc);
426 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
427
428
429 bool (*get_pipe_config)(struct intel_crtc *,
430 struct intel_crtc_state *);
431 void (*get_initial_plane_config)(struct intel_crtc *,
432 struct intel_initial_plane_config *);
433 int (*crtc_compute_clock)(struct intel_crtc *crtc,
434 struct intel_crtc_state *crtc_state);
435 void (*crtc_enable)(struct intel_crtc_state *pipe_config,
436 struct drm_atomic_state *old_state);
437 void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
438 struct drm_atomic_state *old_state);
439 void (*update_crtcs)(struct drm_atomic_state *state);
440 void (*audio_codec_enable)(struct intel_encoder *encoder,
441 const struct intel_crtc_state *crtc_state,
442 const struct drm_connector_state *conn_state);
443 void (*audio_codec_disable)(struct intel_encoder *encoder,
444 const struct intel_crtc_state *old_crtc_state,
445 const struct drm_connector_state *old_conn_state);
446 void (*fdi_link_train)(struct intel_crtc *crtc,
447 const struct intel_crtc_state *crtc_state);
448 void (*init_clock_gating)(struct drm_i915_private *dev_priv);
449 void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
450
451
452
453
454
455
456 void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
457 void (*load_luts)(struct drm_crtc_state *crtc_state);
458};
459
460#define CSR_VERSION(major, minor) ((major) << 16 | (minor))
461#define CSR_VERSION_MAJOR(version) ((version) >> 16)
462#define CSR_VERSION_MINOR(version) ((version) & 0xffff)
463
464struct intel_csr {
465 struct work_struct work;
466 const char *fw_path;
467 uint32_t *dmc_payload;
468 uint32_t dmc_fw_size;
469 uint32_t version;
470 uint32_t mmio_count;
471 i915_reg_t mmioaddr[8];
472 uint32_t mmiodata[8];
473 uint32_t dc_state;
474 uint32_t allowed_dc_mask;
475};
476
477enum i915_cache_level {
478 I915_CACHE_NONE = 0,
479 I915_CACHE_LLC,
480 I915_CACHE_L3_LLC,
481
482
483
484 I915_CACHE_WT,
485};
486
487#define I915_COLOR_UNEVICTABLE (-1)
488
489enum fb_op_origin {
490 ORIGIN_GTT,
491 ORIGIN_CPU,
492 ORIGIN_CS,
493 ORIGIN_FLIP,
494 ORIGIN_DIRTYFB,
495};
496
497struct intel_fbc {
498
499
500 struct mutex lock;
501 unsigned threshold;
502 unsigned int possible_framebuffer_bits;
503 unsigned int busy_bits;
504 unsigned int visible_pipes_mask;
505 struct intel_crtc *crtc;
506
507 struct drm_mm_node compressed_fb;
508 struct drm_mm_node *compressed_llb;
509
510 bool false_color;
511
512 bool enabled;
513 bool active;
514 bool flip_pending;
515
516 bool underrun_detected;
517 struct work_struct underrun_work;
518
519
520
521
522
523
524 struct intel_fbc_state_cache {
525 struct i915_vma *vma;
526 unsigned long flags;
527
528 struct {
529 unsigned int mode_flags;
530 uint32_t hsw_bdw_pixel_rate;
531 } crtc;
532
533 struct {
534 unsigned int rotation;
535 int src_w;
536 int src_h;
537 bool visible;
538
539
540
541
542
543
544 int adjusted_x;
545 int adjusted_y;
546
547 int y;
548 } plane;
549
550 struct {
551 const struct drm_format_info *format;
552 unsigned int stride;
553 } fb;
554 } state_cache;
555
556
557
558
559
560
561
562
563 struct intel_fbc_reg_params {
564 struct i915_vma *vma;
565 unsigned long flags;
566
567 struct {
568 enum pipe pipe;
569 enum i9xx_plane_id i9xx_plane;
570 unsigned int fence_y_offset;
571 } crtc;
572
573 struct {
574 const struct drm_format_info *format;
575 unsigned int stride;
576 } fb;
577
578 int cfb_size;
579 unsigned int gen9_wa_cfb_stride;
580 } params;
581
582 const char *no_fbc_reason;
583};
584
585
586
587
588
589
590enum drrs_refresh_rate_type {
591 DRRS_HIGH_RR,
592 DRRS_LOW_RR,
593 DRRS_MAX_RR,
594};
595
596enum drrs_support_type {
597 DRRS_NOT_SUPPORTED = 0,
598 STATIC_DRRS_SUPPORT = 1,
599 SEAMLESS_DRRS_SUPPORT = 2
600};
601
602struct intel_dp;
603struct i915_drrs {
604 struct mutex mutex;
605 struct delayed_work work;
606 struct intel_dp *dp;
607 unsigned busy_frontbuffer_bits;
608 enum drrs_refresh_rate_type refresh_rate_type;
609 enum drrs_support_type type;
610};
611
612struct i915_psr {
613 struct mutex lock;
614 bool sink_support;
615 struct intel_dp *enabled;
616 bool active;
617 struct work_struct work;
618 unsigned busy_frontbuffer_bits;
619 bool sink_psr2_support;
620 bool link_standby;
621 bool colorimetry_support;
622 bool alpm;
623 bool psr2_enabled;
624 u8 sink_sync_latency;
625 bool debug;
626 ktime_t last_entry_attempt;
627 ktime_t last_exit;
628};
629
630enum intel_pch {
631 PCH_NONE = 0,
632 PCH_IBX,
633 PCH_CPT,
634 PCH_LPT,
635 PCH_SPT,
636 PCH_KBP,
637 PCH_CNP,
638 PCH_ICP,
639 PCH_NOP,
640};
641
642enum intel_sbi_destination {
643 SBI_ICLK,
644 SBI_MPHY,
645};
646
647#define QUIRK_LVDS_SSC_DISABLE (1<<1)
648#define QUIRK_INVERT_BRIGHTNESS (1<<2)
649#define QUIRK_BACKLIGHT_PRESENT (1<<3)
650#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
651#define QUIRK_INCREASE_T12_DELAY (1<<6)
652#define QUIRK_INCREASE_DDI_DISABLED_TIME (1<<7)
653
654struct intel_fbdev;
655struct intel_fbc_work;
656
657struct intel_gmbus {
658 struct i2c_adapter adapter;
659#define GMBUS_FORCE_BIT_RETRY (1U << 31)
660 u32 force_bit;
661 u32 reg0;
662 i915_reg_t gpio_reg;
663 struct i2c_algo_bit_data bit_algo;
664 struct drm_i915_private *dev_priv;
665};
666
667struct i915_suspend_saved_registers {
668 u32 saveDSPARB;
669 u32 saveFBC_CONTROL;
670 u32 saveCACHE_MODE_0;
671 u32 saveMI_ARB_STATE;
672 u32 saveSWF0[16];
673 u32 saveSWF1[16];
674 u32 saveSWF3[3];
675 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
676 u32 savePCH_PORT_HOTPLUG;
677 u16 saveGCDGMBUS;
678};
679
680struct vlv_s0ix_state {
681
682 u32 wr_watermark;
683 u32 gfx_prio_ctrl;
684 u32 arb_mode;
685 u32 gfx_pend_tlb0;
686 u32 gfx_pend_tlb1;
687 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
688 u32 media_max_req_count;
689 u32 gfx_max_req_count;
690 u32 render_hwsp;
691 u32 ecochk;
692 u32 bsd_hwsp;
693 u32 blt_hwsp;
694 u32 tlb_rd_addr;
695
696
697 u32 g3dctl;
698 u32 gsckgctl;
699 u32 mbctl;
700
701
702 u32 ucgctl1;
703 u32 ucgctl3;
704 u32 rcgctl1;
705 u32 rcgctl2;
706 u32 rstctl;
707 u32 misccpctl;
708
709
710 u32 gfxpause;
711 u32 rpdeuhwtc;
712 u32 rpdeuc;
713 u32 ecobus;
714 u32 pwrdwnupctl;
715 u32 rp_down_timeout;
716 u32 rp_deucsw;
717 u32 rcubmabdtmr;
718 u32 rcedata;
719 u32 spare2gh;
720
721
722 u32 gt_imr;
723 u32 gt_ier;
724 u32 pm_imr;
725 u32 pm_ier;
726 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
727
728
729 u32 tilectl;
730 u32 gt_fifoctl;
731 u32 gtlc_wake_ctrl;
732 u32 gtlc_survive;
733 u32 pmwgicz;
734
735
736 u32 gu_ctl0;
737 u32 gu_ctl1;
738 u32 pcbr;
739 u32 clock_gate_dis2;
740};
741
742struct intel_rps_ei {
743 ktime_t ktime;
744 u32 render_c0;
745 u32 media_c0;
746};
747
748struct intel_rps {
749
750
751
752
753 struct work_struct work;
754 bool interrupts_enabled;
755 u32 pm_iir;
756
757
758 u32 pm_intrmsk_mbz;
759
760
761
762
763
764
765
766
767
768
769
770 u8 cur_freq;
771 u8 min_freq_softlimit;
772 u8 max_freq_softlimit;
773 u8 max_freq;
774 u8 min_freq;
775 u8 boost_freq;
776 u8 idle_freq;
777 u8 efficient_freq;
778 u8 rp1_freq;
779 u8 rp0_freq;
780 u16 gpll_ref_freq;
781
782 int last_adj;
783
784 struct {
785 struct mutex mutex;
786
787 enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;
788 unsigned int interactive;
789
790 u8 up_threshold;
791 u8 down_threshold;
792 } power;
793
794 bool enabled;
795 atomic_t num_waiters;
796 atomic_t boosts;
797
798
799 struct intel_rps_ei ei;
800};
801
802struct intel_rc6 {
803 bool enabled;
804 u64 prev_hw_residency[4];
805 u64 cur_residency[4];
806};
807
808struct intel_llc_pstate {
809 bool enabled;
810};
811
812struct intel_gen6_power_mgmt {
813 struct intel_rps rps;
814 struct intel_rc6 rc6;
815 struct intel_llc_pstate llc_pstate;
816};
817
818
819extern spinlock_t mchdev_lock;
820
821struct intel_ilk_power_mgmt {
822 u8 cur_delay;
823 u8 min_delay;
824 u8 max_delay;
825 u8 fmax;
826 u8 fstart;
827
828 u64 last_count1;
829 unsigned long last_time1;
830 unsigned long chipset_power;
831 u64 last_count2;
832 u64 last_time2;
833 unsigned long gfx_power;
834 u8 corr;
835
836 int c_m;
837 int r_t;
838};
839
840struct drm_i915_private;
841struct i915_power_well;
842
843struct i915_power_well_ops {
844
845
846
847
848
849
850 void (*sync_hw)(struct drm_i915_private *dev_priv,
851 struct i915_power_well *power_well);
852
853
854
855
856
857 void (*enable)(struct drm_i915_private *dev_priv,
858 struct i915_power_well *power_well);
859
860
861
862
863 void (*disable)(struct drm_i915_private *dev_priv,
864 struct i915_power_well *power_well);
865
866 bool (*is_enabled)(struct drm_i915_private *dev_priv,
867 struct i915_power_well *power_well);
868};
869
870
871struct i915_power_well {
872 const char *name;
873 bool always_on;
874
875 int count;
876
877 bool hw_enabled;
878 u64 domains;
879
880 enum i915_power_well_id id;
881
882
883
884
885 union {
886 struct {
887 enum dpio_phy phy;
888 } bxt;
889 struct {
890
891 u8 irq_pipe_mask;
892
893 bool has_vga:1;
894 bool has_fuses:1;
895 } hsw;
896 };
897 const struct i915_power_well_ops *ops;
898};
899
900struct i915_power_domains {
901
902
903
904
905 bool init_power_on;
906 bool initializing;
907 int power_well_count;
908
909 struct mutex lock;
910 int domain_use_count[POWER_DOMAIN_NUM];
911 struct i915_power_well *power_wells;
912};
913
914#define MAX_L3_SLICES 2
915struct intel_l3_parity {
916 u32 *remap_info[MAX_L3_SLICES];
917 struct work_struct error_work;
918 int which_slice;
919};
920
921struct i915_gem_mm {
922
923 struct drm_mm stolen;
924
925
926 struct mutex stolen_lock;
927
928
929 spinlock_t obj_lock;
930
931
932
933 struct list_head bound_list;
934
935
936
937
938
939 struct list_head unbound_list;
940
941
942
943
944 struct list_head userfault_list;
945
946
947
948
949 struct llist_head free_list;
950 struct work_struct free_work;
951 spinlock_t free_lock;
952
953
954
955
956 atomic_t free_count;
957
958
959
960
961 struct pagestash wc_stash;
962
963
964
965
966 struct vfsmount *gemfs;
967
968
969 struct i915_hw_ppgtt *aliasing_ppgtt;
970
971 struct notifier_block oom_notifier;
972 struct notifier_block vmap_notifier;
973 struct shrinker shrinker;
974
975
976 struct list_head fence_list;
977
978
979
980
981
982
983 struct workqueue_struct *userptr_wq;
984
985 u64 unordered_timeline;
986
987
988 atomic_t bsd_engine_dispatch_index;
989
990
991 uint32_t bit_6_swizzle_x;
992
993 uint32_t bit_6_swizzle_y;
994
995
996 spinlock_t object_stat_lock;
997 u64 object_memory;
998 u32 object_count;
999};
1000
1001#define I915_IDLE_ENGINES_TIMEOUT (200)
1002
1003#define I915_RESET_TIMEOUT (10 * HZ)
1004#define I915_FENCE_TIMEOUT (10 * HZ)
1005
1006#define I915_ENGINE_DEAD_TIMEOUT (4 * HZ)
1007#define I915_SEQNO_DEAD_TIMEOUT (12 * HZ)
1008
1009#define I915_ENGINE_WEDGED_TIMEOUT (60 * HZ)
1010
1011#define DP_AUX_A 0x40
1012#define DP_AUX_B 0x10
1013#define DP_AUX_C 0x20
1014#define DP_AUX_D 0x30
1015#define DP_AUX_E 0x50
1016#define DP_AUX_F 0x60
1017
1018#define DDC_PIN_B 0x05
1019#define DDC_PIN_C 0x04
1020#define DDC_PIN_D 0x06
1021
1022struct ddi_vbt_port_info {
1023 int max_tmds_clock;
1024
1025
1026
1027
1028
1029
1030#define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1031 uint8_t hdmi_level_shift;
1032
1033 uint8_t supports_dvi:1;
1034 uint8_t supports_hdmi:1;
1035 uint8_t supports_dp:1;
1036 uint8_t supports_edp:1;
1037
1038 uint8_t alternate_aux_channel;
1039 uint8_t alternate_ddc_pin;
1040
1041 uint8_t dp_boost_level;
1042 uint8_t hdmi_boost_level;
1043 int dp_max_link_rate;
1044};
1045
1046enum psr_lines_to_wait {
1047 PSR_0_LINES_TO_WAIT = 0,
1048 PSR_1_LINE_TO_WAIT,
1049 PSR_4_LINES_TO_WAIT,
1050 PSR_8_LINES_TO_WAIT
1051};
1052
1053struct intel_vbt_data {
1054 struct drm_display_mode *lfp_lvds_vbt_mode;
1055 struct drm_display_mode *sdvo_lvds_vbt_mode;
1056
1057
1058 unsigned int int_tv_support:1;
1059 unsigned int lvds_dither:1;
1060 unsigned int int_crt_support:1;
1061 unsigned int lvds_use_ssc:1;
1062 unsigned int int_lvds_support:1;
1063 unsigned int display_clock_mode:1;
1064 unsigned int fdi_rx_polarity_inverted:1;
1065 unsigned int panel_type:4;
1066 int lvds_ssc_freq;
1067 unsigned int bios_lvds_val;
1068
1069 enum drrs_support_type drrs_type;
1070
1071 struct {
1072 int rate;
1073 int lanes;
1074 int preemphasis;
1075 int vswing;
1076 bool low_vswing;
1077 bool initialized;
1078 int bpp;
1079 struct edp_power_seq pps;
1080 } edp;
1081
1082 struct {
1083 bool enable;
1084 bool full_link;
1085 bool require_aux_wakeup;
1086 int idle_frames;
1087 enum psr_lines_to_wait lines_to_wait;
1088 int tp1_wakeup_time_us;
1089 int tp2_tp3_wakeup_time_us;
1090 } psr;
1091
1092 struct {
1093 u16 pwm_freq_hz;
1094 bool present;
1095 bool active_low_pwm;
1096 u8 min_brightness;
1097 u8 controller;
1098 enum intel_backlight_type type;
1099 } backlight;
1100
1101
1102 struct {
1103 u16 panel_id;
1104 struct mipi_config *config;
1105 struct mipi_pps_data *pps;
1106 u16 bl_ports;
1107 u16 cabc_ports;
1108 u8 seq_version;
1109 u32 size;
1110 u8 *data;
1111 const u8 *sequence[MIPI_SEQ_MAX];
1112 u8 *deassert_seq;
1113 } dsi;
1114
1115 int crt_ddc_pin;
1116
1117 int child_dev_num;
1118 struct child_device_config *child_dev;
1119
1120 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1121 struct sdvo_device_mapping sdvo_mappings[2];
1122};
1123
1124enum intel_ddb_partitioning {
1125 INTEL_DDB_PART_1_2,
1126 INTEL_DDB_PART_5_6,
1127};
1128
1129struct intel_wm_level {
1130 bool enable;
1131 uint32_t pri_val;
1132 uint32_t spr_val;
1133 uint32_t cur_val;
1134 uint32_t fbc_val;
1135};
1136
1137struct ilk_wm_values {
1138 uint32_t wm_pipe[3];
1139 uint32_t wm_lp[3];
1140 uint32_t wm_lp_spr[3];
1141 uint32_t wm_linetime[3];
1142 bool enable_fbc_wm;
1143 enum intel_ddb_partitioning partitioning;
1144};
1145
1146struct g4x_pipe_wm {
1147 uint16_t plane[I915_MAX_PLANES];
1148 uint16_t fbc;
1149};
1150
1151struct g4x_sr_wm {
1152 uint16_t plane;
1153 uint16_t cursor;
1154 uint16_t fbc;
1155};
1156
1157struct vlv_wm_ddl_values {
1158 uint8_t plane[I915_MAX_PLANES];
1159};
1160
1161struct vlv_wm_values {
1162 struct g4x_pipe_wm pipe[3];
1163 struct g4x_sr_wm sr;
1164 struct vlv_wm_ddl_values ddl[3];
1165 uint8_t level;
1166 bool cxsr;
1167};
1168
1169struct g4x_wm_values {
1170 struct g4x_pipe_wm pipe[2];
1171 struct g4x_sr_wm sr;
1172 struct g4x_sr_wm hpll;
1173 bool cxsr;
1174 bool hpll_en;
1175 bool fbc_en;
1176};
1177
1178struct skl_ddb_entry {
1179 uint16_t start, end;
1180};
1181
1182static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1183{
1184 return entry->end - entry->start;
1185}
1186
1187static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1188 const struct skl_ddb_entry *e2)
1189{
1190 if (e1->start == e2->start && e1->end == e2->end)
1191 return true;
1192
1193 return false;
1194}
1195
1196struct skl_ddb_allocation {
1197
1198 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1199 struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1200 u8 enabled_slices;
1201};
1202
1203struct skl_ddb_values {
1204 unsigned dirty_pipes;
1205 struct skl_ddb_allocation ddb;
1206};
1207
1208struct skl_wm_level {
1209 bool plane_en;
1210 uint16_t plane_res_b;
1211 uint8_t plane_res_l;
1212};
1213
1214
1215struct skl_wm_params {
1216 bool x_tiled, y_tiled;
1217 bool rc_surface;
1218 bool is_planar;
1219 uint32_t width;
1220 uint8_t cpp;
1221 uint32_t plane_pixel_rate;
1222 uint32_t y_min_scanlines;
1223 uint32_t plane_bytes_per_line;
1224 uint_fixed_16_16_t plane_blocks_per_line;
1225 uint_fixed_16_16_t y_tile_minimum;
1226 uint32_t linetime_us;
1227 uint32_t dbuf_block_size;
1228};
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253struct i915_runtime_pm {
1254 atomic_t wakeref_count;
1255 bool suspended;
1256 bool irqs_enabled;
1257};
1258
1259enum intel_pipe_crc_source {
1260 INTEL_PIPE_CRC_SOURCE_NONE,
1261 INTEL_PIPE_CRC_SOURCE_PLANE1,
1262 INTEL_PIPE_CRC_SOURCE_PLANE2,
1263 INTEL_PIPE_CRC_SOURCE_PF,
1264 INTEL_PIPE_CRC_SOURCE_PIPE,
1265
1266 INTEL_PIPE_CRC_SOURCE_TV,
1267 INTEL_PIPE_CRC_SOURCE_DP_B,
1268 INTEL_PIPE_CRC_SOURCE_DP_C,
1269 INTEL_PIPE_CRC_SOURCE_DP_D,
1270 INTEL_PIPE_CRC_SOURCE_AUTO,
1271 INTEL_PIPE_CRC_SOURCE_MAX,
1272};
1273
1274#define INTEL_PIPE_CRC_ENTRIES_NR 128
1275struct intel_pipe_crc {
1276 spinlock_t lock;
1277 int skipped;
1278 enum intel_pipe_crc_source source;
1279};
1280
1281struct i915_frontbuffer_tracking {
1282 spinlock_t lock;
1283
1284
1285
1286
1287
1288 unsigned busy_bits;
1289 unsigned flip_bits;
1290};
1291
1292struct i915_wa_reg {
1293 u32 addr;
1294 u32 value;
1295
1296 u32 mask;
1297};
1298
1299#define I915_MAX_WA_REGS 16
1300
1301struct i915_workarounds {
1302 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1303 u32 count;
1304};
1305
1306struct i915_virtual_gpu {
1307 bool active;
1308 u32 caps;
1309};
1310
1311
1312struct intel_wm_config {
1313 unsigned int num_pipes_active;
1314 bool sprites_enabled;
1315 bool sprites_scaled;
1316};
1317
1318struct i915_oa_format {
1319 u32 format;
1320 int size;
1321};
1322
1323struct i915_oa_reg {
1324 i915_reg_t addr;
1325 u32 value;
1326};
1327
1328struct i915_oa_config {
1329 char uuid[UUID_STRING_LEN + 1];
1330 int id;
1331
1332 const struct i915_oa_reg *mux_regs;
1333 u32 mux_regs_len;
1334 const struct i915_oa_reg *b_counter_regs;
1335 u32 b_counter_regs_len;
1336 const struct i915_oa_reg *flex_regs;
1337 u32 flex_regs_len;
1338
1339 struct attribute_group sysfs_metric;
1340 struct attribute *attrs[2];
1341 struct device_attribute sysfs_metric_id;
1342
1343 atomic_t ref_count;
1344};
1345
1346struct i915_perf_stream;
1347
1348
1349
1350
1351struct i915_perf_stream_ops {
1352
1353
1354
1355
1356
1357 void (*enable)(struct i915_perf_stream *stream);
1358
1359
1360
1361
1362
1363
1364 void (*disable)(struct i915_perf_stream *stream);
1365
1366
1367
1368
1369
1370 void (*poll_wait)(struct i915_perf_stream *stream,
1371 struct file *file,
1372 poll_table *wait);
1373
1374
1375
1376
1377
1378
1379 int (*wait_unlocked)(struct i915_perf_stream *stream);
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399 int (*read)(struct i915_perf_stream *stream,
1400 char __user *buf,
1401 size_t count,
1402 size_t *offset);
1403
1404
1405
1406
1407
1408
1409 void (*destroy)(struct i915_perf_stream *stream);
1410};
1411
1412
1413
1414
1415struct i915_perf_stream {
1416
1417
1418
1419 struct drm_i915_private *dev_priv;
1420
1421
1422
1423
1424 struct list_head link;
1425
1426
1427
1428
1429
1430
1431 u32 sample_flags;
1432
1433
1434
1435
1436
1437
1438 int sample_size;
1439
1440
1441
1442
1443
1444 struct i915_gem_context *ctx;
1445
1446
1447
1448
1449
1450
1451 bool enabled;
1452
1453
1454
1455
1456
1457 const struct i915_perf_stream_ops *ops;
1458
1459
1460
1461
1462 struct i915_oa_config *oa_config;
1463};
1464
1465
1466
1467
1468struct i915_oa_ops {
1469
1470
1471
1472
1473 bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
1474 u32 addr);
1475
1476
1477
1478
1479
1480 bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);
1481
1482
1483
1484
1485
1486 bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503 void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1504
1505
1506
1507
1508
1509
1510
1511 int (*enable_metric_set)(struct drm_i915_private *dev_priv,
1512 const struct i915_oa_config *oa_config);
1513
1514
1515
1516
1517
1518 void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1519
1520
1521
1522
1523 void (*oa_enable)(struct drm_i915_private *dev_priv);
1524
1525
1526
1527
1528 void (*oa_disable)(struct drm_i915_private *dev_priv);
1529
1530
1531
1532
1533
1534 int (*read)(struct i915_perf_stream *stream,
1535 char __user *buf,
1536 size_t count,
1537 size_t *offset);
1538
1539
1540
1541
1542
1543
1544
1545
1546 u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1547};
1548
1549struct intel_cdclk_state {
1550 unsigned int cdclk, vco, ref, bypass;
1551 u8 voltage_level;
1552};
1553
1554struct drm_i915_private {
1555 struct drm_device drm;
1556
1557 struct kmem_cache *objects;
1558 struct kmem_cache *vmas;
1559 struct kmem_cache *luts;
1560 struct kmem_cache *requests;
1561 struct kmem_cache *dependencies;
1562 struct kmem_cache *priorities;
1563
1564 const struct intel_device_info info;
1565 struct intel_driver_caps caps;
1566
1567
1568
1569
1570
1571
1572
1573
1574 struct resource dsm;
1575
1576
1577
1578 struct resource dsm_reserved;
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589 resource_size_t stolen_usable_size;
1590
1591 void __iomem *regs;
1592
1593 struct intel_uncore uncore;
1594
1595 struct i915_virtual_gpu vgpu;
1596
1597 struct intel_gvt *gvt;
1598
1599 struct intel_wopcm wopcm;
1600
1601 struct intel_huc huc;
1602 struct intel_guc guc;
1603
1604 struct intel_csr csr;
1605
1606 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1607
1608
1609
1610 struct mutex gmbus_mutex;
1611
1612
1613
1614
1615 uint32_t gpio_mmio_base;
1616
1617
1618 uint32_t mipi_mmio_base;
1619
1620 uint32_t psr_mmio_base;
1621
1622 uint32_t pps_mmio_base;
1623
1624 wait_queue_head_t gmbus_wait_queue;
1625
1626 struct pci_dev *bridge_dev;
1627 struct intel_engine_cs *engine[I915_NUM_ENGINES];
1628
1629 struct i915_gem_context *kernel_context;
1630
1631 struct i915_gem_context *preempt_context;
1632 struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
1633 [MAX_ENGINE_INSTANCE + 1];
1634
1635 struct drm_dma_handle *status_page_dmah;
1636 struct resource mch_res;
1637
1638
1639 spinlock_t irq_lock;
1640
1641 bool display_irqs_enabled;
1642
1643
1644 struct pm_qos_request pm_qos;
1645
1646
1647 struct mutex sb_lock;
1648
1649
1650 union {
1651 u32 irq_mask;
1652 u32 de_irq_mask[I915_MAX_PIPES];
1653 };
1654 u32 gt_irq_mask;
1655 u32 pm_imr;
1656 u32 pm_ier;
1657 u32 pm_rps_events;
1658 u32 pm_guc_events;
1659 u32 pipestat_irq_mask[I915_MAX_PIPES];
1660
1661 struct i915_hotplug hotplug;
1662 struct intel_fbc fbc;
1663 struct i915_drrs drrs;
1664 struct intel_opregion opregion;
1665 struct intel_vbt_data vbt;
1666
1667 bool preserve_bios_swizzle;
1668
1669
1670 struct intel_overlay *overlay;
1671
1672
1673 struct mutex backlight_lock;
1674
1675
1676 bool no_aux_handshake;
1677
1678
1679 struct mutex pps_mutex;
1680
1681 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES];
1682 int num_fence_regs;
1683
1684 unsigned int fsb_freq, mem_freq, is_ddr3;
1685 unsigned int skl_preferred_vco_freq;
1686 unsigned int max_cdclk_freq;
1687
1688 unsigned int max_dotclk_freq;
1689 unsigned int rawclk_freq;
1690 unsigned int hpll_freq;
1691 unsigned int fdi_pll_freq;
1692 unsigned int czclk_freq;
1693
1694 struct {
1695
1696
1697
1698
1699
1700
1701
1702 struct intel_cdclk_state logical;
1703
1704
1705
1706
1707 struct intel_cdclk_state actual;
1708
1709 struct intel_cdclk_state hw;
1710 } cdclk;
1711
1712
1713
1714
1715
1716
1717
1718
1719 struct workqueue_struct *wq;
1720
1721
1722 struct workqueue_struct *modeset_wq;
1723
1724
1725 struct drm_i915_display_funcs display;
1726
1727
1728 enum intel_pch pch_type;
1729 unsigned short pch_id;
1730
1731 unsigned long quirks;
1732
1733 struct drm_atomic_state *modeset_restore_state;
1734 struct drm_modeset_acquire_ctx reset_ctx;
1735
1736 struct i915_ggtt ggtt;
1737
1738 struct i915_gem_mm mm;
1739 DECLARE_HASHTABLE(mm_structs, 7);
1740 struct mutex mm_lock;
1741
1742 struct intel_ppat ppat;
1743
1744
1745
1746 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1747 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1748
1749#ifdef CONFIG_DEBUG_FS
1750 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1751#endif
1752
1753
1754 int num_shared_dpll;
1755 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1756 const struct intel_dpll_mgr *dpll_mgr;
1757
1758
1759
1760
1761
1762
1763 struct mutex dpll_lock;
1764
1765 unsigned int active_crtcs;
1766
1767 int min_cdclk[I915_MAX_PIPES];
1768
1769 u8 min_voltage_level[I915_MAX_PIPES];
1770
1771 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1772
1773 struct i915_workarounds workarounds;
1774
1775 struct i915_frontbuffer_tracking fb_tracking;
1776
1777 struct intel_atomic_helper {
1778 struct llist_head free_list;
1779 struct work_struct free_work;
1780 } atomic_helper;
1781
1782 u16 orig_clock;
1783
1784 bool mchbar_need_disable;
1785
1786 struct intel_l3_parity l3_parity;
1787
1788
1789 u32 edram_cap;
1790
1791
1792
1793
1794
1795
1796
1797 struct mutex pcu_lock;
1798
1799
1800 struct intel_gen6_power_mgmt gt_pm;
1801
1802
1803
1804 struct intel_ilk_power_mgmt ips;
1805
1806 struct i915_power_domains power_domains;
1807
1808 struct i915_psr psr;
1809
1810 struct i915_gpu_error gpu_error;
1811
1812 struct drm_i915_gem_object *vlv_pctx;
1813
1814
1815 struct intel_fbdev *fbdev;
1816 struct work_struct fbdev_suspend_work;
1817
1818 struct drm_property *broadcast_rgb_property;
1819 struct drm_property *force_audio_property;
1820
1821
1822 struct i915_audio_component *audio_component;
1823 bool audio_component_registered;
1824
1825
1826
1827
1828 struct mutex av_mutex;
1829
1830 struct {
1831 struct list_head list;
1832 struct llist_head free_list;
1833 struct work_struct free_work;
1834
1835
1836
1837
1838
1839 struct ida hw_ida;
1840#define MAX_CONTEXT_HW_ID (1<<21)
1841#define MAX_GUC_CONTEXT_HW_ID (1 << 20)
1842#define GEN11_MAX_CONTEXT_HW_ID (1<<11)
1843 } contexts;
1844
1845 u32 fdi_rx_config;
1846
1847
1848 u32 chv_phy_control;
1849
1850
1851
1852
1853
1854 u32 chv_dpll_md[I915_MAX_PIPES];
1855 u32 bxt_phy_grc;
1856
1857 u32 suspend_count;
1858 bool power_domains_suspended;
1859 struct i915_suspend_saved_registers regfile;
1860 struct vlv_s0ix_state vlv_s0ix_state;
1861
1862 enum {
1863 I915_SAGV_UNKNOWN = 0,
1864 I915_SAGV_DISABLED,
1865 I915_SAGV_ENABLED,
1866 I915_SAGV_NOT_CONTROLLED
1867 } sagv_status;
1868
1869 struct {
1870
1871
1872
1873
1874
1875
1876 uint16_t pri_latency[5];
1877
1878 uint16_t spr_latency[5];
1879
1880 uint16_t cur_latency[5];
1881
1882
1883
1884
1885
1886 uint16_t skl_latency[8];
1887
1888
1889 union {
1890 struct ilk_wm_values hw;
1891 struct skl_ddb_values skl_hw;
1892 struct vlv_wm_values vlv;
1893 struct g4x_wm_values g4x;
1894 };
1895
1896 uint8_t max_level;
1897
1898
1899
1900
1901
1902
1903 struct mutex wm_mutex;
1904
1905
1906
1907
1908
1909
1910 bool distrust_bios_wm;
1911 } wm;
1912
1913 struct i915_runtime_pm runtime_pm;
1914
1915 struct {
1916 bool initialized;
1917
1918 struct kobject *metrics_kobj;
1919 struct ctl_table_header *sysctl_header;
1920
1921
1922
1923
1924
1925 struct mutex metrics_lock;
1926
1927
1928
1929
1930
1931 struct idr metrics_idr;
1932
1933
1934
1935
1936
1937 struct mutex lock;
1938 struct list_head streams;
1939
1940 struct {
1941
1942
1943
1944
1945
1946
1947 struct i915_perf_stream *exclusive_stream;
1948
1949 struct intel_context *pinned_ctx;
1950 u32 specific_ctx_id;
1951 u32 specific_ctx_id_mask;
1952
1953 struct hrtimer poll_check_timer;
1954 wait_queue_head_t poll_wq;
1955 bool pollin;
1956
1957
1958
1959
1960
1961 struct ratelimit_state spurious_report_rs;
1962
1963 bool periodic;
1964 int period_exponent;
1965
1966 struct i915_oa_config test_config;
1967
1968 struct {
1969 struct i915_vma *vma;
1970 u8 *vaddr;
1971 u32 last_ctx_id;
1972 int format;
1973 int format_size;
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000 spinlock_t ptr_lock;
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011 struct {
2012 u32 offset;
2013 } tails[2];
2014
2015
2016
2017
2018
2019 unsigned int aged_tail_idx;
2020
2021
2022
2023
2024
2025
2026 u64 aging_timestamp;
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037 u32 head;
2038 } oa_buffer;
2039
2040 u32 gen7_latched_oastatus1;
2041 u32 ctx_oactxctrl_offset;
2042 u32 ctx_flexeu0_offset;
2043
2044
2045
2046
2047
2048
2049 u32 gen8_valid_ctx_bit;
2050
2051 struct i915_oa_ops ops;
2052 const struct i915_oa_format *oa_formats;
2053 } oa;
2054 } perf;
2055
2056
2057 struct {
2058 void (*resume)(struct drm_i915_private *);
2059 void (*cleanup_engine)(struct intel_engine_cs *engine);
2060
2061 struct list_head timelines;
2062
2063 struct list_head active_rings;
2064 struct list_head closed_vma;
2065 u32 active_requests;
2066 u32 request_serial;
2067
2068
2069
2070
2071
2072
2073
2074
2075 bool awake;
2076
2077
2078
2079
2080 unsigned int epoch;
2081#define I915_EPOCH_INVALID 0
2082
2083
2084
2085
2086
2087
2088
2089
2090 struct delayed_work retire_work;
2091
2092
2093
2094
2095
2096
2097
2098
2099 struct delayed_work idle_work;
2100
2101 ktime_t last_init_time;
2102 } gt;
2103
2104
2105 bool chv_phy_assert[2];
2106
2107 bool ipc_enabled;
2108
2109
2110 struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2111
2112
2113 struct {
2114 struct platform_device *platdev;
2115 int irq;
2116 } lpe_audio;
2117
2118 struct i915_pmu pmu;
2119
2120
2121
2122
2123
2124};
2125
2126static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
2127{
2128 return container_of(dev, struct drm_i915_private, drm);
2129}
2130
2131static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
2132{
2133 return to_i915(dev_get_drvdata(kdev));
2134}
2135
2136static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm)
2137{
2138 return container_of(wopcm, struct drm_i915_private, wopcm);
2139}
2140
2141static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
2142{
2143 return container_of(guc, struct drm_i915_private, guc);
2144}
2145
2146static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
2147{
2148 return container_of(huc, struct drm_i915_private, huc);
2149}
2150
2151
2152#define for_each_engine(engine__, dev_priv__, id__) \
2153 for ((id__) = 0; \
2154 (id__) < I915_NUM_ENGINES; \
2155 (id__)++) \
2156 for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2157
2158
2159#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
2160 for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \
2161 (tmp__) ? \
2162 ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \
2163 0;)
2164
2165enum hdmi_force_audio {
2166 HDMI_AUDIO_OFF_DVI = -2,
2167 HDMI_AUDIO_OFF,
2168 HDMI_AUDIO_AUTO,
2169 HDMI_AUDIO_ON,
2170};
2171
2172#define I915_GTT_OFFSET_NONE ((u32)-1)
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2183#define INTEL_FRONTBUFFER(pipe, plane_id) ({ \
2184 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
2185 BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \
2186 BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \
2187})
2188#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2189 BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2190#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2191 GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \
2192 INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))
2193
2194
2195
2196
2197static __always_inline struct sgt_iter {
2198 struct scatterlist *sgp;
2199 union {
2200 unsigned long pfn;
2201 dma_addr_t dma;
2202 };
2203 unsigned int curr;
2204 unsigned int max;
2205} __sgt_iter(struct scatterlist *sgl, bool dma) {
2206 struct sgt_iter s = { .sgp = sgl };
2207
2208 if (s.sgp) {
2209 s.max = s.curr = s.sgp->offset;
2210 s.max += s.sgp->length;
2211 if (dma)
2212 s.dma = sg_dma_address(s.sgp);
2213 else
2214 s.pfn = page_to_pfn(sg_page(s.sgp));
2215 }
2216
2217 return s;
2218}
2219
2220static inline struct scatterlist *____sg_next(struct scatterlist *sg)
2221{
2222 ++sg;
2223 if (unlikely(sg_is_chain(sg)))
2224 sg = sg_chain_ptr(sg);
2225 return sg;
2226}
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237static inline struct scatterlist *__sg_next(struct scatterlist *sg)
2238{
2239 return sg_is_last(sg) ? NULL : ____sg_next(sg);
2240}
2241
2242
2243
2244
2245
2246
2247
2248#define for_each_sgt_dma(__dmap, __iter, __sgt) \
2249 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2250 ((__dmap) = (__iter).dma + (__iter).curr); \
2251 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2252 (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2253
2254
2255
2256
2257
2258
2259
2260#define for_each_sgt_page(__pp, __iter, __sgt) \
2261 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2262 ((__pp) = (__iter).pfn == 0 ? NULL : \
2263 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2264 (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \
2265 (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2266
2267static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
2268{
2269 unsigned int page_sizes;
2270
2271 page_sizes = 0;
2272 while (sg) {
2273 GEM_BUG_ON(sg->offset);
2274 GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
2275 page_sizes |= sg->length;
2276 sg = __sg_next(sg);
2277 }
2278
2279 return page_sizes;
2280}
2281
2282static inline unsigned int i915_sg_segment_size(void)
2283{
2284 unsigned int size = swiotlb_max_segment();
2285
2286 if (size == 0)
2287 return SCATTERLIST_MAX_SEGMENT;
2288
2289 size = rounddown(size, PAGE_SIZE);
2290
2291 if (size < PAGE_SIZE)
2292 size = PAGE_SIZE;
2293
2294 return size;
2295}
2296
2297static inline const struct intel_device_info *
2298intel_info(const struct drm_i915_private *dev_priv)
2299{
2300 return &dev_priv->info;
2301}
2302
2303#define INTEL_INFO(dev_priv) intel_info((dev_priv))
2304#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
2305
2306#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
2307#define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id)
2308
2309#define REVID_FOREVER 0xff
2310#define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision)
2311
2312#define GEN_FOREVER (0)
2313
2314#define INTEL_GEN_MASK(s, e) ( \
2315 BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
2316 BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
2317 GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
2318 (s) != GEN_FOREVER ? (s) - 1 : 0) \
2319)
2320
2321
2322
2323
2324
2325
2326#define IS_GEN(dev_priv, s, e) \
2327 (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2328
2329
2330
2331
2332
2333
2334#define IS_REVID(p, since, until) \
2335 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2336
2337#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
2338
2339#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
2340#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
2341#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X)
2342#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G)
2343#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G)
2344#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM)
2345#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G)
2346#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM)
2347#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G)
2348#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM)
2349#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45)
2350#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45)
2351#define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv))
2352#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001)
2353#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011)
2354#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
2355#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33)
2356#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
2357#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2358#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
2359 (dev_priv)->info.gt == 1)
2360#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
2361#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
2362#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
2363#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL)
2364#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
2365#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON)
2366#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
2367#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
2368#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
2369#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2370#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2371#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
2372#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
2373 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
2374#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
2375 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \
2376 (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \
2377 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
2378
2379#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
2380 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
2381#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
2382 (dev_priv)->info.gt == 3)
2383#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
2384 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
2385#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
2386 (dev_priv)->info.gt == 3)
2387
2388#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
2389 INTEL_DEVID(dev_priv) == 0x0A1E)
2390#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \
2391 INTEL_DEVID(dev_priv) == 0x1913 || \
2392 INTEL_DEVID(dev_priv) == 0x1916 || \
2393 INTEL_DEVID(dev_priv) == 0x1921 || \
2394 INTEL_DEVID(dev_priv) == 0x1926)
2395#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \
2396 INTEL_DEVID(dev_priv) == 0x1915 || \
2397 INTEL_DEVID(dev_priv) == 0x191E)
2398#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \
2399 INTEL_DEVID(dev_priv) == 0x5913 || \
2400 INTEL_DEVID(dev_priv) == 0x5916 || \
2401 INTEL_DEVID(dev_priv) == 0x5921 || \
2402 INTEL_DEVID(dev_priv) == 0x5926)
2403#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \
2404 INTEL_DEVID(dev_priv) == 0x5915 || \
2405 INTEL_DEVID(dev_priv) == 0x591E)
2406#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
2407 (dev_priv)->info.gt == 2)
2408#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
2409 (dev_priv)->info.gt == 3)
2410#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
2411 (dev_priv)->info.gt == 4)
2412#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
2413 (dev_priv)->info.gt == 2)
2414#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
2415 (dev_priv)->info.gt == 3)
2416#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2417 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2418#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2419 (dev_priv)->info.gt == 2)
2420#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
2421 (dev_priv)->info.gt == 3)
2422#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
2423 (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
2424
2425#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2426
2427#define SKL_REVID_A0 0x0
2428#define SKL_REVID_B0 0x1
2429#define SKL_REVID_C0 0x2
2430#define SKL_REVID_D0 0x3
2431#define SKL_REVID_E0 0x4
2432#define SKL_REVID_F0 0x5
2433#define SKL_REVID_G0 0x6
2434#define SKL_REVID_H0 0x7
2435
2436#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2437
2438#define BXT_REVID_A0 0x0
2439#define BXT_REVID_A1 0x1
2440#define BXT_REVID_B0 0x3
2441#define BXT_REVID_B_LAST 0x8
2442#define BXT_REVID_C0 0x9
2443
2444#define IS_BXT_REVID(dev_priv, since, until) \
2445 (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2446
2447#define KBL_REVID_A0 0x0
2448#define KBL_REVID_B0 0x1
2449#define KBL_REVID_C0 0x2
2450#define KBL_REVID_D0 0x3
2451#define KBL_REVID_E0 0x4
2452
2453#define IS_KBL_REVID(dev_priv, since, until) \
2454 (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2455
2456#define GLK_REVID_A0 0x0
2457#define GLK_REVID_A1 0x1
2458
2459#define IS_GLK_REVID(dev_priv, since, until) \
2460 (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
2461
2462#define CNL_REVID_A0 0x0
2463#define CNL_REVID_B0 0x1
2464#define CNL_REVID_C0 0x2
2465
2466#define IS_CNL_REVID(p, since, until) \
2467 (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
2468
2469#define ICL_REVID_A0 0x0
2470#define ICL_REVID_A2 0x1
2471#define ICL_REVID_B0 0x3
2472#define ICL_REVID_B2 0x4
2473#define ICL_REVID_C0 0x5
2474
2475#define IS_ICL_REVID(p, since, until) \
2476 (IS_ICELAKE(p) && IS_REVID(p, since, until))
2477
2478
2479
2480
2481
2482
2483
2484#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1)))
2485#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2)))
2486#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3)))
2487#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4)))
2488#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5)))
2489#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6)))
2490#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7)))
2491#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8)))
2492#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9)))
2493#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10)))
2494
2495#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
2496#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv))
2497#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2498
2499#define ENGINE_MASK(id) BIT(id)
2500#define RENDER_RING ENGINE_MASK(RCS)
2501#define BSD_RING ENGINE_MASK(VCS)
2502#define BLT_RING ENGINE_MASK(BCS)
2503#define VEBOX_RING ENGINE_MASK(VECS)
2504#define BSD2_RING ENGINE_MASK(VCS2)
2505#define BSD3_RING ENGINE_MASK(VCS3)
2506#define BSD4_RING ENGINE_MASK(VCS4)
2507#define VEBOX2_RING ENGINE_MASK(VECS2)
2508#define ALL_ENGINES (~0)
2509
2510#define HAS_ENGINE(dev_priv, id) \
2511 (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2512
2513#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2514#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2515#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2516#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2517
2518#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)
2519
2520#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
2521#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
2522#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2523#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
2524 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2525
2526#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
2527
2528#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
2529 ((dev_priv)->info.has_logical_ring_contexts)
2530#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
2531 ((dev_priv)->info.has_logical_ring_elsq)
2532#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
2533 ((dev_priv)->info.has_logical_ring_preemption)
2534
2535#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
2536
2537#define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt)
2538#define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2)
2539#define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3)
2540#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
2541 GEM_BUG_ON((sizes) == 0); \
2542 ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
2543})
2544
2545#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay)
2546#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
2547 ((dev_priv)->info.overlay_needs_physical)
2548
2549
2550#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
2551
2552
2553#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2554 (IS_CANNONLAKE(dev_priv) || \
2555 IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2556
2557#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2558#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \
2559 IS_GEMINILAKE(dev_priv) || \
2560 IS_KABYLAKE(dev_priv))
2561
2562
2563
2564
2565#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
2566 !(IS_I915G(dev_priv) || \
2567 IS_I915GM(dev_priv)))
2568#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv)
2569#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug)
2570
2571#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
2572#define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc)
2573#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
2574
2575#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2576
2577#define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst)
2578
2579#define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi)
2580#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
2581#define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr)
2582
2583#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
2584#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
2585#define HAS_RC6pp(dev_priv) (false)
2586
2587#define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr)
2588
2589#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2590#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
2591
2592#define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc)
2593
2594
2595
2596
2597
2598
2599#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
2600#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
2601#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2602#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
2603
2604
2605#define HAS_HUC(dev_priv) (HAS_GUC(dev_priv))
2606#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
2607
2608
2609#define USES_GUC(dev_priv) intel_uc_is_using_guc()
2610#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission()
2611#define USES_HUC(dev_priv) intel_uc_is_using_huc()
2612
2613#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2614
2615#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
2616
2617#define INTEL_PCH_DEVICE_ID_MASK 0xff80
2618#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2619#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2620#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2621#define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2622#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2623#define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
2624#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
2625#define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2626#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2627#define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280
2628#define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300
2629#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80
2630#define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480
2631#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2632#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2633#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900
2634
2635#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2636#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
2637#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2638#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2639#define HAS_PCH_CNP_LP(dev_priv) \
2640 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2641#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
2642#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
2643#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2644#define HAS_PCH_LPT_LP(dev_priv) \
2645 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
2646 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2647#define HAS_PCH_LPT_H(dev_priv) \
2648 (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
2649 INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2650#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
2651#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
2652#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
2653#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2654
2655#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2656
2657#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2658
2659
2660#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2661#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
2662 2 : HAS_L3_DPF(dev_priv))
2663
2664#define GT_FREQUENCY_MULTIPLIER 50
2665#define GEN9_FREQ_SCALER 3
2666
2667#include "i915_trace.h"
2668
2669static inline bool intel_vtd_active(void)
2670{
2671#ifdef CONFIG_INTEL_IOMMU
2672 if (intel_iommu_gfx_mapped)
2673 return true;
2674#endif
2675 return false;
2676}
2677
2678static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
2679{
2680 return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
2681}
2682
2683static inline bool
2684intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
2685{
2686 return IS_BROXTON(dev_priv) && intel_vtd_active();
2687}
2688
2689int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2690 int enable_ppgtt);
2691
2692
2693void __printf(3, 4)
2694__i915_printk(struct drm_i915_private *dev_priv, const char *level,
2695 const char *fmt, ...);
2696
2697#define i915_report_error(dev_priv, fmt, ...) \
2698 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2699
2700#ifdef CONFIG_COMPAT
2701extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2702 unsigned long arg);
2703#else
2704#define i915_compat_ioctl NULL
2705#endif
2706extern const struct dev_pm_ops i915_pm_ops;
2707
2708extern int i915_driver_load(struct pci_dev *pdev,
2709 const struct pci_device_id *ent);
2710extern void i915_driver_unload(struct drm_device *dev);
2711extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
2712extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2713
2714extern void i915_reset(struct drm_i915_private *i915,
2715 unsigned int stalled_mask,
2716 const char *reason);
2717extern int i915_reset_engine(struct intel_engine_cs *engine,
2718 const char *reason);
2719
2720extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2721extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2722extern int intel_guc_reset_engine(struct intel_guc *guc,
2723 struct intel_engine_cs *engine);
2724extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2725extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2726extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2727extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2728extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2729extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2730int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2731
2732int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2733int intel_engines_init(struct drm_i915_private *dev_priv);
2734
2735u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv);
2736
2737
2738void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
2739 u32 pin_mask, u32 long_mask);
2740void intel_hpd_init(struct drm_i915_private *dev_priv);
2741void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2742void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2743enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv,
2744 enum port port);
2745bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2746void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2747
2748
2749static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
2750{
2751 unsigned long delay;
2752
2753 if (unlikely(!i915_modparams.enable_hangcheck))
2754 return;
2755
2756
2757
2758
2759
2760
2761 delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
2762 queue_delayed_work(system_long_wq,
2763 &dev_priv->gpu_error.hangcheck_work, delay);
2764}
2765
2766__printf(4, 5)
2767void i915_handle_error(struct drm_i915_private *dev_priv,
2768 u32 engine_mask,
2769 unsigned long flags,
2770 const char *fmt, ...);
2771#define I915_ERROR_CAPTURE BIT(0)
2772
2773extern void intel_irq_init(struct drm_i915_private *dev_priv);
2774extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2775int intel_irq_install(struct drm_i915_private *dev_priv);
2776void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2777
2778static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
2779{
2780 return dev_priv->gvt;
2781}
2782
2783static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2784{
2785 return dev_priv->vgpu.active;
2786}
2787
2788u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
2789 enum pipe pipe);
2790void
2791i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2792 u32 status_mask);
2793
2794void
2795i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2796 u32 status_mask);
2797
2798void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2799void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2800void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2801 uint32_t mask,
2802 uint32_t bits);
2803void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2804 uint32_t interrupt_mask,
2805 uint32_t enabled_irq_mask);
2806static inline void
2807ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2808{
2809 ilk_update_display_irq(dev_priv, bits, bits);
2810}
2811static inline void
2812ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2813{
2814 ilk_update_display_irq(dev_priv, bits, 0);
2815}
2816void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2817 enum pipe pipe,
2818 uint32_t interrupt_mask,
2819 uint32_t enabled_irq_mask);
2820static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2821 enum pipe pipe, uint32_t bits)
2822{
2823 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2824}
2825static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2826 enum pipe pipe, uint32_t bits)
2827{
2828 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2829}
2830void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2831 uint32_t interrupt_mask,
2832 uint32_t enabled_irq_mask);
2833static inline void
2834ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2835{
2836 ibx_display_interrupt_update(dev_priv, bits, bits);
2837}
2838static inline void
2839ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2840{
2841 ibx_display_interrupt_update(dev_priv, bits, 0);
2842}
2843
2844
2845int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2846 struct drm_file *file_priv);
2847int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2848 struct drm_file *file_priv);
2849int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2850 struct drm_file *file_priv);
2851int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2852 struct drm_file *file_priv);
2853int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2854 struct drm_file *file_priv);
2855int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2856 struct drm_file *file_priv);
2857int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2858 struct drm_file *file_priv);
2859int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
2860 struct drm_file *file_priv);
2861int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
2862 struct drm_file *file_priv);
2863int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file_priv);
2865int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file);
2867int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2868 struct drm_file *file);
2869int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2870 struct drm_file *file_priv);
2871int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2872 struct drm_file *file_priv);
2873int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
2874 struct drm_file *file_priv);
2875int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
2876 struct drm_file *file_priv);
2877int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
2878void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
2879int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2880 struct drm_file *file);
2881int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2882 struct drm_file *file_priv);
2883int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2884 struct drm_file *file_priv);
2885void i915_gem_sanitize(struct drm_i915_private *i915);
2886int i915_gem_init_early(struct drm_i915_private *dev_priv);
2887void i915_gem_cleanup_early(struct drm_i915_private *dev_priv);
2888void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2889int i915_gem_freeze(struct drm_i915_private *dev_priv);
2890int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
2891
2892void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
2893void i915_gem_object_free(struct drm_i915_gem_object *obj);
2894void i915_gem_object_init(struct drm_i915_gem_object *obj,
2895 const struct drm_i915_gem_object_ops *ops);
2896struct drm_i915_gem_object *
2897i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
2898struct drm_i915_gem_object *
2899i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
2900 const void *data, size_t size);
2901void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
2902void i915_gem_free_object(struct drm_gem_object *obj);
2903
2904static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
2905{
2906 if (!atomic_read(&i915->mm.free_count))
2907 return;
2908
2909
2910
2911
2912
2913
2914
2915 do {
2916 rcu_barrier();
2917 } while (flush_work(&i915->mm.free_work));
2918}
2919
2920static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
2921{
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933 int pass = 2;
2934 do {
2935 rcu_barrier();
2936 drain_workqueue(i915->wq);
2937 } while (--pass);
2938}
2939
2940struct i915_vma * __must_check
2941i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2942 const struct i915_ggtt_view *view,
2943 u64 size,
2944 u64 alignment,
2945 u64 flags);
2946
2947int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
2948void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2949
2950void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);
2951
2952static inline int __sg_page_count(const struct scatterlist *sg)
2953{
2954 return sg->length >> PAGE_SHIFT;
2955}
2956
2957struct scatterlist *
2958i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
2959 unsigned int n, unsigned int *offset);
2960
2961struct page *
2962i915_gem_object_get_page(struct drm_i915_gem_object *obj,
2963 unsigned int n);
2964
2965struct page *
2966i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
2967 unsigned int n);
2968
2969dma_addr_t
2970i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
2971 unsigned long n);
2972
2973void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
2974 struct sg_table *pages,
2975 unsigned int sg_page_sizes);
2976int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2977
2978static inline int __must_check
2979i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2980{
2981 might_lock(&obj->mm.lock);
2982
2983 if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
2984 return 0;
2985
2986 return __i915_gem_object_get_pages(obj);
2987}
2988
2989static inline bool
2990i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
2991{
2992 return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
2993}
2994
2995static inline void
2996__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2997{
2998 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
2999
3000 atomic_inc(&obj->mm.pages_pin_count);
3001}
3002
3003static inline bool
3004i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
3005{
3006 return atomic_read(&obj->mm.pages_pin_count);
3007}
3008
3009static inline void
3010__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3011{
3012 GEM_BUG_ON(!i915_gem_object_has_pages(obj));
3013 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
3014
3015 atomic_dec(&obj->mm.pages_pin_count);
3016}
3017
3018static inline void
3019i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3020{
3021 __i915_gem_object_unpin_pages(obj);
3022}
3023
3024enum i915_mm_subclass {
3025 I915_MM_NORMAL = 0,
3026 I915_MM_SHRINKER
3027};
3028
3029void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
3030 enum i915_mm_subclass subclass);
3031void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
3032
3033enum i915_map_type {
3034 I915_MAP_WB = 0,
3035 I915_MAP_WC,
3036#define I915_MAP_OVERRIDE BIT(31)
3037 I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
3038 I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3039};
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
3058 enum i915_map_type type);
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
3070{
3071 i915_gem_object_unpin_pages(obj);
3072}
3073
3074int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
3075 unsigned int *needs_clflush);
3076int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
3077 unsigned int *needs_clflush);
3078#define CLFLUSH_BEFORE BIT(0)
3079#define CLFLUSH_AFTER BIT(1)
3080#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)
3081
3082static inline void
3083i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
3084{
3085 i915_gem_object_unpin_pages(obj);
3086}
3087
3088int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3089int i915_gem_dumb_create(struct drm_file *file_priv,
3090 struct drm_device *dev,
3091 struct drm_mode_create_dumb *args);
3092int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
3093 uint32_t handle, uint64_t *offset);
3094int i915_gem_mmap_gtt_version(void);
3095
3096void i915_gem_track_fb(struct drm_i915_gem_object *old,
3097 struct drm_i915_gem_object *new,
3098 unsigned frontbuffer_bits);
3099
3100int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3101
3102struct i915_request *
3103i915_gem_find_active_request(struct intel_engine_cs *engine);
3104
3105static inline bool i915_reset_backoff(struct i915_gpu_error *error)
3106{
3107 return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
3108}
3109
3110static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3111{
3112 return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3113}
3114
3115static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3116{
3117 return unlikely(test_bit(I915_WEDGED, &error->flags));
3118}
3119
3120static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3121{
3122 return i915_reset_backoff(error) | i915_terminally_wedged(error);
3123}
3124
3125static inline u32 i915_reset_count(struct i915_gpu_error *error)
3126{
3127 return READ_ONCE(error->reset_count);
3128}
3129
3130static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
3131 struct intel_engine_cs *engine)
3132{
3133 return READ_ONCE(error->reset_engine_count[engine->id]);
3134}
3135
3136struct i915_request *
3137i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3138int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3139void i915_gem_reset(struct drm_i915_private *dev_priv,
3140 unsigned int stalled_mask);
3141void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3142void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3143void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3144bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3145void i915_gem_reset_engine(struct intel_engine_cs *engine,
3146 struct i915_request *request,
3147 bool stalled);
3148
3149void i915_gem_init_mmio(struct drm_i915_private *i915);
3150int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
3151int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3152void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3153void i915_gem_fini(struct drm_i915_private *dev_priv);
3154void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3155int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3156 unsigned int flags, long timeout);
3157int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
3158void i915_gem_suspend_late(struct drm_i915_private *dev_priv);
3159void i915_gem_resume(struct drm_i915_private *dev_priv);
3160vm_fault_t i915_gem_fault(struct vm_fault *vmf);
3161int i915_gem_object_wait(struct drm_i915_gem_object *obj,
3162 unsigned int flags,
3163 long timeout,
3164 struct intel_rps_client *rps);
3165int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
3166 unsigned int flags,
3167 const struct i915_sched_attr *attr);
3168#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX
3169
3170int __must_check
3171i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
3172int __must_check
3173i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3174int __must_check
3175i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3176struct i915_vma * __must_check
3177i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3178 u32 alignment,
3179 const struct i915_ggtt_view *view,
3180 unsigned int flags);
3181void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3182int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3183 int align);
3184int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3185void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3186
3187int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3188 enum i915_cache_level cache_level);
3189
3190struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3191 struct dma_buf *dma_buf);
3192
3193struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3194 struct drm_gem_object *gem_obj, int flags);
3195
3196static inline struct i915_hw_ppgtt *
3197i915_vm_to_ppgtt(struct i915_address_space *vm)
3198{
3199 return container_of(vm, struct i915_hw_ppgtt, vm);
3200}
3201
3202
3203struct drm_i915_fence_reg *
3204i915_reserve_fence(struct drm_i915_private *dev_priv);
3205void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3206
3207void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3208void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3209
3210void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3211void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
3212 struct sg_table *pages);
3213void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
3214 struct sg_table *pages);
3215
3216static inline struct i915_gem_context *
3217__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
3218{
3219 return idr_find(&file_priv->context_idr, id);
3220}
3221
3222static inline struct i915_gem_context *
3223i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
3224{
3225 struct i915_gem_context *ctx;
3226
3227 rcu_read_lock();
3228 ctx = __i915_gem_context_lookup_rcu(file_priv, id);
3229 if (ctx && !kref_get_unless_zero(&ctx->ref))
3230 ctx = NULL;
3231 rcu_read_unlock();
3232
3233 return ctx;
3234}
3235
3236int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3237 struct drm_file *file);
3238int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
3239 struct drm_file *file);
3240int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
3241 struct drm_file *file);
3242void i915_oa_init_reg_state(struct intel_engine_cs *engine,
3243 struct i915_gem_context *ctx,
3244 uint32_t *reg_state);
3245
3246
3247int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3248 u64 min_size, u64 alignment,
3249 unsigned cache_level,
3250 u64 start, u64 end,
3251 unsigned flags);
3252int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
3253 struct drm_mm_node *node,
3254 unsigned int flags);
3255int i915_gem_evict_vm(struct i915_address_space *vm);
3256
3257void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);
3258
3259
3260static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3261{
3262 wmb();
3263 if (INTEL_GEN(dev_priv) < 6)
3264 intel_gtt_chipset_flush();
3265}
3266
3267
3268int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3269 struct drm_mm_node *node, u64 size,
3270 unsigned alignment);
3271int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3272 struct drm_mm_node *node, u64 size,
3273 unsigned alignment, u64 start,
3274 u64 end);
3275void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3276 struct drm_mm_node *node);
3277int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3278void i915_gem_cleanup_stolen(struct drm_device *dev);
3279struct drm_i915_gem_object *
3280i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
3281 resource_size_t size);
3282struct drm_i915_gem_object *
3283i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3284 resource_size_t stolen_offset,
3285 resource_size_t gtt_offset,
3286 resource_size_t size);
3287
3288
3289struct drm_i915_gem_object *
3290i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3291 phys_addr_t size);
3292
3293
3294unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3295 unsigned long target,
3296 unsigned long *nr_scanned,
3297 unsigned flags);
3298#define I915_SHRINK_PURGEABLE 0x1
3299#define I915_SHRINK_UNBOUND 0x2
3300#define I915_SHRINK_BOUND 0x4
3301#define I915_SHRINK_ACTIVE 0x8
3302#define I915_SHRINK_VMAPS 0x10
3303unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
3304void i915_gem_shrinker_register(struct drm_i915_private *i915);
3305void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3306void i915_gem_shrinker_taints_mutex(struct mutex *mutex);
3307
3308
3309static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3310{
3311 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3312
3313 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3314 i915_gem_object_is_tiled(obj);
3315}
3316
3317u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
3318 unsigned int tiling, unsigned int stride);
3319u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
3320 unsigned int tiling, unsigned int stride);
3321
3322
3323#ifdef CONFIG_DEBUG_FS
3324int i915_debugfs_register(struct drm_i915_private *dev_priv);
3325int i915_debugfs_connector_add(struct drm_connector *connector);
3326void intel_display_crc_init(struct drm_i915_private *dev_priv);
3327#else
3328static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3329static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3330{ return 0; }
3331static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3332#endif
3333
3334const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3335
3336
3337int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3338void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3339void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
3340int intel_engine_cmd_parser(struct intel_engine_cs *engine,
3341 struct drm_i915_gem_object *batch_obj,
3342 struct drm_i915_gem_object *shadow_batch_obj,
3343 u32 batch_start_offset,
3344 u32 batch_len,
3345 bool is_master);
3346
3347
3348extern void i915_perf_init(struct drm_i915_private *dev_priv);
3349extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3350extern void i915_perf_register(struct drm_i915_private *dev_priv);
3351extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3352
3353
3354extern int i915_save_state(struct drm_i915_private *dev_priv);
3355extern int i915_restore_state(struct drm_i915_private *dev_priv);
3356
3357
3358void i915_setup_sysfs(struct drm_i915_private *dev_priv);
3359void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
3360
3361
3362int intel_lpe_audio_init(struct drm_i915_private *dev_priv);
3363void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
3364void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3365void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3366 enum pipe pipe, enum port port,
3367 const void *eld, int ls_clock, bool dp_output);
3368
3369
3370extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
3371extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3372extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3373 unsigned int pin);
3374extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
3375
3376extern struct i2c_adapter *
3377intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3378extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3379extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3380static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3381{
3382 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3383}
3384extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3385
3386
3387void intel_bios_init(struct drm_i915_private *dev_priv);
3388void intel_bios_cleanup(struct drm_i915_private *dev_priv);
3389bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3390bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3391bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3392bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3393bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3394bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3395bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3396bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
3397 enum port port);
3398bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
3399 enum port port);
3400
3401
3402#ifdef CONFIG_ACPI
3403extern void intel_register_dsm_handler(void);
3404extern void intel_unregister_dsm_handler(void);
3405#else
3406static inline void intel_register_dsm_handler(void) { return; }
3407static inline void intel_unregister_dsm_handler(void) { return; }
3408#endif
3409
3410
3411static inline struct intel_device_info *
3412mkwrite_device_info(struct drm_i915_private *dev_priv)
3413{
3414 return (struct intel_device_info *)&dev_priv->info;
3415}
3416
3417
3418extern void intel_modeset_init_hw(struct drm_device *dev);
3419extern int intel_modeset_init(struct drm_device *dev);
3420extern void intel_modeset_cleanup(struct drm_device *dev);
3421extern int intel_connector_register(struct drm_connector *);
3422extern void intel_connector_unregister(struct drm_connector *);
3423extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
3424 bool state);
3425extern void intel_display_resume(struct drm_device *dev);
3426extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
3427extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3428extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3429extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3430extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3431extern void intel_rps_mark_interactive(struct drm_i915_private *i915,
3432 bool interactive);
3433extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3434 bool enable);
3435
3436int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3437 struct drm_file *file);
3438
3439
3440extern struct intel_overlay_error_state *
3441intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3442extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3443 struct intel_overlay_error_state *error);
3444
3445extern struct intel_display_error_state *
3446intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3447extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3448 struct intel_display_error_state *error);
3449
3450int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3451int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
3452 u32 val, int fast_timeout_us,
3453 int slow_timeout_ms);
3454#define sandybridge_pcode_write(dev_priv, mbox, val) \
3455 sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
3456
3457int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
3458 u32 reply_mask, u32 reply, int timeout_base_ms);
3459
3460
3461u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3462int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3463u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3464u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
3465void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3466u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3467void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3468u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3469void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3470u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3471void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3472u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3473void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3474u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3475 enum intel_sbi_destination destination);
3476void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3477 enum intel_sbi_destination destination);
3478u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3479void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3480
3481
3482void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3483 enum dpio_phy *phy, enum dpio_channel *ch);
3484void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
3485 enum port port, u32 margin, u32 scale,
3486 u32 enable, u32 deemphasis);
3487void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3488void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
3489bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
3490 enum dpio_phy phy);
3491bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
3492 enum dpio_phy phy);
3493uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3494void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
3495 uint8_t lane_lat_optim_mask);
3496uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
3497
3498void chv_set_phy_signal_level(struct intel_encoder *encoder,
3499 u32 deemph_reg_value, u32 margin_reg_value,
3500 bool uniq_trans_scale);
3501void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3502 const struct intel_crtc_state *crtc_state,
3503 bool reset);
3504void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
3505 const struct intel_crtc_state *crtc_state);
3506void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3507 const struct intel_crtc_state *crtc_state);
3508void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3509void chv_phy_post_pll_disable(struct intel_encoder *encoder,
3510 const struct intel_crtc_state *old_crtc_state);
3511
3512void vlv_set_phy_signal_level(struct intel_encoder *encoder,
3513 u32 demph_reg_value, u32 preemph_reg_value,
3514 u32 uniqtranscale_reg_value, u32 tx3_demph);
3515void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
3516 const struct intel_crtc_state *crtc_state);
3517void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
3518 const struct intel_crtc_state *crtc_state);
3519void vlv_phy_reset_lanes(struct intel_encoder *encoder,
3520 const struct intel_crtc_state *old_crtc_state);
3521
3522int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3523int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3524u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3525 const i915_reg_t reg);
3526
3527u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
3528
3529static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
3530 const i915_reg_t reg)
3531{
3532 return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
3533}
3534
3535#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3536#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3537
3538#define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3539#define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3540#define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3541#define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3542
3543#define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3544#define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3545#define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3546#define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3547
3548
3549
3550
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562#define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3563
3564#define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3565 u32 upper, lower, old_upper, loop = 0; \
3566 upper = I915_READ(upper_reg); \
3567 do { \
3568 old_upper = upper; \
3569 lower = I915_READ(lower_reg); \
3570 upper = I915_READ(upper_reg); \
3571 } while (upper != old_upper && loop++ < 2); \
3572 (u64)upper << 32 | lower; })
3573
3574#define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3575#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3576
3577#define __raw_read(x, s) \
3578static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3579 i915_reg_t reg) \
3580{ \
3581 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3582}
3583
3584#define __raw_write(x, s) \
3585static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3586 i915_reg_t reg, uint##x##_t val) \
3587{ \
3588 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3589}
3590__raw_read(8, b)
3591__raw_read(16, w)
3592__raw_read(32, l)
3593__raw_read(64, q)
3594
3595__raw_write(8, b)
3596__raw_write(16, w)
3597__raw_write(32, l)
3598__raw_write(64, q)
3599
3600#undef __raw_read
3601#undef __raw_write
3602
3603
3604
3605
3606
3607
3608
3609
3610
3611
3612
3613
3614
3615
3616
3617
3618
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3630#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3631#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3632#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3633
3634
3635#define INTEL_BROADCAST_RGB_AUTO 0
3636#define INTEL_BROADCAST_RGB_FULL 1
3637#define INTEL_BROADCAST_RGB_LIMITED 2
3638
3639static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3640{
3641 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3642 return VLV_VGACNTRL;
3643 else if (INTEL_GEN(dev_priv) >= 5)
3644 return CPU_VGACNTRL;
3645 else
3646 return VGACNTRL;
3647}
3648
3649static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3650{
3651 unsigned long j = msecs_to_jiffies(m);
3652
3653 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3654}
3655
3656static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3657{
3658
3659 if (NSEC_PER_SEC % HZ &&
3660 div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
3661 return MAX_JIFFY_OFFSET;
3662
3663 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3664}
3665
3666
3667
3668
3669
3670
3671
3672static inline void
3673wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3674{
3675 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3676
3677
3678
3679
3680
3681 tmp_jiffies = jiffies;
3682 target_jiffies = timestamp_jiffies +
3683 msecs_to_jiffies_timeout(to_wait_ms);
3684
3685 if (time_after(target_jiffies, tmp_jiffies)) {
3686 remaining_jiffies = target_jiffies - tmp_jiffies;
3687 while (remaining_jiffies)
3688 remaining_jiffies =
3689 schedule_timeout_uninterruptible(remaining_jiffies);
3690 }
3691}
3692
3693static inline bool
3694__i915_request_irq_complete(const struct i915_request *rq)
3695{
3696 struct intel_engine_cs *engine = rq->engine;
3697 u32 seqno;
3698
3699
3700
3701
3702
3703
3704
3705 if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags))
3706 return true;
3707
3708
3709
3710
3711
3712
3713
3714 seqno = i915_request_global_seqno(rq);
3715 if (!seqno)
3716 return false;
3717
3718
3719
3720
3721 if (__i915_request_completed(rq, seqno))
3722 return true;
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735 if (engine->irq_seqno_barrier &&
3736 test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
3737 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749
3750
3751 engine->irq_seqno_barrier(engine);
3752
3753
3754
3755
3756
3757
3758
3759 spin_lock_irq(&b->irq_lock);
3760 if (b->irq_wait && b->irq_wait->tsk != current)
3761
3762
3763
3764
3765
3766
3767 wake_up_process(b->irq_wait->tsk);
3768 spin_unlock_irq(&b->irq_lock);
3769
3770 if (__i915_request_completed(rq, seqno))
3771 return true;
3772 }
3773
3774 return false;
3775}
3776
3777void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
3778bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);
3779
3780
3781
3782
3783
3784
3785
3786
3787
3788
3789
3790#define i915_can_memcpy_from_wc(dst, src, len) \
3791 i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)
3792
3793#define i915_has_memcpy_from_wc() \
3794 i915_memcpy_from_wc(NULL, NULL, 0)
3795
3796
3797int remap_io_mapping(struct vm_area_struct *vma,
3798 unsigned long addr, unsigned long pfn, unsigned long size,
3799 struct io_mapping *iomap);
3800
3801static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
3802{
3803 if (INTEL_GEN(i915) >= 10)
3804 return CNL_HWS_CSB_WRITE_INDEX;
3805 else
3806 return I915_HWS_CSB_WRITE_INDEX;
3807}
3808
3809#endif
3810