LXR linux/drivers/i2c/busses/i2c-sh

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * SuperH Mobile I2C Controller
   4 *
   5 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   6 *
   7 * Copyright (C) 2008 Magnus Damm
   8 *
   9 * Portions of the code based on out-of-tree driver i2c-sh7343.c
  10 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  11 */
  12
  13#include <linux/clk.h>
  14#include <linux/delay.h>
  15#include <linux/dmaengine.h>
  16#include <linux/dma-mapping.h>
  17#include <linux/err.h>
  18#include <linux/i2c.h>
  19#include <linux/init.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/kernel.h>
  23#include <linux/module.h>
  24#include <linux/of_device.h>
  25#include <linux/platform_device.h>
  26#include <linux/pm_runtime.h>
  27#include <linux/slab.h>
  28
  29/* Transmit operation:                                                      */
  30/*                                                                          */
  31/* 0 byte transmit                                                          */
  32/* BUS:     S     A8     ACK   P(*)                                         */
  33/* IRQ:       DTE   WAIT                                                    */
  34/* ICIC:                                                                    */
  35/* ICCR: 0x94       0x90                                                    */
  36/* ICDR:      A8                                                            */
  37/*                                                                          */
  38/* 1 byte transmit                                                          */
  39/* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  40/* IRQ:       DTE   WAIT         WAIT                                       */
  41/* ICIC:      -DTE                                                          */
  42/* ICCR: 0x94                    0x90                                       */
  43/* ICDR:      A8    D8(1)                                                   */
  44/*                                                                          */
  45/* 2 byte transmit                                                          */
  46/* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  47/* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  48/* ICIC:      -DTE                                                          */
  49/* ICCR: 0x94                                  0x90                         */
  50/* ICDR:      A8    D8(1)        D8(2)                                      */
  51/*                                                                          */
  52/* 3 bytes or more, +---------+ gets repeated                               */
  53/*                                                                          */
  54/*                                                                          */
  55/* Receive operation:                                                       */
  56/*                                                                          */
  57/* 0 byte receive - not supported since slave may hold SDA low              */
  58/*                                                                          */
  59/* 1 byte receive       [TX] | [RX]                                         */
  60/* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  61/* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  62/* ICIC:      -DTE           |   +DTE                                       */
  63/* ICCR: 0x94       0x81     |   0xc0                                       */
  64/* ICDR:      A8             |            D8(1)                             */
  65/*                                                                          */
  66/* 2 byte receive        [TX]| [RX]                                         */
  67/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  68/* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  69/* ICIC:      -DTE           |                 +DTE                         */
  70/* ICCR: 0x94       0x81     |                 0xc0                         */
  71/* ICDR:      A8             |                 D8(1)    D8(2)               */
  72/*                                                                          */
  73/* 3 byte receive       [TX] | [RX]                                     (*) */
  74/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  75/* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  76/* ICIC:      -DTE           |                              +DTE            */
  77/* ICCR: 0x94       0x81     |                              0xc0            */
  78/* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  79/*                                                                          */
  80/* 4 bytes or more, this part is repeated    +---------+                    */
  81/*                                                                          */
  82/*                                                                          */
  83/* Interrupt order and BUSY flag                                            */
  84/*     ___                                                 _                */
  85/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  86/* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  87/*                                                                          */
  88/*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  89/*                                           ___                            */
  90/* WAIT IRQ ________________________________/   \___________                */
  91/* TACK IRQ ____________________________________/   \_______                */
  92/* DTE  IRQ __________________________________________/   \_                */
  93/* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
  94/*         _______________________________________________                  */
  95/* BUSY __/                                               \_                */
  96/*                                                                          */
  97/* (*) The STOP condition is only sent by the master at the end of the last */
  98/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
  99/* only cleared after the STOP condition, so, between messages we have to   */
 100/* poll for the DTE bit.                                                    */
 101/*                                                                          */
 102
 103enum sh_mobile_i2c_op {
 104        OP_START = 0,
 105        OP_TX_FIRST,
 106        OP_TX,
 107        OP_TX_STOP,
 108        OP_TX_TO_RX,
 109        OP_RX,
 110        OP_RX_STOP,
 111        OP_RX_STOP_DATA,
 112};
 113
 114struct sh_mobile_i2c_data {
 115        struct device *dev;
 116        void __iomem *reg;
 117        struct i2c_adapter adap;
 118        unsigned long bus_speed;
 119        unsigned int clks_per_count;
 120        struct clk *clk;
 121        u_int8_t icic;
 122        u_int8_t flags;
 123        u_int16_t iccl;
 124        u_int16_t icch;
 125
 126        spinlock_t lock;
 127        wait_queue_head_t wait;
 128        struct i2c_msg *msg;
 129        int pos;
 130        int sr;
 131        bool send_stop;
 132        bool stop_after_dma;
 133
 134        struct resource *res;
 135        struct dma_chan *dma_tx;
 136        struct dma_chan *dma_rx;
 137        struct scatterlist sg;
 138        enum dma_data_direction dma_direction;
 139        u8 *dma_buf;
 140};
 141
 142struct sh_mobile_dt_config {
 143        int clks_per_count;
 144        int (*setup)(struct sh_mobile_i2c_data *pd);
 145};
 146
 147#define IIC_FLAG_HAS_ICIC67     (1 << 0)
 148
 149#define STANDARD_MODE           100000
 150#define FAST_MODE               400000
 151
 152/* Register offsets */
 153#define ICDR                    0x00
 154#define ICCR                    0x04
 155#define ICSR                    0x08
 156#define ICIC                    0x0c
 157#define ICCL                    0x10
 158#define ICCH                    0x14
 159#define ICSTART                 0x70
 160
 161/* Register bits */
 162#define ICCR_ICE                0x80
 163#define ICCR_RACK               0x40
 164#define ICCR_TRS                0x10
 165#define ICCR_BBSY               0x04
 166#define ICCR_SCP                0x01
 167
 168#define ICSR_SCLM               0x80
 169#define ICSR_SDAM               0x40
 170#define SW_DONE                 0x20
 171#define ICSR_BUSY               0x10
 172#define ICSR_AL                 0x08
 173#define ICSR_TACK               0x04
 174#define ICSR_WAIT               0x02
 175#define ICSR_DTE                0x01
 176
 177#define ICIC_ICCLB8             0x80
 178#define ICIC_ICCHB8             0x40
 179#define ICIC_TDMAE              0x20
 180#define ICIC_RDMAE              0x10
 181#define ICIC_ALE                0x08
 182#define ICIC_TACKE              0x04
 183#define ICIC_WAITE              0x02
 184#define ICIC_DTEE               0x01
 185
 186#define ICSTART_ICSTART         0x10
 187
 188static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 189{
 190        if (offs == ICIC)
 191                data |= pd->icic;
 192
 193        iowrite8(data, pd->reg + offs);
 194}
 195
 196static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 197{
 198        return ioread8(pd->reg + offs);
 199}
 200
 201static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 202                        unsigned char set, unsigned char clr)
 203{
 204        iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 205}
 206
 207static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 208{
 209        /*
 210         * Conditional expression:
 211         *   ICCL >= COUNT_CLK * (tLOW + tf)
 212         *
 213         * SH-Mobile IIC hardware starts counting the LOW period of
 214         * the SCL signal (tLOW) as soon as it pulls the SCL line.
 215         * In order to meet the tLOW timing spec, we need to take into
 216         * account the fall time of SCL signal (tf).  Default tf value
 217         * should be 0.3 us, for safety.
 218         */
 219        return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 220}
 221
 222static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 223{
 224        /*
 225         * Conditional expression:
 226         *   ICCH >= COUNT_CLK * (tHIGH + tf)
 227         *
 228         * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 229         * and can ignore it.  SH-Mobile IIC controller starts counting
 230         * the HIGH period of the SCL signal (tHIGH) after the SCL input
 231         * voltage increases at VIH.
 232         *
 233         * Afterward it turned out calculating ICCH using only tHIGH spec
 234         * will result in violation of the tHD;STA timing spec.  We need
 235         * to take into account the fall time of SDA signal (tf) at START
 236         * condition, in order to meet both tHIGH and tHD;STA specs.
 237         */
 238        return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 239}
 240
 241static int sh_mobile_i2c_check_timing(struct sh_mobile_i2c_data *pd)
 242{
 243        u16 max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 244
 245        if (pd->iccl > max_val || pd->icch > max_val) {
 246                dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 247                        pd->iccl, pd->icch);
 248                return -EINVAL;
 249        }
 250
 251        /* one more bit of ICCL in ICIC */
 252        if (pd->iccl & 0x100)
 253                pd->icic |= ICIC_ICCLB8;
 254        else
 255                pd->icic &= ~ICIC_ICCLB8;
 256
 257        /* one more bit of ICCH in ICIC */
 258        if (pd->icch & 0x100)
 259                pd->icic |= ICIC_ICCHB8;
 260        else
 261                pd->icic &= ~ICIC_ICCHB8;
 262
 263        dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 264        return 0;
 265}
 266
 267static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 268{
 269        unsigned long i2c_clk_khz;
 270        u32 tHIGH, tLOW, tf;
 271
 272        i2c_clk_khz = clk_get_rate(pd->clk) / 1000 / pd->clks_per_count;
 273
 274        if (pd->bus_speed == STANDARD_MODE) {
 275                tLOW    = 47;   /* tLOW = 4.7 us */
 276                tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 277                tf      = 3;    /* tf = 0.3 us */
 278        } else if (pd->bus_speed == FAST_MODE) {
 279                tLOW    = 13;   /* tLOW = 1.3 us */
 280                tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 281                tf      = 3;    /* tf = 0.3 us */
 282        } else {
 283                dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 284                        pd->bus_speed);
 285                return -EINVAL;
 286        }
 287
 288        pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 289        pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 290
 291        return sh_mobile_i2c_check_timing(pd);
 292}
 293
 294static int sh_mobile_i2c_v2_init(struct sh_mobile_i2c_data *pd)
 295{
 296        unsigned long clks_per_cycle;
 297
 298        /* L = 5, H = 4, L + H = 9 */
 299        clks_per_cycle = clk_get_rate(pd->clk) / pd->bus_speed;
 300        pd->iccl = DIV_ROUND_UP(clks_per_cycle * 5 / 9 - 1, pd->clks_per_count);
 301        pd->icch = DIV_ROUND_UP(clks_per_cycle * 4 / 9 - 5, pd->clks_per_count);
 302
 303        return sh_mobile_i2c_check_timing(pd);
 304}
 305
 306static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 307                            enum sh_mobile_i2c_op op, unsigned char data)
 308{
 309        unsigned char ret = 0;
 310        unsigned long flags;
 311
 312        dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 313
 314        spin_lock_irqsave(&pd->lock, flags);
 315
 316        switch (op) {
 317        case OP_START: /* issue start and trigger DTE interrupt */
 318                iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 319                break;
 320        case OP_TX_FIRST: /* disable DTE interrupt and write data */
 321                iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 322                iic_wr(pd, ICDR, data);
 323                break;
 324        case OP_TX: /* write data */
 325                iic_wr(pd, ICDR, data);
 326                break;
 327        case OP_TX_STOP: /* issue a stop (or rep_start) */
 328                iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 329                                               : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 330                break;
 331        case OP_TX_TO_RX: /* select read mode */
 332                iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 333                break;
 334        case OP_RX: /* just read data */
 335                ret = iic_rd(pd, ICDR);
 336                break;
 337        case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 338                iic_wr(pd, ICIC,
 339                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 340                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 341                break;
 342        case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 343                iic_wr(pd, ICIC,
 344                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 345                ret = iic_rd(pd, ICDR);
 346                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 347                break;
 348        }
 349
 350        spin_unlock_irqrestore(&pd->lock, flags);
 351
 352        dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 353        return ret;
 354}
 355
 356static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 357{
 358        return pd->pos == -1;
 359}
 360
 361static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 362                                   unsigned char *buf)
 363{
 364        switch (pd->pos) {
 365        case -1:
 366                *buf = i2c_8bit_addr_from_msg(pd->msg);
 367                break;
 368        default:
 369                *buf = pd->msg->buf[pd->pos];
 370        }
 371}
 372
 373static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 374{
 375        unsigned char data;
 376
 377        if (pd->pos == pd->msg->len) {
 378                i2c_op(pd, OP_TX_STOP, 0);
 379                return 1;
 380        }
 381
 382        sh_mobile_i2c_get_data(pd, &data);
 383        i2c_op(pd, sh_mobile_i2c_is_first_byte(pd) ? OP_TX_FIRST : OP_TX, data);
 384
 385        pd->pos++;
 386        return 0;
 387}
 388
 389static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 390{
 391        unsigned char data;
 392        int real_pos;
 393
 394        do {
 395                if (pd->pos <= -1) {
 396                        sh_mobile_i2c_get_data(pd, &data);
 397
 398                        if (sh_mobile_i2c_is_first_byte(pd))
 399                                i2c_op(pd, OP_TX_FIRST, data);
 400                        else
 401                                i2c_op(pd, OP_TX, data);
 402                        break;
 403                }
 404
 405                if (pd->pos == 0) {
 406                        i2c_op(pd, OP_TX_TO_RX, 0);
 407                        break;
 408                }
 409
 410                real_pos = pd->pos - 2;
 411
 412                if (pd->pos == pd->msg->len) {
 413                        if (pd->stop_after_dma) {
 414                                /* Simulate PIO end condition after DMA transfer */
 415                                i2c_op(pd, OP_RX_STOP, 0);
 416                                pd->pos++;
 417                                break;
 418                        }
 419
 420                        if (real_pos < 0) {
 421                                i2c_op(pd, OP_RX_STOP, 0);
 422                                break;
 423                        }
 424                        data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 425                } else if (real_pos >= 0) {
 426                        data = i2c_op(pd, OP_RX, 0);
 427                }
 428
 429                if (real_pos >= 0)
 430                        pd->msg->buf[real_pos] = data;
 431        } while (0);
 432
 433        pd->pos++;
 434        return pd->pos == (pd->msg->len + 2);
 435}
 436
 437static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 438{
 439        struct sh_mobile_i2c_data *pd = dev_id;
 440        unsigned char sr;
 441        int wakeup = 0;
 442
 443        sr = iic_rd(pd, ICSR);
 444        pd->sr |= sr; /* remember state */
 445
 446        dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 447               (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 448               pd->pos, pd->msg->len);
 449
 450        /* Kick off TxDMA after preface was done */
 451        if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 452                iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 453        else if (sr & (ICSR_AL | ICSR_TACK))
 454                /* don't interrupt transaction - continue to issue stop */
 455                iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 456        else if (pd->msg->flags & I2C_M_RD)
 457                wakeup = sh_mobile_i2c_isr_rx(pd);
 458        else
 459                wakeup = sh_mobile_i2c_isr_tx(pd);
 460
 461        /* Kick off RxDMA after preface was done */
 462        if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 463                iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 464
 465        if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 466                iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 467
 468        if (wakeup) {
 469                pd->sr |= SW_DONE;
 470                wake_up(&pd->wait);
 471        }
 472
 473        /* defeat write posting to avoid spurious WAIT interrupts */
 474        iic_rd(pd, ICSR);
 475
 476        return IRQ_HANDLED;
 477}
 478
 479static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 480{
 481        struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 482                                ? pd->dma_rx : pd->dma_tx;
 483
 484        dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 485                         pd->msg->len, pd->dma_direction);
 486
 487        pd->dma_direction = DMA_NONE;
 488}
 489
 490static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 491{
 492        if (pd->dma_direction == DMA_NONE)
 493                return;
 494        else if (pd->dma_direction == DMA_FROM_DEVICE)
 495                dmaengine_terminate_all(pd->dma_rx);
 496        else if (pd->dma_direction == DMA_TO_DEVICE)
 497                dmaengine_terminate_all(pd->dma_tx);
 498
 499        sh_mobile_i2c_dma_unmap(pd);
 500}
 501
 502static void sh_mobile_i2c_dma_callback(void *data)
 503{
 504        struct sh_mobile_i2c_data *pd = data;
 505
 506        sh_mobile_i2c_dma_unmap(pd);
 507        pd->pos = pd->msg->len;
 508        pd->stop_after_dma = true;
 509
 510        iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 511}
 512
 513static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 514                                enum dma_transfer_direction dir, dma_addr_t port_addr)
 515{
 516        struct dma_chan *chan;
 517        struct dma_slave_config cfg;
 518        char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 519        int ret;
 520
 521        chan = dma_request_slave_channel_reason(dev, chan_name);
 522        if (IS_ERR(chan)) {
 523                dev_dbg(dev, "request_channel failed for %s (%ld)\n", chan_name,
 524                        PTR_ERR(chan));
 525                return chan;
 526        }
 527
 528        memset(&cfg, 0, sizeof(cfg));
 529        cfg.direction = dir;
 530        if (dir == DMA_MEM_TO_DEV) {
 531                cfg.dst_addr = port_addr;
 532                cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 533        } else {
 534                cfg.src_addr = port_addr;
 535                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 536        }
 537
 538        ret = dmaengine_slave_config(chan, &cfg);
 539        if (ret) {
 540                dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 541                dma_release_channel(chan);
 542                return ERR_PTR(ret);
 543        }
 544
 545        dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 546        return chan;
 547}
 548
 549static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 550{
 551        bool read = pd->msg->flags & I2C_M_RD;
 552        enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 553        struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 554        struct dma_async_tx_descriptor *txdesc;
 555        dma_addr_t dma_addr;
 556        dma_cookie_t cookie;
 557
 558        if (PTR_ERR(chan) == -EPROBE_DEFER) {
 559                if (read)
 560                        chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 561                                                                           pd->res->start + ICDR);
 562                else
 563                        chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 564                                                                           pd->res->start + ICDR);
 565        }
 566
 567        if (IS_ERR(chan))
 568                return;
 569
 570        dma_addr = dma_map_single(chan->device->dev, pd->dma_buf, pd->msg->len, dir);
 571        if (dma_mapping_error(chan->device->dev, dma_addr)) {
 572                dev_dbg(pd->dev, "dma map failed, using PIO\n");
 573                return;
 574        }
 575
 576        sg_dma_len(&pd->sg) = pd->msg->len;
 577        sg_dma_address(&pd->sg) = dma_addr;
 578
 579        pd->dma_direction = dir;
 580
 581        txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 582                                         read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 583                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 584        if (!txdesc) {
 585                dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 586                sh_mobile_i2c_cleanup_dma(pd);
 587                return;
 588        }
 589
 590        txdesc->callback = sh_mobile_i2c_dma_callback;
 591        txdesc->callback_param = pd;
 592
 593        cookie = dmaengine_submit(txdesc);
 594        if (dma_submit_error(cookie)) {
 595                dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 596                sh_mobile_i2c_cleanup_dma(pd);
 597                return;
 598        }
 599
 600        dma_async_issue_pending(chan);
 601}
 602
 603static void start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 604                     bool do_init)
 605{
 606        if (do_init) {
 607                /* Initialize channel registers */
 608                iic_wr(pd, ICCR, ICCR_SCP);
 609
 610                /* Enable channel and configure rx ack */
 611                iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 612
 613                /* Set the clock */
 614                iic_wr(pd, ICCL, pd->iccl & 0xff);
 615                iic_wr(pd, ICCH, pd->icch & 0xff);
 616        }
 617
 618        pd->msg = usr_msg;
 619        pd->pos = -1;
 620        pd->sr = 0;
 621
 622        pd->dma_buf = i2c_get_dma_safe_msg_buf(pd->msg, 8);
 623        if (pd->dma_buf)
 624                sh_mobile_i2c_xfer_dma(pd);
 625
 626        /* Enable all interrupts to begin with */
 627        iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 628}
 629
 630static int poll_dte(struct sh_mobile_i2c_data *pd)
 631{
 632        int i;
 633
 634        for (i = 1000; i; i--) {
 635                u_int8_t val = iic_rd(pd, ICSR);
 636
 637                if (val & ICSR_DTE)
 638                        break;
 639
 640                if (val & ICSR_TACK)
 641                        return -ENXIO;
 642
 643                udelay(10);
 644        }
 645
 646        return i ? 0 : -ETIMEDOUT;
 647}
 648
 649static int poll_busy(struct sh_mobile_i2c_data *pd)
 650{
 651        int i;
 652
 653        for (i = 1000; i; i--) {
 654                u_int8_t val = iic_rd(pd, ICSR);
 655
 656                dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 657
 658                /* the interrupt handler may wake us up before the
 659                 * transfer is finished, so poll the hardware
 660                 * until we're done.
 661                 */
 662                if (!(val & ICSR_BUSY)) {
 663                        /* handle missing acknowledge and arbitration lost */
 664                        val |= pd->sr;
 665                        if (val & ICSR_TACK)
 666                                return -ENXIO;
 667                        if (val & ICSR_AL)
 668                                return -EAGAIN;
 669                        break;
 670                }
 671
 672                udelay(10);
 673        }
 674
 675        return i ? 0 : -ETIMEDOUT;
 676}
 677
 678static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 679                              struct i2c_msg *msgs,
 680                              int num)
 681{
 682        struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 683        struct i2c_msg  *msg;
 684        int err = 0;
 685        int i;
 686        long timeout;
 687
 688        /* Wake up device and enable clock */
 689        pm_runtime_get_sync(pd->dev);
 690
 691        /* Process all messages */
 692        for (i = 0; i < num; i++) {
 693                bool do_start = pd->send_stop || !i;
 694                msg = &msgs[i];
 695                pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 696                pd->stop_after_dma = false;
 697
 698                start_ch(pd, msg, do_start);
 699
 700                if (do_start)
 701                        i2c_op(pd, OP_START, 0);
 702
 703                /* The interrupt handler takes care of the rest... */
 704                timeout = wait_event_timeout(pd->wait,
 705                                       pd->sr & (ICSR_TACK | SW_DONE),
 706                                       adapter->timeout);
 707
 708                /* 'stop_after_dma' tells if DMA transfer was complete */
 709                i2c_put_dma_safe_msg_buf(pd->dma_buf, pd->msg, pd->stop_after_dma);
 710
 711                if (!timeout) {
 712                        dev_err(pd->dev, "Transfer request timed out\n");
 713                        if (pd->dma_direction != DMA_NONE)
 714                                sh_mobile_i2c_cleanup_dma(pd);
 715
 716                        err = -ETIMEDOUT;
 717                        break;
 718                }
 719
 720                if (pd->send_stop)
 721                        err = poll_busy(pd);
 722                else
 723                        err = poll_dte(pd);
 724                if (err < 0)
 725                        break;
 726        }
 727
 728        /* Disable channel */
 729        iic_wr(pd, ICCR, ICCR_SCP);
 730
 731        /* Disable clock and mark device as idle */
 732        pm_runtime_put_sync(pd->dev);
 733
 734        return err ?: num;
 735}
 736
 737static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 738{
 739        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 740}
 741
 742static const struct i2c_algorithm sh_mobile_i2c_algorithm = {
 743        .functionality  = sh_mobile_i2c_func,
 744        .master_xfer    = sh_mobile_i2c_xfer,
 745};
 746
 747static const struct i2c_adapter_quirks sh_mobile_i2c_quirks = {
 748        .flags = I2C_AQ_NO_ZERO_LEN_READ,
 749};
 750
 751/*
 752 * r8a7740 chip has lasting errata on I2C I/O pad reset.
 753 * this is work-around for it.
 754 */
 755static int sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 756{
 757        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 758        iic_rd(pd, ICCR); /* dummy read */
 759
 760        iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 761        iic_rd(pd, ICSTART); /* dummy read */
 762
 763        udelay(10);
 764
 765        iic_wr(pd, ICCR, ICCR_SCP);
 766        iic_wr(pd, ICSTART, 0);
 767
 768        udelay(10);
 769
 770        iic_wr(pd, ICCR, ICCR_TRS);
 771        udelay(10);
 772        iic_wr(pd, ICCR, 0);
 773        udelay(10);
 774        iic_wr(pd, ICCR, ICCR_TRS);
 775        udelay(10);
 776
 777        return sh_mobile_i2c_init(pd);
 778}
 779
 780static const struct sh_mobile_dt_config default_dt_config = {
 781        .clks_per_count = 1,
 782        .setup = sh_mobile_i2c_init,
 783};
 784
 785static const struct sh_mobile_dt_config fast_clock_dt_config = {
 786        .clks_per_count = 2,
 787        .setup = sh_mobile_i2c_init,
 788};
 789
 790static const struct sh_mobile_dt_config v2_freq_calc_dt_config = {
 791        .clks_per_count = 2,
 792        .setup = sh_mobile_i2c_v2_init,
 793};
 794
 795static const struct sh_mobile_dt_config r8a7740_dt_config = {
 796        .clks_per_count = 1,
 797        .setup = sh_mobile_i2c_r8a7740_workaround,
 798};
 799
 800static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 801        { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 802        { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 803        { .compatible = "renesas,iic-r8a7790", .data = &v2_freq_calc_dt_config },
 804        { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 805        { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 806        { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 807        { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 808        { .compatible = "renesas,rcar-gen2-iic", .data = &fast_clock_dt_config },
 809        { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
 810        { .compatible = "renesas,rcar-gen3-iic", .data = &fast_clock_dt_config },
 811        { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 812        { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 813        {},
 814};
 815MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 816
 817static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 818{
 819        if (!IS_ERR(pd->dma_tx)) {
 820                dma_release_channel(pd->dma_tx);
 821                pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 822        }
 823
 824        if (!IS_ERR(pd->dma_rx)) {
 825                dma_release_channel(pd->dma_rx);
 826                pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 827        }
 828}
 829
 830static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 831{
 832        struct resource *res;
 833        resource_size_t n;
 834        int k = 0, ret;
 835
 836        while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 837                for (n = res->start; n <= res->end; n++) {
 838                        ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 839                                          0, dev_name(&dev->dev), pd);
 840                        if (ret) {
 841                                dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 842                                return ret;
 843                        }
 844                }
 845                k++;
 846        }
 847
 848        return k > 0 ? 0 : -ENOENT;
 849}
 850
 851static int sh_mobile_i2c_probe(struct platform_device *dev)
 852{
 853        struct sh_mobile_i2c_data *pd;
 854        struct i2c_adapter *adap;
 855        struct resource *res;
 856        const struct sh_mobile_dt_config *config;
 857        int ret;
 858        u32 bus_speed;
 859
 860        pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 861        if (!pd)
 862                return -ENOMEM;
 863
 864        pd->clk = devm_clk_get(&dev->dev, NULL);
 865        if (IS_ERR(pd->clk)) {
 866                dev_err(&dev->dev, "cannot get clock\n");
 867                return PTR_ERR(pd->clk);
 868        }
 869
 870        ret = sh_mobile_i2c_hook_irqs(dev, pd);
 871        if (ret)
 872                return ret;
 873
 874        pd->dev = &dev->dev;
 875        platform_set_drvdata(dev, pd);
 876
 877        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 878
 879        pd->res = res;
 880        pd->reg = devm_ioremap_resource(&dev->dev, res);
 881        if (IS_ERR(pd->reg))
 882                return PTR_ERR(pd->reg);
 883
 884        ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 885        pd->bus_speed = (ret || !bus_speed) ? STANDARD_MODE : bus_speed;
 886        pd->clks_per_count = 1;
 887
 888        /* Newer variants come with two new bits in ICIC */
 889        if (resource_size(res) > 0x17)
 890                pd->flags |= IIC_FLAG_HAS_ICIC67;
 891
 892        pm_runtime_enable(&dev->dev);
 893        pm_runtime_get_sync(&dev->dev);
 894
 895        config = of_device_get_match_data(&dev->dev);
 896        if (config) {
 897                pd->clks_per_count = config->clks_per_count;
 898                ret = config->setup(pd);
 899        } else {
 900                ret = sh_mobile_i2c_init(pd);
 901        }
 902
 903        pm_runtime_put_sync(&dev->dev);
 904        if (ret)
 905                return ret;
 906
 907        /* Init DMA */
 908        sg_init_table(&pd->sg, 1);
 909        pd->dma_direction = DMA_NONE;
 910        pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 911
 912        /* setup the private data */
 913        adap = &pd->adap;
 914        i2c_set_adapdata(adap, pd);
 915
 916        adap->owner = THIS_MODULE;
 917        adap->algo = &sh_mobile_i2c_algorithm;
 918        adap->quirks = &sh_mobile_i2c_quirks;
 919        adap->dev.parent = &dev->dev;
 920        adap->retries = 5;
 921        adap->nr = dev->id;
 922        adap->dev.of_node = dev->dev.of_node;
 923
 924        strlcpy(adap->name, dev->name, sizeof(adap->name));
 925
 926        spin_lock_init(&pd->lock);
 927        init_waitqueue_head(&pd->wait);
 928
 929        ret = i2c_add_numbered_adapter(adap);
 930        if (ret < 0) {
 931                sh_mobile_i2c_release_dma(pd);
 932                return ret;
 933        }
 934
 935        dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 936
 937        return 0;
 938}
 939
 940static int sh_mobile_i2c_remove(struct platform_device *dev)
 941{
 942        struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 943
 944        i2c_del_adapter(&pd->adap);
 945        sh_mobile_i2c_release_dma(pd);
 946        pm_runtime_disable(&dev->dev);
 947        return 0;
 948}
 949
 950static int sh_mobile_i2c_runtime_nop(struct device *dev)
 951{
 952        /* Runtime PM callback shared between ->runtime_suspend()
 953         * and ->runtime_resume(). Simply returns success.
 954         *
 955         * This driver re-initializes all registers after
 956         * pm_runtime_get_sync() anyway so there is no need
 957         * to save and restore registers here.
 958         */
 959        return 0;
 960}
 961
 962static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
 963        .runtime_suspend = sh_mobile_i2c_runtime_nop,
 964        .runtime_resume = sh_mobile_i2c_runtime_nop,
 965};
 966
 967static struct platform_driver sh_mobile_i2c_driver = {
 968        .driver         = {
 969                .name           = "i2c-sh_mobile",
 970                .pm             = &sh_mobile_i2c_dev_pm_ops,
 971                .of_match_table = sh_mobile_i2c_dt_ids,
 972        },
 973        .probe          = sh_mobile_i2c_probe,
 974        .remove         = sh_mobile_i2c_remove,
 975};
 976
 977static int __init sh_mobile_i2c_adap_init(void)
 978{
 979        return platform_driver_register(&sh_mobile_i2c_driver);
 980}
 981subsys_initcall(sh_mobile_i2c_adap_init);
 982
 983static void __exit sh_mobile_i2c_adap_exit(void)
 984{
 985        platform_driver_unregister(&sh_mobile_i2c_driver);
 986}
 987module_exit(sh_mobile_i2c_adap_exit);
 988
 989MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
 990MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
 991MODULE_LICENSE("GPL v2");
 992MODULE_ALIAS("platform:i2c-sh_mobile");
 993