linux/drivers/media/usb/pvrusb2/pvrusb2-hdw.c
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   1/*
   2 *
   3 *
   4 *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5 *
   6 *  This program is free software; you can redistribute it and/or modify
   7 *  it under the terms of the GNU General Public License as published by
   8 *  the Free Software Foundation; either version 2 of the License
   9 *
  10 *  This program is distributed in the hope that it will be useful,
  11 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 *  GNU General Public License for more details.
  14 *
  15 */
  16
  17#include <linux/errno.h>
  18#include <linux/string.h>
  19#include <linux/slab.h>
  20#include <linux/module.h>
  21#include <linux/firmware.h>
  22#include <linux/videodev2.h>
  23#include <media/v4l2-common.h>
  24#include <media/tuner.h>
  25#include "pvrusb2.h"
  26#include "pvrusb2-std.h"
  27#include "pvrusb2-util.h"
  28#include "pvrusb2-hdw.h"
  29#include "pvrusb2-i2c-core.h"
  30#include "pvrusb2-eeprom.h"
  31#include "pvrusb2-hdw-internal.h"
  32#include "pvrusb2-encoder.h"
  33#include "pvrusb2-debug.h"
  34#include "pvrusb2-fx2-cmd.h"
  35#include "pvrusb2-wm8775.h"
  36#include "pvrusb2-video-v4l.h"
  37#include "pvrusb2-cx2584x-v4l.h"
  38#include "pvrusb2-cs53l32a.h"
  39#include "pvrusb2-audio.h"
  40
  41#define TV_MIN_FREQ     55250000L
  42#define TV_MAX_FREQ    850000000L
  43
  44/* This defines a minimum interval that the decoder must remain quiet
  45   before we are allowed to start it running. */
  46#define TIME_MSEC_DECODER_WAIT 50
  47
  48/* This defines a minimum interval that the decoder must be allowed to run
  49   before we can safely begin using its streaming output. */
  50#define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  51
  52/* This defines a minimum interval that the encoder must remain quiet
  53   before we are allowed to configure it. */
  54#define TIME_MSEC_ENCODER_WAIT 50
  55
  56/* This defines the minimum interval that the encoder must successfully run
  57   before we consider that the encoder has run at least once since its
  58   firmware has been loaded.  This measurement is in important for cases
  59   where we can't do something until we know that the encoder has been run
  60   at least once. */
  61#define TIME_MSEC_ENCODER_OK 250
  62
  63static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  64static DEFINE_MUTEX(pvr2_unit_mtx);
  65
  66static int ctlchg;
  67static int procreload;
  68static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  69static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  70static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  71static int init_pause_msec;
  72
  73module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  74MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  75module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  76MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  77module_param(procreload, int, S_IRUGO|S_IWUSR);
  78MODULE_PARM_DESC(procreload,
  79                 "Attempt init failure recovery with firmware reload");
  80module_param_array(tuner,    int, NULL, 0444);
  81MODULE_PARM_DESC(tuner,"specify installed tuner type");
  82module_param_array(video_std,    int, NULL, 0444);
  83MODULE_PARM_DESC(video_std,"specify initial video standard");
  84module_param_array(tolerance,    int, NULL, 0444);
  85MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  86
  87/* US Broadcast channel 3 (61.25 MHz), to help with testing */
  88static int default_tv_freq    = 61250000L;
  89/* 104.3 MHz, a usable FM station for my area */
  90static int default_radio_freq = 104300000L;
  91
  92module_param_named(tv_freq, default_tv_freq, int, 0444);
  93MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  94module_param_named(radio_freq, default_radio_freq, int, 0444);
  95MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
  96
  97#define PVR2_CTL_WRITE_ENDPOINT  0x01
  98#define PVR2_CTL_READ_ENDPOINT   0x81
  99
 100#define PVR2_GPIO_IN 0x9008
 101#define PVR2_GPIO_OUT 0x900c
 102#define PVR2_GPIO_DIR 0x9020
 103
 104#define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 105
 106#define PVR2_FIRMWARE_ENDPOINT   0x02
 107
 108/* size of a firmware chunk */
 109#define FIRMWARE_CHUNK_SIZE 0x2000
 110
 111typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 112                                        struct v4l2_subdev *);
 113
 114static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 115        [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 116        [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 117        [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 118        [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 119        [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 120};
 121
 122static const char *module_names[] = {
 123        [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 124        [PVR2_CLIENT_ID_CX25840] = "cx25840",
 125        [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 126        [PVR2_CLIENT_ID_TUNER] = "tuner",
 127        [PVR2_CLIENT_ID_DEMOD] = "tuner",
 128        [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 129        [PVR2_CLIENT_ID_WM8775] = "wm8775",
 130};
 131
 132
 133static const unsigned char *module_i2c_addresses[] = {
 134        [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 135        [PVR2_CLIENT_ID_DEMOD] = "\x43",
 136        [PVR2_CLIENT_ID_MSP3400] = "\x40",
 137        [PVR2_CLIENT_ID_SAA7115] = "\x21",
 138        [PVR2_CLIENT_ID_WM8775] = "\x1b",
 139        [PVR2_CLIENT_ID_CX25840] = "\x44",
 140        [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 141};
 142
 143
 144static const char *ir_scheme_names[] = {
 145        [PVR2_IR_SCHEME_NONE] = "none",
 146        [PVR2_IR_SCHEME_29XXX] = "29xxx",
 147        [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 148        [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 149        [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 150};
 151
 152
 153/* Define the list of additional controls we'll dynamically construct based
 154   on query of the cx2341x module. */
 155struct pvr2_mpeg_ids {
 156        const char *strid;
 157        int id;
 158};
 159static const struct pvr2_mpeg_ids mpeg_ids[] = {
 160        {
 161                .strid = "audio_layer",
 162                .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 163        },{
 164                .strid = "audio_bitrate",
 165                .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 166        },{
 167                /* Already using audio_mode elsewhere :-( */
 168                .strid = "mpeg_audio_mode",
 169                .id = V4L2_CID_MPEG_AUDIO_MODE,
 170        },{
 171                .strid = "mpeg_audio_mode_extension",
 172                .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 173        },{
 174                .strid = "audio_emphasis",
 175                .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 176        },{
 177                .strid = "audio_crc",
 178                .id = V4L2_CID_MPEG_AUDIO_CRC,
 179        },{
 180                .strid = "video_aspect",
 181                .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 182        },{
 183                .strid = "video_b_frames",
 184                .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 185        },{
 186                .strid = "video_gop_size",
 187                .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 188        },{
 189                .strid = "video_gop_closure",
 190                .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 191        },{
 192                .strid = "video_bitrate_mode",
 193                .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 194        },{
 195                .strid = "video_bitrate",
 196                .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 197        },{
 198                .strid = "video_bitrate_peak",
 199                .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 200        },{
 201                .strid = "video_temporal_decimation",
 202                .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 203        },{
 204                .strid = "stream_type",
 205                .id = V4L2_CID_MPEG_STREAM_TYPE,
 206        },{
 207                .strid = "video_spatial_filter_mode",
 208                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 209        },{
 210                .strid = "video_spatial_filter",
 211                .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 212        },{
 213                .strid = "video_luma_spatial_filter_type",
 214                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 215        },{
 216                .strid = "video_chroma_spatial_filter_type",
 217                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 218        },{
 219                .strid = "video_temporal_filter_mode",
 220                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 221        },{
 222                .strid = "video_temporal_filter",
 223                .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 224        },{
 225                .strid = "video_median_filter_type",
 226                .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 227        },{
 228                .strid = "video_luma_median_filter_top",
 229                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 230        },{
 231                .strid = "video_luma_median_filter_bottom",
 232                .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 233        },{
 234                .strid = "video_chroma_median_filter_top",
 235                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 236        },{
 237                .strid = "video_chroma_median_filter_bottom",
 238                .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 239        }
 240};
 241#define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 242
 243
 244static const char *control_values_srate[] = {
 245        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 246        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 247        [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 248};
 249
 250
 251
 252static const char *control_values_input[] = {
 253        [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 254        [PVR2_CVAL_INPUT_DTV]       = "dtv",
 255        [PVR2_CVAL_INPUT_RADIO]     = "radio",
 256        [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 257        [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 258};
 259
 260
 261static const char *control_values_audiomode[] = {
 262        [V4L2_TUNER_MODE_MONO]   = "Mono",
 263        [V4L2_TUNER_MODE_STEREO] = "Stereo",
 264        [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 265        [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 266        [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 267};
 268
 269
 270static const char *control_values_hsm[] = {
 271        [PVR2_CVAL_HSM_FAIL] = "Fail",
 272        [PVR2_CVAL_HSM_HIGH] = "High",
 273        [PVR2_CVAL_HSM_FULL] = "Full",
 274};
 275
 276
 277static const char *pvr2_state_names[] = {
 278        [PVR2_STATE_NONE] =    "none",
 279        [PVR2_STATE_DEAD] =    "dead",
 280        [PVR2_STATE_COLD] =    "cold",
 281        [PVR2_STATE_WARM] =    "warm",
 282        [PVR2_STATE_ERROR] =   "error",
 283        [PVR2_STATE_READY] =   "ready",
 284        [PVR2_STATE_RUN] =     "run",
 285};
 286
 287
 288struct pvr2_fx2cmd_descdef {
 289        unsigned char id;
 290        unsigned char *desc;
 291};
 292
 293static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 294        {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 295        {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 296        {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 297        {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 298        {FX2CMD_REG_WRITE, "write encoder register"},
 299        {FX2CMD_REG_READ, "read encoder register"},
 300        {FX2CMD_MEMSEL, "encoder memsel"},
 301        {FX2CMD_I2C_WRITE, "i2c write"},
 302        {FX2CMD_I2C_READ, "i2c read"},
 303        {FX2CMD_GET_USB_SPEED, "get USB speed"},
 304        {FX2CMD_STREAMING_ON, "stream on"},
 305        {FX2CMD_STREAMING_OFF, "stream off"},
 306        {FX2CMD_FWPOST1, "fwpost1"},
 307        {FX2CMD_POWER_OFF, "power off"},
 308        {FX2CMD_POWER_ON, "power on"},
 309        {FX2CMD_DEEP_RESET, "deep reset"},
 310        {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 311        {FX2CMD_GET_IR_CODE, "get IR code"},
 312        {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 313        {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 314        {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 315        {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 316        {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 317        {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 318        {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 319};
 320
 321
 322static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 323static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 324static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 325static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 326static void pvr2_hdw_worker_poll(struct work_struct *work);
 327static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 328static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 329static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 330static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 331static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 332static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 333static void pvr2_hdw_quiescent_timeout(struct timer_list *);
 334static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *);
 335static void pvr2_hdw_encoder_wait_timeout(struct timer_list *);
 336static void pvr2_hdw_encoder_run_timeout(struct timer_list *);
 337static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 338static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 339                                unsigned int timeout,int probe_fl,
 340                                void *write_data,unsigned int write_len,
 341                                void *read_data,unsigned int read_len);
 342static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 343static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw);
 344
 345static void trace_stbit(const char *name,int val)
 346{
 347        pvr2_trace(PVR2_TRACE_STBITS,
 348                   "State bit %s <-- %s",
 349                   name,(val ? "true" : "false"));
 350}
 351
 352static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 353{
 354        struct pvr2_hdw *hdw = cptr->hdw;
 355        if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 356                *vp = hdw->freqTable[hdw->freqProgSlot-1];
 357        } else {
 358                *vp = 0;
 359        }
 360        return 0;
 361}
 362
 363static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 364{
 365        struct pvr2_hdw *hdw = cptr->hdw;
 366        unsigned int slotId = hdw->freqProgSlot;
 367        if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 368                hdw->freqTable[slotId-1] = v;
 369                /* Handle side effects correctly - if we're tuned to this
 370                   slot, then forgot the slot id relation since the stored
 371                   frequency has been changed. */
 372                if (hdw->freqSelector) {
 373                        if (hdw->freqSlotRadio == slotId) {
 374                                hdw->freqSlotRadio = 0;
 375                        }
 376                } else {
 377                        if (hdw->freqSlotTelevision == slotId) {
 378                                hdw->freqSlotTelevision = 0;
 379                        }
 380                }
 381        }
 382        return 0;
 383}
 384
 385static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 386{
 387        *vp = cptr->hdw->freqProgSlot;
 388        return 0;
 389}
 390
 391static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 392{
 393        struct pvr2_hdw *hdw = cptr->hdw;
 394        if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 395                hdw->freqProgSlot = v;
 396        }
 397        return 0;
 398}
 399
 400static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 401{
 402        struct pvr2_hdw *hdw = cptr->hdw;
 403        *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 404        return 0;
 405}
 406
 407static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 408{
 409        unsigned freq = 0;
 410        struct pvr2_hdw *hdw = cptr->hdw;
 411        if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 412        if (slotId > 0) {
 413                freq = hdw->freqTable[slotId-1];
 414                if (!freq) return 0;
 415                pvr2_hdw_set_cur_freq(hdw,freq);
 416        }
 417        if (hdw->freqSelector) {
 418                hdw->freqSlotRadio = slotId;
 419        } else {
 420                hdw->freqSlotTelevision = slotId;
 421        }
 422        return 0;
 423}
 424
 425static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 426{
 427        *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 428        return 0;
 429}
 430
 431static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 432{
 433        return cptr->hdw->freqDirty != 0;
 434}
 435
 436static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 437{
 438        cptr->hdw->freqDirty = 0;
 439}
 440
 441static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 442{
 443        pvr2_hdw_set_cur_freq(cptr->hdw,v);
 444        return 0;
 445}
 446
 447static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 448{
 449        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 450        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 451        if (stat != 0) {
 452                return stat;
 453        }
 454        *left = cap->bounds.left;
 455        return 0;
 456}
 457
 458static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 459{
 460        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 461        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 462        if (stat != 0) {
 463                return stat;
 464        }
 465        *left = cap->bounds.left;
 466        if (cap->bounds.width > cptr->hdw->cropw_val) {
 467                *left += cap->bounds.width - cptr->hdw->cropw_val;
 468        }
 469        return 0;
 470}
 471
 472static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 473{
 474        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 475        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 476        if (stat != 0) {
 477                return stat;
 478        }
 479        *top = cap->bounds.top;
 480        return 0;
 481}
 482
 483static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 484{
 485        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 486        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 487        if (stat != 0) {
 488                return stat;
 489        }
 490        *top = cap->bounds.top;
 491        if (cap->bounds.height > cptr->hdw->croph_val) {
 492                *top += cap->bounds.height - cptr->hdw->croph_val;
 493        }
 494        return 0;
 495}
 496
 497static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 498{
 499        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 500        int stat, bleftend, cleft;
 501
 502        stat = pvr2_hdw_check_cropcap(cptr->hdw);
 503        if (stat != 0) {
 504                return stat;
 505        }
 506        bleftend = cap->bounds.left+cap->bounds.width;
 507        cleft = cptr->hdw->cropl_val;
 508
 509        *width = cleft < bleftend ? bleftend-cleft : 0;
 510        return 0;
 511}
 512
 513static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 514{
 515        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 516        int stat, btopend, ctop;
 517
 518        stat = pvr2_hdw_check_cropcap(cptr->hdw);
 519        if (stat != 0) {
 520                return stat;
 521        }
 522        btopend = cap->bounds.top+cap->bounds.height;
 523        ctop = cptr->hdw->cropt_val;
 524
 525        *height = ctop < btopend ? btopend-ctop : 0;
 526        return 0;
 527}
 528
 529static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 530{
 531        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 532        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 533        if (stat != 0) {
 534                return stat;
 535        }
 536        *val = cap->bounds.left;
 537        return 0;
 538}
 539
 540static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 541{
 542        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 543        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 544        if (stat != 0) {
 545                return stat;
 546        }
 547        *val = cap->bounds.top;
 548        return 0;
 549}
 550
 551static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 552{
 553        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 554        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 555        if (stat != 0) {
 556                return stat;
 557        }
 558        *val = cap->bounds.width;
 559        return 0;
 560}
 561
 562static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 563{
 564        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 565        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 566        if (stat != 0) {
 567                return stat;
 568        }
 569        *val = cap->bounds.height;
 570        return 0;
 571}
 572
 573static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 574{
 575        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 576        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 577        if (stat != 0) {
 578                return stat;
 579        }
 580        *val = cap->defrect.left;
 581        return 0;
 582}
 583
 584static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 585{
 586        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 587        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 588        if (stat != 0) {
 589                return stat;
 590        }
 591        *val = cap->defrect.top;
 592        return 0;
 593}
 594
 595static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 596{
 597        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 598        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 599        if (stat != 0) {
 600                return stat;
 601        }
 602        *val = cap->defrect.width;
 603        return 0;
 604}
 605
 606static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 607{
 608        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 609        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 610        if (stat != 0) {
 611                return stat;
 612        }
 613        *val = cap->defrect.height;
 614        return 0;
 615}
 616
 617static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 618{
 619        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 620        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 621        if (stat != 0) {
 622                return stat;
 623        }
 624        *val = cap->pixelaspect.numerator;
 625        return 0;
 626}
 627
 628static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 629{
 630        struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 631        int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 632        if (stat != 0) {
 633                return stat;
 634        }
 635        *val = cap->pixelaspect.denominator;
 636        return 0;
 637}
 638
 639static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 640{
 641        /* Actual maximum depends on the video standard in effect. */
 642        if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 643                *vp = 480;
 644        } else {
 645                *vp = 576;
 646        }
 647        return 0;
 648}
 649
 650static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 651{
 652        /* Actual minimum depends on device digitizer type. */
 653        if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 654                *vp = 75;
 655        } else {
 656                *vp = 17;
 657        }
 658        return 0;
 659}
 660
 661static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 662{
 663        *vp = cptr->hdw->input_val;
 664        return 0;
 665}
 666
 667static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 668{
 669        return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 670}
 671
 672static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 673{
 674        return pvr2_hdw_set_input(cptr->hdw,v);
 675}
 676
 677static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 678{
 679        return cptr->hdw->input_dirty != 0;
 680}
 681
 682static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 683{
 684        cptr->hdw->input_dirty = 0;
 685}
 686
 687
 688static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 689{
 690        unsigned long fv;
 691        struct pvr2_hdw *hdw = cptr->hdw;
 692        if (hdw->tuner_signal_stale) {
 693                pvr2_hdw_status_poll(hdw);
 694        }
 695        fv = hdw->tuner_signal_info.rangehigh;
 696        if (!fv) {
 697                /* Safety fallback */
 698                *vp = TV_MAX_FREQ;
 699                return 0;
 700        }
 701        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 702                fv = (fv * 125) / 2;
 703        } else {
 704                fv = fv * 62500;
 705        }
 706        *vp = fv;
 707        return 0;
 708}
 709
 710static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 711{
 712        unsigned long fv;
 713        struct pvr2_hdw *hdw = cptr->hdw;
 714        if (hdw->tuner_signal_stale) {
 715                pvr2_hdw_status_poll(hdw);
 716        }
 717        fv = hdw->tuner_signal_info.rangelow;
 718        if (!fv) {
 719                /* Safety fallback */
 720                *vp = TV_MIN_FREQ;
 721                return 0;
 722        }
 723        if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 724                fv = (fv * 125) / 2;
 725        } else {
 726                fv = fv * 62500;
 727        }
 728        *vp = fv;
 729        return 0;
 730}
 731
 732static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 733{
 734        return cptr->hdw->enc_stale != 0;
 735}
 736
 737static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 738{
 739        cptr->hdw->enc_stale = 0;
 740        cptr->hdw->enc_unsafe_stale = 0;
 741}
 742
 743static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 744{
 745        int ret;
 746        struct v4l2_ext_controls cs;
 747        struct v4l2_ext_control c1;
 748        memset(&cs,0,sizeof(cs));
 749        memset(&c1,0,sizeof(c1));
 750        cs.controls = &c1;
 751        cs.count = 1;
 752        c1.id = cptr->info->v4l_id;
 753        ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 754                                VIDIOC_G_EXT_CTRLS);
 755        if (ret) return ret;
 756        *vp = c1.value;
 757        return 0;
 758}
 759
 760static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 761{
 762        int ret;
 763        struct pvr2_hdw *hdw = cptr->hdw;
 764        struct v4l2_ext_controls cs;
 765        struct v4l2_ext_control c1;
 766        memset(&cs,0,sizeof(cs));
 767        memset(&c1,0,sizeof(c1));
 768        cs.controls = &c1;
 769        cs.count = 1;
 770        c1.id = cptr->info->v4l_id;
 771        c1.value = v;
 772        ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 773                                hdw->state_encoder_run, &cs,
 774                                VIDIOC_S_EXT_CTRLS);
 775        if (ret == -EBUSY) {
 776                /* Oops.  cx2341x is telling us it's not safe to change
 777                   this control while we're capturing.  Make a note of this
 778                   fact so that the pipeline will be stopped the next time
 779                   controls are committed.  Then go on ahead and store this
 780                   change anyway. */
 781                ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 782                                        0, &cs,
 783                                        VIDIOC_S_EXT_CTRLS);
 784                if (!ret) hdw->enc_unsafe_stale = !0;
 785        }
 786        if (ret) return ret;
 787        hdw->enc_stale = !0;
 788        return 0;
 789}
 790
 791static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 792{
 793        struct v4l2_queryctrl qctrl;
 794        struct pvr2_ctl_info *info;
 795        qctrl.id = cptr->info->v4l_id;
 796        cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 797        /* Strip out the const so we can adjust a function pointer.  It's
 798           OK to do this here because we know this is a dynamically created
 799           control, so the underlying storage for the info pointer is (a)
 800           private to us, and (b) not in read-only storage.  Either we do
 801           this or we significantly complicate the underlying control
 802           implementation. */
 803        info = (struct pvr2_ctl_info *)(cptr->info);
 804        if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 805                if (info->set_value) {
 806                        info->set_value = NULL;
 807                }
 808        } else {
 809                if (!(info->set_value)) {
 810                        info->set_value = ctrl_cx2341x_set;
 811                }
 812        }
 813        return qctrl.flags;
 814}
 815
 816static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 817{
 818        *vp = cptr->hdw->state_pipeline_req;
 819        return 0;
 820}
 821
 822static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 823{
 824        *vp = cptr->hdw->master_state;
 825        return 0;
 826}
 827
 828static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 829{
 830        int result = pvr2_hdw_is_hsm(cptr->hdw);
 831        *vp = PVR2_CVAL_HSM_FULL;
 832        if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 833        if (result) *vp = PVR2_CVAL_HSM_HIGH;
 834        return 0;
 835}
 836
 837static int ctrl_stddetect_get(struct pvr2_ctrl *cptr, int *vp)
 838{
 839        *vp = pvr2_hdw_get_detected_std(cptr->hdw);
 840        return 0;
 841}
 842
 843static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 844{
 845        *vp = cptr->hdw->std_mask_avail;
 846        return 0;
 847}
 848
 849static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 850{
 851        struct pvr2_hdw *hdw = cptr->hdw;
 852        v4l2_std_id ns;
 853        ns = hdw->std_mask_avail;
 854        ns = (ns & ~m) | (v & m);
 855        if (ns == hdw->std_mask_avail) return 0;
 856        hdw->std_mask_avail = ns;
 857        hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
 858        return 0;
 859}
 860
 861static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 862                               char *bufPtr,unsigned int bufSize,
 863                               unsigned int *len)
 864{
 865        *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 866        return 0;
 867}
 868
 869static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 870                               const char *bufPtr,unsigned int bufSize,
 871                               int *mskp,int *valp)
 872{
 873        int ret;
 874        v4l2_std_id id;
 875        ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 876        if (ret < 0) return ret;
 877        if (mskp) *mskp = id;
 878        if (valp) *valp = id;
 879        return 0;
 880}
 881
 882static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 883{
 884        *vp = cptr->hdw->std_mask_cur;
 885        return 0;
 886}
 887
 888static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 889{
 890        struct pvr2_hdw *hdw = cptr->hdw;
 891        v4l2_std_id ns;
 892        ns = hdw->std_mask_cur;
 893        ns = (ns & ~m) | (v & m);
 894        if (ns == hdw->std_mask_cur) return 0;
 895        hdw->std_mask_cur = ns;
 896        hdw->std_dirty = !0;
 897        return 0;
 898}
 899
 900static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 901{
 902        return cptr->hdw->std_dirty != 0;
 903}
 904
 905static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 906{
 907        cptr->hdw->std_dirty = 0;
 908}
 909
 910static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 911{
 912        struct pvr2_hdw *hdw = cptr->hdw;
 913        pvr2_hdw_status_poll(hdw);
 914        *vp = hdw->tuner_signal_info.signal;
 915        return 0;
 916}
 917
 918static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 919{
 920        int val = 0;
 921        unsigned int subchan;
 922        struct pvr2_hdw *hdw = cptr->hdw;
 923        pvr2_hdw_status_poll(hdw);
 924        subchan = hdw->tuner_signal_info.rxsubchans;
 925        if (subchan & V4L2_TUNER_SUB_MONO) {
 926                val |= (1 << V4L2_TUNER_MODE_MONO);
 927        }
 928        if (subchan & V4L2_TUNER_SUB_STEREO) {
 929                val |= (1 << V4L2_TUNER_MODE_STEREO);
 930        }
 931        if (subchan & V4L2_TUNER_SUB_LANG1) {
 932                val |= (1 << V4L2_TUNER_MODE_LANG1);
 933        }
 934        if (subchan & V4L2_TUNER_SUB_LANG2) {
 935                val |= (1 << V4L2_TUNER_MODE_LANG2);
 936        }
 937        *vp = val;
 938        return 0;
 939}
 940
 941
 942#define DEFINT(vmin,vmax) \
 943        .type = pvr2_ctl_int, \
 944        .def.type_int.min_value = vmin, \
 945        .def.type_int.max_value = vmax
 946
 947#define DEFENUM(tab) \
 948        .type = pvr2_ctl_enum, \
 949        .def.type_enum.count = ARRAY_SIZE(tab), \
 950        .def.type_enum.value_names = tab
 951
 952#define DEFBOOL \
 953        .type = pvr2_ctl_bool
 954
 955#define DEFMASK(msk,tab) \
 956        .type = pvr2_ctl_bitmask, \
 957        .def.type_bitmask.valid_bits = msk, \
 958        .def.type_bitmask.bit_names = tab
 959
 960#define DEFREF(vname) \
 961        .set_value = ctrl_set_##vname, \
 962        .get_value = ctrl_get_##vname, \
 963        .is_dirty = ctrl_isdirty_##vname, \
 964        .clear_dirty = ctrl_cleardirty_##vname
 965
 966
 967#define VCREATE_FUNCS(vname) \
 968static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
 969{*vp = cptr->hdw->vname##_val; return 0;} \
 970static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
 971{cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
 972static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
 973{return cptr->hdw->vname##_dirty != 0;} \
 974static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
 975{cptr->hdw->vname##_dirty = 0;}
 976
 977VCREATE_FUNCS(brightness)
 978VCREATE_FUNCS(contrast)
 979VCREATE_FUNCS(saturation)
 980VCREATE_FUNCS(hue)
 981VCREATE_FUNCS(volume)
 982VCREATE_FUNCS(balance)
 983VCREATE_FUNCS(bass)
 984VCREATE_FUNCS(treble)
 985VCREATE_FUNCS(mute)
 986VCREATE_FUNCS(cropl)
 987VCREATE_FUNCS(cropt)
 988VCREATE_FUNCS(cropw)
 989VCREATE_FUNCS(croph)
 990VCREATE_FUNCS(audiomode)
 991VCREATE_FUNCS(res_hor)
 992VCREATE_FUNCS(res_ver)
 993VCREATE_FUNCS(srate)
 994
 995/* Table definition of all controls which can be manipulated */
 996static const struct pvr2_ctl_info control_defs[] = {
 997        {
 998                .v4l_id = V4L2_CID_BRIGHTNESS,
 999                .desc = "Brightness",
1000                .name = "brightness",
1001                .default_value = 128,
1002                DEFREF(brightness),
1003                DEFINT(0,255),
1004        },{
1005                .v4l_id = V4L2_CID_CONTRAST,
1006                .desc = "Contrast",
1007                .name = "contrast",
1008                .default_value = 68,
1009                DEFREF(contrast),
1010                DEFINT(0,127),
1011        },{
1012                .v4l_id = V4L2_CID_SATURATION,
1013                .desc = "Saturation",
1014                .name = "saturation",
1015                .default_value = 64,
1016                DEFREF(saturation),
1017                DEFINT(0,127),
1018        },{
1019                .v4l_id = V4L2_CID_HUE,
1020                .desc = "Hue",
1021                .name = "hue",
1022                .default_value = 0,
1023                DEFREF(hue),
1024                DEFINT(-128,127),
1025        },{
1026                .v4l_id = V4L2_CID_AUDIO_VOLUME,
1027                .desc = "Volume",
1028                .name = "volume",
1029                .default_value = 62000,
1030                DEFREF(volume),
1031                DEFINT(0,65535),
1032        },{
1033                .v4l_id = V4L2_CID_AUDIO_BALANCE,
1034                .desc = "Balance",
1035                .name = "balance",
1036                .default_value = 0,
1037                DEFREF(balance),
1038                DEFINT(-32768,32767),
1039        },{
1040                .v4l_id = V4L2_CID_AUDIO_BASS,
1041                .desc = "Bass",
1042                .name = "bass",
1043                .default_value = 0,
1044                DEFREF(bass),
1045                DEFINT(-32768,32767),
1046        },{
1047                .v4l_id = V4L2_CID_AUDIO_TREBLE,
1048                .desc = "Treble",
1049                .name = "treble",
1050                .default_value = 0,
1051                DEFREF(treble),
1052                DEFINT(-32768,32767),
1053        },{
1054                .v4l_id = V4L2_CID_AUDIO_MUTE,
1055                .desc = "Mute",
1056                .name = "mute",
1057                .default_value = 0,
1058                DEFREF(mute),
1059                DEFBOOL,
1060        }, {
1061                .desc = "Capture crop left margin",
1062                .name = "crop_left",
1063                .internal_id = PVR2_CID_CROPL,
1064                .default_value = 0,
1065                DEFREF(cropl),
1066                DEFINT(-129, 340),
1067                .get_min_value = ctrl_cropl_min_get,
1068                .get_max_value = ctrl_cropl_max_get,
1069                .get_def_value = ctrl_get_cropcapdl,
1070        }, {
1071                .desc = "Capture crop top margin",
1072                .name = "crop_top",
1073                .internal_id = PVR2_CID_CROPT,
1074                .default_value = 0,
1075                DEFREF(cropt),
1076                DEFINT(-35, 544),
1077                .get_min_value = ctrl_cropt_min_get,
1078                .get_max_value = ctrl_cropt_max_get,
1079                .get_def_value = ctrl_get_cropcapdt,
1080        }, {
1081                .desc = "Capture crop width",
1082                .name = "crop_width",
1083                .internal_id = PVR2_CID_CROPW,
1084                .default_value = 720,
1085                DEFREF(cropw),
1086                DEFINT(0, 864),
1087                .get_max_value = ctrl_cropw_max_get,
1088                .get_def_value = ctrl_get_cropcapdw,
1089        }, {
1090                .desc = "Capture crop height",
1091                .name = "crop_height",
1092                .internal_id = PVR2_CID_CROPH,
1093                .default_value = 480,
1094                DEFREF(croph),
1095                DEFINT(0, 576),
1096                .get_max_value = ctrl_croph_max_get,
1097                .get_def_value = ctrl_get_cropcapdh,
1098        }, {
1099                .desc = "Capture capability pixel aspect numerator",
1100                .name = "cropcap_pixel_numerator",
1101                .internal_id = PVR2_CID_CROPCAPPAN,
1102                .get_value = ctrl_get_cropcappan,
1103        }, {
1104                .desc = "Capture capability pixel aspect denominator",
1105                .name = "cropcap_pixel_denominator",
1106                .internal_id = PVR2_CID_CROPCAPPAD,
1107                .get_value = ctrl_get_cropcappad,
1108        }, {
1109                .desc = "Capture capability bounds top",
1110                .name = "cropcap_bounds_top",
1111                .internal_id = PVR2_CID_CROPCAPBT,
1112                .get_value = ctrl_get_cropcapbt,
1113        }, {
1114                .desc = "Capture capability bounds left",
1115                .name = "cropcap_bounds_left",
1116                .internal_id = PVR2_CID_CROPCAPBL,
1117                .get_value = ctrl_get_cropcapbl,
1118        }, {
1119                .desc = "Capture capability bounds width",
1120                .name = "cropcap_bounds_width",
1121                .internal_id = PVR2_CID_CROPCAPBW,
1122                .get_value = ctrl_get_cropcapbw,
1123        }, {
1124                .desc = "Capture capability bounds height",
1125                .name = "cropcap_bounds_height",
1126                .internal_id = PVR2_CID_CROPCAPBH,
1127                .get_value = ctrl_get_cropcapbh,
1128        },{
1129                .desc = "Video Source",
1130                .name = "input",
1131                .internal_id = PVR2_CID_INPUT,
1132                .default_value = PVR2_CVAL_INPUT_TV,
1133                .check_value = ctrl_check_input,
1134                DEFREF(input),
1135                DEFENUM(control_values_input),
1136        },{
1137                .desc = "Audio Mode",
1138                .name = "audio_mode",
1139                .internal_id = PVR2_CID_AUDIOMODE,
1140                .default_value = V4L2_TUNER_MODE_STEREO,
1141                DEFREF(audiomode),
1142                DEFENUM(control_values_audiomode),
1143        },{
1144                .desc = "Horizontal capture resolution",
1145                .name = "resolution_hor",
1146                .internal_id = PVR2_CID_HRES,
1147                .default_value = 720,
1148                DEFREF(res_hor),
1149                DEFINT(19,720),
1150        },{
1151                .desc = "Vertical capture resolution",
1152                .name = "resolution_ver",
1153                .internal_id = PVR2_CID_VRES,
1154                .default_value = 480,
1155                DEFREF(res_ver),
1156                DEFINT(17,576),
1157                /* Hook in check for video standard and adjust maximum
1158                   depending on the standard. */
1159                .get_max_value = ctrl_vres_max_get,
1160                .get_min_value = ctrl_vres_min_get,
1161        },{
1162                .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1163                .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1164                .desc = "Audio Sampling Frequency",
1165                .name = "srate",
1166                DEFREF(srate),
1167                DEFENUM(control_values_srate),
1168        },{
1169                .desc = "Tuner Frequency (Hz)",
1170                .name = "frequency",
1171                .internal_id = PVR2_CID_FREQUENCY,
1172                .default_value = 0,
1173                .set_value = ctrl_freq_set,
1174                .get_value = ctrl_freq_get,
1175                .is_dirty = ctrl_freq_is_dirty,
1176                .clear_dirty = ctrl_freq_clear_dirty,
1177                DEFINT(0,0),
1178                /* Hook in check for input value (tv/radio) and adjust
1179                   max/min values accordingly */
1180                .get_max_value = ctrl_freq_max_get,
1181                .get_min_value = ctrl_freq_min_get,
1182        },{
1183                .desc = "Channel",
1184                .name = "channel",
1185                .set_value = ctrl_channel_set,
1186                .get_value = ctrl_channel_get,
1187                DEFINT(0,FREQTABLE_SIZE),
1188        },{
1189                .desc = "Channel Program Frequency",
1190                .name = "freq_table_value",
1191                .set_value = ctrl_channelfreq_set,
1192                .get_value = ctrl_channelfreq_get,
1193                DEFINT(0,0),
1194                /* Hook in check for input value (tv/radio) and adjust
1195                   max/min values accordingly */
1196                .get_max_value = ctrl_freq_max_get,
1197                .get_min_value = ctrl_freq_min_get,
1198        },{
1199                .desc = "Channel Program ID",
1200                .name = "freq_table_channel",
1201                .set_value = ctrl_channelprog_set,
1202                .get_value = ctrl_channelprog_get,
1203                DEFINT(0,FREQTABLE_SIZE),
1204        },{
1205                .desc = "Streaming Enabled",
1206                .name = "streaming_enabled",
1207                .get_value = ctrl_streamingenabled_get,
1208                DEFBOOL,
1209        },{
1210                .desc = "USB Speed",
1211                .name = "usb_speed",
1212                .get_value = ctrl_hsm_get,
1213                DEFENUM(control_values_hsm),
1214        },{
1215                .desc = "Master State",
1216                .name = "master_state",
1217                .get_value = ctrl_masterstate_get,
1218                DEFENUM(pvr2_state_names),
1219        },{
1220                .desc = "Signal Present",
1221                .name = "signal_present",
1222                .get_value = ctrl_signal_get,
1223                DEFINT(0,65535),
1224        },{
1225                .desc = "Audio Modes Present",
1226                .name = "audio_modes_present",
1227                .get_value = ctrl_audio_modes_present_get,
1228                /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1229                   v4l.  Nothing outside of this module cares about this,
1230                   but I reuse it in order to also reuse the
1231                   control_values_audiomode string table. */
1232                DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1233                         (1 << V4L2_TUNER_MODE_STEREO)|
1234                         (1 << V4L2_TUNER_MODE_LANG1)|
1235                         (1 << V4L2_TUNER_MODE_LANG2)),
1236                        control_values_audiomode),
1237        },{
1238                .desc = "Video Standards Available Mask",
1239                .name = "video_standard_mask_available",
1240                .internal_id = PVR2_CID_STDAVAIL,
1241                .skip_init = !0,
1242                .get_value = ctrl_stdavail_get,
1243                .set_value = ctrl_stdavail_set,
1244                .val_to_sym = ctrl_std_val_to_sym,
1245                .sym_to_val = ctrl_std_sym_to_val,
1246                .type = pvr2_ctl_bitmask,
1247        },{
1248                .desc = "Video Standards In Use Mask",
1249                .name = "video_standard_mask_active",
1250                .internal_id = PVR2_CID_STDCUR,
1251                .skip_init = !0,
1252                .get_value = ctrl_stdcur_get,
1253                .set_value = ctrl_stdcur_set,
1254                .is_dirty = ctrl_stdcur_is_dirty,
1255                .clear_dirty = ctrl_stdcur_clear_dirty,
1256                .val_to_sym = ctrl_std_val_to_sym,
1257                .sym_to_val = ctrl_std_sym_to_val,
1258                .type = pvr2_ctl_bitmask,
1259        },{
1260                .desc = "Video Standards Detected Mask",
1261                .name = "video_standard_mask_detected",
1262                .internal_id = PVR2_CID_STDDETECT,
1263                .skip_init = !0,
1264                .get_value = ctrl_stddetect_get,
1265                .val_to_sym = ctrl_std_val_to_sym,
1266                .sym_to_val = ctrl_std_sym_to_val,
1267                .type = pvr2_ctl_bitmask,
1268        }
1269};
1270
1271#define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1272
1273
1274const char *pvr2_config_get_name(enum pvr2_config cfg)
1275{
1276        switch (cfg) {
1277        case pvr2_config_empty: return "empty";
1278        case pvr2_config_mpeg: return "mpeg";
1279        case pvr2_config_vbi: return "vbi";
1280        case pvr2_config_pcm: return "pcm";
1281        case pvr2_config_rawvideo: return "raw video";
1282        }
1283        return "<unknown>";
1284}
1285
1286
1287struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1288{
1289        return hdw->usb_dev;
1290}
1291
1292
1293unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1294{
1295        return hdw->serial_number;
1296}
1297
1298
1299const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1300{
1301        return hdw->bus_info;
1302}
1303
1304
1305const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1306{
1307        return hdw->identifier;
1308}
1309
1310
1311unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1312{
1313        return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1314}
1315
1316/* Set the currently tuned frequency and account for all possible
1317   driver-core side effects of this action. */
1318static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1319{
1320        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1321                if (hdw->freqSelector) {
1322                        /* Swing over to radio frequency selection */
1323                        hdw->freqSelector = 0;
1324                        hdw->freqDirty = !0;
1325                }
1326                if (hdw->freqValRadio != val) {
1327                        hdw->freqValRadio = val;
1328                        hdw->freqSlotRadio = 0;
1329                        hdw->freqDirty = !0;
1330                }
1331        } else {
1332                if (!(hdw->freqSelector)) {
1333                        /* Swing over to television frequency selection */
1334                        hdw->freqSelector = 1;
1335                        hdw->freqDirty = !0;
1336                }
1337                if (hdw->freqValTelevision != val) {
1338                        hdw->freqValTelevision = val;
1339                        hdw->freqSlotTelevision = 0;
1340                        hdw->freqDirty = !0;
1341                }
1342        }
1343}
1344
1345int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1346{
1347        return hdw->unit_number;
1348}
1349
1350
1351/* Attempt to locate one of the given set of files.  Messages are logged
1352   appropriate to what has been found.  The return value will be 0 or
1353   greater on success (it will be the index of the file name found) and
1354   fw_entry will be filled in.  Otherwise a negative error is returned on
1355   failure.  If the return value is -ENOENT then no viable firmware file
1356   could be located. */
1357static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1358                                const struct firmware **fw_entry,
1359                                const char *fwtypename,
1360                                unsigned int fwcount,
1361                                const char *fwnames[])
1362{
1363        unsigned int idx;
1364        int ret = -EINVAL;
1365        for (idx = 0; idx < fwcount; idx++) {
1366                ret = request_firmware(fw_entry,
1367                                       fwnames[idx],
1368                                       &hdw->usb_dev->dev);
1369                if (!ret) {
1370                        trace_firmware("Located %s firmware: %s; uploading...",
1371                                       fwtypename,
1372                                       fwnames[idx]);
1373                        return idx;
1374                }
1375                if (ret == -ENOENT) continue;
1376                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1377                           "request_firmware fatal error with code=%d",ret);
1378                return ret;
1379        }
1380        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1381                   "***WARNING*** Device %s firmware seems to be missing.",
1382                   fwtypename);
1383        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1384                   "Did you install the pvrusb2 firmware files in their proper location?");
1385        if (fwcount == 1) {
1386                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1387                           "request_firmware unable to locate %s file %s",
1388                           fwtypename,fwnames[0]);
1389        } else {
1390                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1391                           "request_firmware unable to locate one of the following %s files:",
1392                           fwtypename);
1393                for (idx = 0; idx < fwcount; idx++) {
1394                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1395                                   "request_firmware: Failed to find %s",
1396                                   fwnames[idx]);
1397                }
1398        }
1399        return ret;
1400}
1401
1402
1403/*
1404 * pvr2_upload_firmware1().
1405 *
1406 * Send the 8051 firmware to the device.  After the upload, arrange for
1407 * device to re-enumerate.
1408 *
1409 * NOTE : the pointer to the firmware data given by request_firmware()
1410 * is not suitable for an usb transaction.
1411 *
1412 */
1413static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1414{
1415        const struct firmware *fw_entry = NULL;
1416        void  *fw_ptr;
1417        unsigned int pipe;
1418        unsigned int fwsize;
1419        int ret;
1420        u16 address;
1421
1422        if (!hdw->hdw_desc->fx2_firmware.cnt) {
1423                hdw->fw1_state = FW1_STATE_OK;
1424                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1425                           "Connected device type defines no firmware to upload; ignoring firmware");
1426                return -ENOTTY;
1427        }
1428
1429        hdw->fw1_state = FW1_STATE_FAILED; // default result
1430
1431        trace_firmware("pvr2_upload_firmware1");
1432
1433        ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1434                                   hdw->hdw_desc->fx2_firmware.cnt,
1435                                   hdw->hdw_desc->fx2_firmware.lst);
1436        if (ret < 0) {
1437                if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1438                return ret;
1439        }
1440
1441        usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1442
1443        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1444        fwsize = fw_entry->size;
1445
1446        if ((fwsize != 0x2000) &&
1447            (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1448                if (hdw->hdw_desc->flag_fx2_16kb) {
1449                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1450                                   "Wrong fx2 firmware size (expected 8192 or 16384, got %u)",
1451                                   fwsize);
1452                } else {
1453                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1454                                   "Wrong fx2 firmware size (expected 8192, got %u)",
1455                                   fwsize);
1456                }
1457                release_firmware(fw_entry);
1458                return -ENOMEM;
1459        }
1460
1461        fw_ptr = kmalloc(0x800, GFP_KERNEL);
1462        if (fw_ptr == NULL){
1463                release_firmware(fw_entry);
1464                return -ENOMEM;
1465        }
1466
1467        /* We have to hold the CPU during firmware upload. */
1468        pvr2_hdw_cpureset_assert(hdw,1);
1469
1470        /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1471           chunk. */
1472
1473        ret = 0;
1474        for (address = 0; address < fwsize; address += 0x800) {
1475                memcpy(fw_ptr, fw_entry->data + address, 0x800);
1476                ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1477                                       0, fw_ptr, 0x800, HZ);
1478        }
1479
1480        trace_firmware("Upload done, releasing device's CPU");
1481
1482        /* Now release the CPU.  It will disconnect and reconnect later. */
1483        pvr2_hdw_cpureset_assert(hdw,0);
1484
1485        kfree(fw_ptr);
1486        release_firmware(fw_entry);
1487
1488        trace_firmware("Upload done (%d bytes sent)",ret);
1489
1490        /* We should have written fwsize bytes */
1491        if (ret == fwsize) {
1492                hdw->fw1_state = FW1_STATE_RELOAD;
1493                return 0;
1494        }
1495
1496        return -EIO;
1497}
1498
1499
1500/*
1501 * pvr2_upload_firmware2()
1502 *
1503 * This uploads encoder firmware on endpoint 2.
1504 *
1505 */
1506
1507int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1508{
1509        const struct firmware *fw_entry = NULL;
1510        void  *fw_ptr;
1511        unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1512        int actual_length;
1513        int ret = 0;
1514        int fwidx;
1515        static const char *fw_files[] = {
1516                CX2341X_FIRM_ENC_FILENAME,
1517        };
1518
1519        if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1520                return 0;
1521        }
1522
1523        trace_firmware("pvr2_upload_firmware2");
1524
1525        ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1526                                   ARRAY_SIZE(fw_files), fw_files);
1527        if (ret < 0) return ret;
1528        fwidx = ret;
1529        ret = 0;
1530        /* Since we're about to completely reinitialize the encoder,
1531           invalidate our cached copy of its configuration state.  Next
1532           time we configure the encoder, then we'll fully configure it. */
1533        hdw->enc_cur_valid = 0;
1534
1535        /* Encoder is about to be reset so note that as far as we're
1536           concerned now, the encoder has never been run. */
1537        del_timer_sync(&hdw->encoder_run_timer);
1538        if (hdw->state_encoder_runok) {
1539                hdw->state_encoder_runok = 0;
1540                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1541        }
1542
1543        /* First prepare firmware loading */
1544        ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1545        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1546        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1547        ret |= pvr2_hdw_cmd_deep_reset(hdw);
1548        ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1549        ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1550        ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1551        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1552        ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1553        ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1554        ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1555        ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1556        ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1557        ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1558        ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1559        ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1560        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1561        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1562
1563        if (ret) {
1564                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1565                           "firmware2 upload prep failed, ret=%d",ret);
1566                release_firmware(fw_entry);
1567                goto done;
1568        }
1569
1570        /* Now send firmware */
1571
1572        fw_len = fw_entry->size;
1573
1574        if (fw_len % sizeof(u32)) {
1575                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1576                           "size of %s firmware must be a multiple of %zu bytes",
1577                           fw_files[fwidx],sizeof(u32));
1578                release_firmware(fw_entry);
1579                ret = -EINVAL;
1580                goto done;
1581        }
1582
1583        fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1584        if (fw_ptr == NULL){
1585                release_firmware(fw_entry);
1586                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1587                           "failed to allocate memory for firmware2 upload");
1588                ret = -ENOMEM;
1589                goto done;
1590        }
1591
1592        pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1593
1594        fw_done = 0;
1595        for (fw_done = 0; fw_done < fw_len;) {
1596                bcnt = fw_len - fw_done;
1597                if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1598                memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1599                /* Usbsnoop log shows that we must swap bytes... */
1600                /* Some background info: The data being swapped here is a
1601                   firmware image destined for the mpeg encoder chip that
1602                   lives at the other end of a USB endpoint.  The encoder
1603                   chip always talks in 32 bit chunks and its storage is
1604                   organized into 32 bit words.  However from the file
1605                   system to the encoder chip everything is purely a byte
1606                   stream.  The firmware file's contents are always 32 bit
1607                   swapped from what the encoder expects.  Thus the need
1608                   always exists to swap the bytes regardless of the endian
1609                   type of the host processor and therefore swab32() makes
1610                   the most sense. */
1611                for (icnt = 0; icnt < bcnt/4 ; icnt++)
1612                        ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1613
1614                ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1615                                    &actual_length, HZ);
1616                ret |= (actual_length != bcnt);
1617                if (ret) break;
1618                fw_done += bcnt;
1619        }
1620
1621        trace_firmware("upload of %s : %i / %i ",
1622                       fw_files[fwidx],fw_done,fw_len);
1623
1624        kfree(fw_ptr);
1625        release_firmware(fw_entry);
1626
1627        if (ret) {
1628                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1629                           "firmware2 upload transfer failure");
1630                goto done;
1631        }
1632
1633        /* Finish upload */
1634
1635        ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1636        ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1637        ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1638
1639        if (ret) {
1640                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1641                           "firmware2 upload post-proc failure");
1642        }
1643
1644 done:
1645        if (hdw->hdw_desc->signal_routing_scheme ==
1646            PVR2_ROUTING_SCHEME_GOTVIEW) {
1647                /* Ensure that GPIO 11 is set to output for GOTVIEW
1648                   hardware. */
1649                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1650        }
1651        return ret;
1652}
1653
1654
1655static const char *pvr2_get_state_name(unsigned int st)
1656{
1657        if (st < ARRAY_SIZE(pvr2_state_names)) {
1658                return pvr2_state_names[st];
1659        }
1660        return "???";
1661}
1662
1663static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1664{
1665        /* Even though we really only care about the video decoder chip at
1666           this point, we'll broadcast stream on/off to all sub-devices
1667           anyway, just in case somebody else wants to hear the
1668           command... */
1669        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1670                   (enablefl ? "on" : "off"));
1671        v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1672        v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1673        if (hdw->decoder_client_id) {
1674                /* We get here if the encoder has been noticed.  Otherwise
1675                   we'll issue a warning to the user (which should
1676                   normally never happen). */
1677                return 0;
1678        }
1679        if (!hdw->flag_decoder_missed) {
1680                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1681                           "WARNING: No decoder present");
1682                hdw->flag_decoder_missed = !0;
1683                trace_stbit("flag_decoder_missed",
1684                            hdw->flag_decoder_missed);
1685        }
1686        return -EIO;
1687}
1688
1689
1690int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1691{
1692        return hdw->master_state;
1693}
1694
1695
1696static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1697{
1698        if (!hdw->flag_tripped) return 0;
1699        hdw->flag_tripped = 0;
1700        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1701                   "Clearing driver error statuss");
1702        return !0;
1703}
1704
1705
1706int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1707{
1708        int fl;
1709        LOCK_TAKE(hdw->big_lock); do {
1710                fl = pvr2_hdw_untrip_unlocked(hdw);
1711        } while (0); LOCK_GIVE(hdw->big_lock);
1712        if (fl) pvr2_hdw_state_sched(hdw);
1713        return 0;
1714}
1715
1716
1717
1718
1719int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1720{
1721        return hdw->state_pipeline_req != 0;
1722}
1723
1724
1725int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1726{
1727        int ret,st;
1728        LOCK_TAKE(hdw->big_lock); do {
1729                pvr2_hdw_untrip_unlocked(hdw);
1730                if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1731                        hdw->state_pipeline_req = enable_flag != 0;
1732                        pvr2_trace(PVR2_TRACE_START_STOP,
1733                                   "/*--TRACE_STREAM--*/ %s",
1734                                   enable_flag ? "enable" : "disable");
1735                }
1736                pvr2_hdw_state_sched(hdw);
1737        } while (0); LOCK_GIVE(hdw->big_lock);
1738        if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1739        if (enable_flag) {
1740                while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1741                        if (st != PVR2_STATE_READY) return -EIO;
1742                        if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1743                }
1744        }
1745        return 0;
1746}
1747
1748
1749int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1750{
1751        int fl;
1752        LOCK_TAKE(hdw->big_lock);
1753        if ((fl = (hdw->desired_stream_type != config)) != 0) {
1754                hdw->desired_stream_type = config;
1755                hdw->state_pipeline_config = 0;
1756                trace_stbit("state_pipeline_config",
1757                            hdw->state_pipeline_config);
1758                pvr2_hdw_state_sched(hdw);
1759        }
1760        LOCK_GIVE(hdw->big_lock);
1761        if (fl) return 0;
1762        return pvr2_hdw_wait(hdw,0);
1763}
1764
1765
1766static int get_default_tuner_type(struct pvr2_hdw *hdw)
1767{
1768        int unit_number = hdw->unit_number;
1769        int tp = -1;
1770        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1771                tp = tuner[unit_number];
1772        }
1773        if (tp < 0) return -EINVAL;
1774        hdw->tuner_type = tp;
1775        hdw->tuner_updated = !0;
1776        return 0;
1777}
1778
1779
1780static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1781{
1782        int unit_number = hdw->unit_number;
1783        int tp = 0;
1784        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1785                tp = video_std[unit_number];
1786                if (tp) return tp;
1787        }
1788        return 0;
1789}
1790
1791
1792static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1793{
1794        int unit_number = hdw->unit_number;
1795        int tp = 0;
1796        if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1797                tp = tolerance[unit_number];
1798        }
1799        return tp;
1800}
1801
1802
1803static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1804{
1805        /* Try a harmless request to fetch the eeprom's address over
1806           endpoint 1.  See what happens.  Only the full FX2 image can
1807           respond to this.  If this probe fails then likely the FX2
1808           firmware needs be loaded. */
1809        int result;
1810        LOCK_TAKE(hdw->ctl_lock); do {
1811                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1812                result = pvr2_send_request_ex(hdw,HZ*1,!0,
1813                                           hdw->cmd_buffer,1,
1814                                           hdw->cmd_buffer,1);
1815                if (result < 0) break;
1816        } while(0); LOCK_GIVE(hdw->ctl_lock);
1817        if (result) {
1818                pvr2_trace(PVR2_TRACE_INIT,
1819                           "Probe of device endpoint 1 result status %d",
1820                           result);
1821        } else {
1822                pvr2_trace(PVR2_TRACE_INIT,
1823                           "Probe of device endpoint 1 succeeded");
1824        }
1825        return result == 0;
1826}
1827
1828struct pvr2_std_hack {
1829        v4l2_std_id pat;  /* Pattern to match */
1830        v4l2_std_id msk;  /* Which bits we care about */
1831        v4l2_std_id std;  /* What additional standards or default to set */
1832};
1833
1834/* This data structure labels specific combinations of standards from
1835   tveeprom that we'll try to recognize.  If we recognize one, then assume
1836   a specified default standard to use.  This is here because tveeprom only
1837   tells us about available standards not the intended default standard (if
1838   any) for the device in question.  We guess the default based on what has
1839   been reported as available.  Note that this is only for guessing a
1840   default - which can always be overridden explicitly - and if the user
1841   has otherwise named a default then that default will always be used in
1842   place of this table. */
1843static const struct pvr2_std_hack std_eeprom_maps[] = {
1844        {       /* PAL(B/G) */
1845                .pat = V4L2_STD_B|V4L2_STD_GH,
1846                .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1847        },
1848        {       /* NTSC(M) */
1849                .pat = V4L2_STD_MN,
1850                .std = V4L2_STD_NTSC_M,
1851        },
1852        {       /* PAL(I) */
1853                .pat = V4L2_STD_PAL_I,
1854                .std = V4L2_STD_PAL_I,
1855        },
1856        {       /* SECAM(L/L') */
1857                .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1858                .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1859        },
1860        {       /* PAL(D/D1/K) */
1861                .pat = V4L2_STD_DK,
1862                .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1863        },
1864};
1865
1866static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1867{
1868        char buf[40];
1869        unsigned int bcnt;
1870        v4l2_std_id std1,std2,std3;
1871
1872        std1 = get_default_standard(hdw);
1873        std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1874
1875        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1876        pvr2_trace(PVR2_TRACE_STD,
1877                   "Supported video standard(s) reported available in hardware: %.*s",
1878                   bcnt,buf);
1879
1880        hdw->std_mask_avail = hdw->std_mask_eeprom;
1881
1882        std2 = (std1|std3) & ~hdw->std_mask_avail;
1883        if (std2) {
1884                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1885                pvr2_trace(PVR2_TRACE_STD,
1886                           "Expanding supported video standards to include: %.*s",
1887                           bcnt,buf);
1888                hdw->std_mask_avail |= std2;
1889        }
1890
1891        hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
1892
1893        if (std1) {
1894                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1895                pvr2_trace(PVR2_TRACE_STD,
1896                           "Initial video standard forced to %.*s",
1897                           bcnt,buf);
1898                hdw->std_mask_cur = std1;
1899                hdw->std_dirty = !0;
1900                return;
1901        }
1902        if (std3) {
1903                bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1904                pvr2_trace(PVR2_TRACE_STD,
1905                           "Initial video standard (determined by device type): %.*s",
1906                           bcnt, buf);
1907                hdw->std_mask_cur = std3;
1908                hdw->std_dirty = !0;
1909                return;
1910        }
1911
1912        {
1913                unsigned int idx;
1914                for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1915                        if (std_eeprom_maps[idx].msk ?
1916                            ((std_eeprom_maps[idx].pat ^
1917                             hdw->std_mask_eeprom) &
1918                             std_eeprom_maps[idx].msk) :
1919                            (std_eeprom_maps[idx].pat !=
1920                             hdw->std_mask_eeprom)) continue;
1921                        bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1922                                                  std_eeprom_maps[idx].std);
1923                        pvr2_trace(PVR2_TRACE_STD,
1924                                   "Initial video standard guessed as %.*s",
1925                                   bcnt,buf);
1926                        hdw->std_mask_cur = std_eeprom_maps[idx].std;
1927                        hdw->std_dirty = !0;
1928                        return;
1929                }
1930        }
1931
1932}
1933
1934
1935static unsigned int pvr2_copy_i2c_addr_list(
1936        unsigned short *dst, const unsigned char *src,
1937        unsigned int dst_max)
1938{
1939        unsigned int cnt = 0;
1940        if (!src) return 0;
1941        while (src[cnt] && (cnt + 1) < dst_max) {
1942                dst[cnt] = src[cnt];
1943                cnt++;
1944        }
1945        dst[cnt] = I2C_CLIENT_END;
1946        return cnt;
1947}
1948
1949
1950static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
1951{
1952        /*
1953          Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
1954          for cx25840 causes that module to correctly set up its video
1955          scaling.  This is really a problem in the cx25840 module itself,
1956          but we work around it here.  The problem has not been seen in
1957          ivtv because there VBI is supported and set up.  We don't do VBI
1958          here (at least not yet) and thus we never attempted to even set
1959          it up.
1960        */
1961        struct v4l2_format fmt;
1962        if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
1963                /* We're not using a cx25840 so don't enable the hack */
1964                return;
1965        }
1966
1967        pvr2_trace(PVR2_TRACE_INIT,
1968                   "Module ID %u: Executing cx25840 VBI hack",
1969                   hdw->decoder_client_id);
1970        memset(&fmt, 0, sizeof(fmt));
1971        fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
1972        fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
1973        fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
1974        v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
1975                             vbi, s_sliced_fmt, &fmt.fmt.sliced);
1976}
1977
1978
1979static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
1980                                const struct pvr2_device_client_desc *cd)
1981{
1982        const char *fname;
1983        unsigned char mid;
1984        struct v4l2_subdev *sd;
1985        unsigned int i2ccnt;
1986        const unsigned char *p;
1987        /* Arbitrary count - max # i2c addresses we will probe */
1988        unsigned short i2caddr[25];
1989
1990        mid = cd->module_id;
1991        fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
1992        if (!fname) {
1993                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1994                           "Module ID %u for device %s has no name?  The driver might have a configuration problem.",
1995                           mid,
1996                           hdw->hdw_desc->description);
1997                return -EINVAL;
1998        }
1999        pvr2_trace(PVR2_TRACE_INIT,
2000                   "Module ID %u (%s) for device %s being loaded...",
2001                   mid, fname,
2002                   hdw->hdw_desc->description);
2003
2004        i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2005                                         ARRAY_SIZE(i2caddr));
2006        if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2007                         module_i2c_addresses[mid] : NULL) != NULL)) {
2008                /* Second chance: Try default i2c address list */
2009                i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2010                                                 ARRAY_SIZE(i2caddr));
2011                if (i2ccnt) {
2012                        pvr2_trace(PVR2_TRACE_INIT,
2013                                   "Module ID %u: Using default i2c address list",
2014                                   mid);
2015                }
2016        }
2017
2018        if (!i2ccnt) {
2019                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2020                           "Module ID %u (%s) for device %s: No i2c addresses.  The driver might have a configuration problem.",
2021                           mid, fname, hdw->hdw_desc->description);
2022                return -EINVAL;
2023        }
2024
2025        if (i2ccnt == 1) {
2026                pvr2_trace(PVR2_TRACE_INIT,
2027                           "Module ID %u: Setting up with specified i2c address 0x%x",
2028                           mid, i2caddr[0]);
2029                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2030                                         fname, i2caddr[0], NULL);
2031        } else {
2032                pvr2_trace(PVR2_TRACE_INIT,
2033                           "Module ID %u: Setting up with address probe list",
2034                           mid);
2035                sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2036                                         fname, 0, i2caddr);
2037        }
2038
2039        if (!sd) {
2040                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2041                           "Module ID %u (%s) for device %s failed to load.  Possible missing sub-device kernel module or initialization failure within module.",
2042                           mid, fname, hdw->hdw_desc->description);
2043                return -EIO;
2044        }
2045
2046        /* Tag this sub-device instance with the module ID we know about.
2047           In other places we'll use that tag to determine if the instance
2048           requires special handling. */
2049        sd->grp_id = mid;
2050
2051        pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2052
2053
2054        /* client-specific setup... */
2055        switch (mid) {
2056        case PVR2_CLIENT_ID_CX25840:
2057        case PVR2_CLIENT_ID_SAA7115:
2058                hdw->decoder_client_id = mid;
2059                break;
2060        default: break;
2061        }
2062
2063        return 0;
2064}
2065
2066
2067static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2068{
2069        unsigned int idx;
2070        const struct pvr2_string_table *cm;
2071        const struct pvr2_device_client_table *ct;
2072        int okFl = !0;
2073
2074        cm = &hdw->hdw_desc->client_modules;
2075        for (idx = 0; idx < cm->cnt; idx++) {
2076                request_module(cm->lst[idx]);
2077        }
2078
2079        ct = &hdw->hdw_desc->client_table;
2080        for (idx = 0; idx < ct->cnt; idx++) {
2081                if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2082        }
2083        if (!okFl) {
2084                hdw->flag_modulefail = !0;
2085                pvr2_hdw_render_useless(hdw);
2086        }
2087}
2088
2089
2090static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2091{
2092        int ret;
2093        unsigned int idx;
2094        struct pvr2_ctrl *cptr;
2095        int reloadFl = 0;
2096        if (hdw->hdw_desc->fx2_firmware.cnt) {
2097                if (!reloadFl) {
2098                        reloadFl =
2099                                (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2100                                 == 0);
2101                        if (reloadFl) {
2102                                pvr2_trace(PVR2_TRACE_INIT,
2103                                           "USB endpoint config looks strange; possibly firmware needs to be loaded");
2104                        }
2105                }
2106                if (!reloadFl) {
2107                        reloadFl = !pvr2_hdw_check_firmware(hdw);
2108                        if (reloadFl) {
2109                                pvr2_trace(PVR2_TRACE_INIT,
2110                                           "Check for FX2 firmware failed; possibly firmware needs to be loaded");
2111                        }
2112                }
2113                if (reloadFl) {
2114                        if (pvr2_upload_firmware1(hdw) != 0) {
2115                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2116                                           "Failure uploading firmware1");
2117                        }
2118                        return;
2119                }
2120        }
2121        hdw->fw1_state = FW1_STATE_OK;
2122
2123        if (!pvr2_hdw_dev_ok(hdw)) return;
2124
2125        hdw->force_dirty = !0;
2126
2127        if (!hdw->hdw_desc->flag_no_powerup) {
2128                pvr2_hdw_cmd_powerup(hdw);
2129                if (!pvr2_hdw_dev_ok(hdw)) return;
2130        }
2131
2132        /* Take the IR chip out of reset, if appropriate */
2133        if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2134                pvr2_issue_simple_cmd(hdw,
2135                                      FX2CMD_HCW_ZILOG_RESET |
2136                                      (1 << 8) |
2137                                      ((0) << 16));
2138        }
2139
2140        // This step MUST happen after the earlier powerup step.
2141        pvr2_i2c_core_init(hdw);
2142        if (!pvr2_hdw_dev_ok(hdw)) return;
2143
2144        pvr2_hdw_load_modules(hdw);
2145        if (!pvr2_hdw_dev_ok(hdw)) return;
2146
2147        v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2148
2149        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2150                cptr = hdw->controls + idx;
2151                if (cptr->info->skip_init) continue;
2152                if (!cptr->info->set_value) continue;
2153                cptr->info->set_value(cptr,~0,cptr->info->default_value);
2154        }
2155
2156        pvr2_hdw_cx25840_vbi_hack(hdw);
2157
2158        /* Set up special default values for the television and radio
2159           frequencies here.  It's not really important what these defaults
2160           are, but I set them to something usable in the Chicago area just
2161           to make driver testing a little easier. */
2162
2163        hdw->freqValTelevision = default_tv_freq;
2164        hdw->freqValRadio = default_radio_freq;
2165
2166        // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2167        // thread-safe against the normal pvr2_send_request() mechanism.
2168        // (We should make it thread safe).
2169
2170        if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2171                ret = pvr2_hdw_get_eeprom_addr(hdw);
2172                if (!pvr2_hdw_dev_ok(hdw)) return;
2173                if (ret < 0) {
2174                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2175                                   "Unable to determine location of eeprom, skipping");
2176                } else {
2177                        hdw->eeprom_addr = ret;
2178                        pvr2_eeprom_analyze(hdw);
2179                        if (!pvr2_hdw_dev_ok(hdw)) return;
2180                }
2181        } else {
2182                hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2183                hdw->tuner_updated = !0;
2184                hdw->std_mask_eeprom = V4L2_STD_ALL;
2185        }
2186
2187        if (hdw->serial_number) {
2188                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2189                                "sn-%lu", hdw->serial_number);
2190        } else if (hdw->unit_number >= 0) {
2191                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2192                                "unit-%c",
2193                                hdw->unit_number + 'a');
2194        } else {
2195                idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2196                                "unit-??");
2197        }
2198        hdw->identifier[idx] = 0;
2199
2200        pvr2_hdw_setup_std(hdw);
2201
2202        if (!get_default_tuner_type(hdw)) {
2203                pvr2_trace(PVR2_TRACE_INIT,
2204                           "pvr2_hdw_setup: Tuner type overridden to %d",
2205                           hdw->tuner_type);
2206        }
2207
2208
2209        if (!pvr2_hdw_dev_ok(hdw)) return;
2210
2211        if (hdw->hdw_desc->signal_routing_scheme ==
2212            PVR2_ROUTING_SCHEME_GOTVIEW) {
2213                /* Ensure that GPIO 11 is set to output for GOTVIEW
2214                   hardware. */
2215                pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2216        }
2217
2218        pvr2_hdw_commit_setup(hdw);
2219
2220        hdw->vid_stream = pvr2_stream_create();
2221        if (!pvr2_hdw_dev_ok(hdw)) return;
2222        pvr2_trace(PVR2_TRACE_INIT,
2223                   "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2224        if (hdw->vid_stream) {
2225                idx = get_default_error_tolerance(hdw);
2226                if (idx) {
2227                        pvr2_trace(PVR2_TRACE_INIT,
2228                                   "pvr2_hdw_setup: video stream %p setting tolerance %u",
2229                                   hdw->vid_stream,idx);
2230                }
2231                pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2232                                  PVR2_VID_ENDPOINT,idx);
2233        }
2234
2235        if (!pvr2_hdw_dev_ok(hdw)) return;
2236
2237        hdw->flag_init_ok = !0;
2238
2239        pvr2_hdw_state_sched(hdw);
2240}
2241
2242
2243/* Set up the structure and attempt to put the device into a usable state.
2244   This can be a time-consuming operation, which is why it is not done
2245   internally as part of the create() step. */
2246static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2247{
2248        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2249        do {
2250                pvr2_hdw_setup_low(hdw);
2251                pvr2_trace(PVR2_TRACE_INIT,
2252                           "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2253                           hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2254                if (pvr2_hdw_dev_ok(hdw)) {
2255                        if (hdw->flag_init_ok) {
2256                                pvr2_trace(
2257                                        PVR2_TRACE_INFO,
2258                                        "Device initialization completed successfully.");
2259                                break;
2260                        }
2261                        if (hdw->fw1_state == FW1_STATE_RELOAD) {
2262                                pvr2_trace(
2263                                        PVR2_TRACE_INFO,
2264                                        "Device microcontroller firmware (re)loaded; it should now reset and reconnect.");
2265                                break;
2266                        }
2267                        pvr2_trace(
2268                                PVR2_TRACE_ERROR_LEGS,
2269                                "Device initialization was not successful.");
2270                        if (hdw->fw1_state == FW1_STATE_MISSING) {
2271                                pvr2_trace(
2272                                        PVR2_TRACE_ERROR_LEGS,
2273                                        "Giving up since device microcontroller firmware appears to be missing.");
2274                                break;
2275                        }
2276                }
2277                if (hdw->flag_modulefail) {
2278                        pvr2_trace(
2279                                PVR2_TRACE_ERROR_LEGS,
2280                                "***WARNING*** pvrusb2 driver initialization failed due to the failure of one or more sub-device kernel modules.");
2281                        pvr2_trace(
2282                                PVR2_TRACE_ERROR_LEGS,
2283                                "You need to resolve the failing condition before this driver can function.  There should be some earlier messages giving more information about the problem.");
2284                        break;
2285                }
2286                if (procreload) {
2287                        pvr2_trace(
2288                                PVR2_TRACE_ERROR_LEGS,
2289                                "Attempting pvrusb2 recovery by reloading primary firmware.");
2290                        pvr2_trace(
2291                                PVR2_TRACE_ERROR_LEGS,
2292                                "If this works, device should disconnect and reconnect in a sane state.");
2293                        hdw->fw1_state = FW1_STATE_UNKNOWN;
2294                        pvr2_upload_firmware1(hdw);
2295                } else {
2296                        pvr2_trace(
2297                                PVR2_TRACE_ERROR_LEGS,
2298                                "***WARNING*** pvrusb2 device hardware appears to be jammed and I can't clear it.");
2299                        pvr2_trace(
2300                                PVR2_TRACE_ERROR_LEGS,
2301                                "You might need to power cycle the pvrusb2 device in order to recover.");
2302                }
2303        } while (0);
2304        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2305}
2306
2307
2308/* Perform second stage initialization.  Set callback pointer first so that
2309   we can avoid a possible initialization race (if the kernel thread runs
2310   before the callback has been set). */
2311int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2312                        void (*callback_func)(void *),
2313                        void *callback_data)
2314{
2315        LOCK_TAKE(hdw->big_lock); do {
2316                if (hdw->flag_disconnected) {
2317                        /* Handle a race here: If we're already
2318                           disconnected by this point, then give up.  If we
2319                           get past this then we'll remain connected for
2320                           the duration of initialization since the entire
2321                           initialization sequence is now protected by the
2322                           big_lock. */
2323                        break;
2324                }
2325                hdw->state_data = callback_data;
2326                hdw->state_func = callback_func;
2327                pvr2_hdw_setup(hdw);
2328        } while (0); LOCK_GIVE(hdw->big_lock);
2329        return hdw->flag_init_ok;
2330}
2331
2332
2333/* Create, set up, and return a structure for interacting with the
2334   underlying hardware.  */
2335struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2336                                 const struct usb_device_id *devid)
2337{
2338        unsigned int idx,cnt1,cnt2,m;
2339        struct pvr2_hdw *hdw = NULL;
2340        int valid_std_mask;
2341        struct pvr2_ctrl *cptr;
2342        struct usb_device *usb_dev;
2343        const struct pvr2_device_desc *hdw_desc;
2344        __u8 ifnum;
2345        struct v4l2_queryctrl qctrl;
2346        struct pvr2_ctl_info *ciptr;
2347
2348        usb_dev = interface_to_usbdev(intf);
2349
2350        hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2351
2352        if (hdw_desc == NULL) {
2353                pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create: No device description pointer, unable to continue.");
2354                pvr2_trace(PVR2_TRACE_INIT,
2355                           "If you have a new device type, please contact Mike Isely <isely@pobox.com> to get it included in the driver");
2356                goto fail;
2357        }
2358
2359        hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2360        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2361                   hdw,hdw_desc->description);
2362        pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2363                hdw_desc->description);
2364        if (hdw_desc->flag_is_experimental) {
2365                pvr2_trace(PVR2_TRACE_INFO, "**********");
2366                pvr2_trace(PVR2_TRACE_INFO,
2367                           "WARNING: Support for this device (%s) is experimental.",
2368                                                              hdw_desc->description);
2369                pvr2_trace(PVR2_TRACE_INFO,
2370                           "Important functionality might not be entirely working.");
2371                pvr2_trace(PVR2_TRACE_INFO,
2372                           "Please consider contacting the driver author to help with further stabilization of the driver.");
2373                pvr2_trace(PVR2_TRACE_INFO, "**********");
2374        }
2375        if (!hdw) goto fail;
2376
2377        timer_setup(&hdw->quiescent_timer, pvr2_hdw_quiescent_timeout, 0);
2378
2379        timer_setup(&hdw->decoder_stabilization_timer,
2380                    pvr2_hdw_decoder_stabilization_timeout, 0);
2381
2382        timer_setup(&hdw->encoder_wait_timer, pvr2_hdw_encoder_wait_timeout,
2383                    0);
2384
2385        timer_setup(&hdw->encoder_run_timer, pvr2_hdw_encoder_run_timeout, 0);
2386
2387        hdw->master_state = PVR2_STATE_DEAD;
2388
2389        init_waitqueue_head(&hdw->state_wait_data);
2390
2391        hdw->tuner_signal_stale = !0;
2392        cx2341x_fill_defaults(&hdw->enc_ctl_state);
2393
2394        /* Calculate which inputs are OK */
2395        m = 0;
2396        if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2397        if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2398                m |= 1 << PVR2_CVAL_INPUT_DTV;
2399        }
2400        if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2401        if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2402        if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2403        hdw->input_avail_mask = m;
2404        hdw->input_allowed_mask = hdw->input_avail_mask;
2405
2406        /* If not a hybrid device, pathway_state never changes.  So
2407           initialize it here to what it should forever be. */
2408        if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2409                hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2410        } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2411                hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2412        }
2413
2414        hdw->control_cnt = CTRLDEF_COUNT;
2415        hdw->control_cnt += MPEGDEF_COUNT;
2416        hdw->controls = kcalloc(hdw->control_cnt, sizeof(struct pvr2_ctrl),
2417                                GFP_KERNEL);
2418        if (!hdw->controls) goto fail;
2419        hdw->hdw_desc = hdw_desc;
2420        hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2421        for (idx = 0; idx < hdw->control_cnt; idx++) {
2422                cptr = hdw->controls + idx;
2423                cptr->hdw = hdw;
2424        }
2425        for (idx = 0; idx < 32; idx++) {
2426                hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2427        }
2428        for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2429                cptr = hdw->controls + idx;
2430                cptr->info = control_defs+idx;
2431        }
2432
2433        /* Ensure that default input choice is a valid one. */
2434        m = hdw->input_avail_mask;
2435        if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2436                if (!((1 << idx) & m)) continue;
2437                hdw->input_val = idx;
2438                break;
2439        }
2440
2441        /* Define and configure additional controls from cx2341x module. */
2442        hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2443                                      sizeof(*(hdw->mpeg_ctrl_info)),
2444                                      GFP_KERNEL);
2445        if (!hdw->mpeg_ctrl_info) goto fail;
2446        for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2447                cptr = hdw->controls + idx + CTRLDEF_COUNT;
2448                ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2449                ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2450                ciptr->name = mpeg_ids[idx].strid;
2451                ciptr->v4l_id = mpeg_ids[idx].id;
2452                ciptr->skip_init = !0;
2453                ciptr->get_value = ctrl_cx2341x_get;
2454                ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2455                ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2456                if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2457                qctrl.id = ciptr->v4l_id;
2458                cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2459                if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2460                        ciptr->set_value = ctrl_cx2341x_set;
2461                }
2462                strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2463                        PVR2_CTLD_INFO_DESC_SIZE);
2464                hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2465                ciptr->default_value = qctrl.default_value;
2466                switch (qctrl.type) {
2467                default:
2468                case V4L2_CTRL_TYPE_INTEGER:
2469                        ciptr->type = pvr2_ctl_int;
2470                        ciptr->def.type_int.min_value = qctrl.minimum;
2471                        ciptr->def.type_int.max_value = qctrl.maximum;
2472                        break;
2473                case V4L2_CTRL_TYPE_BOOLEAN:
2474                        ciptr->type = pvr2_ctl_bool;
2475                        break;
2476                case V4L2_CTRL_TYPE_MENU:
2477                        ciptr->type = pvr2_ctl_enum;
2478                        ciptr->def.type_enum.value_names =
2479                                cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2480                                                                ciptr->v4l_id);
2481                        for (cnt1 = 0;
2482                             ciptr->def.type_enum.value_names[cnt1] != NULL;
2483                             cnt1++) { }
2484                        ciptr->def.type_enum.count = cnt1;
2485                        break;
2486                }
2487                cptr->info = ciptr;
2488        }
2489
2490        // Initialize control data regarding video standard masks
2491        valid_std_mask = pvr2_std_get_usable();
2492        for (idx = 0; idx < 32; idx++) {
2493                if (!(valid_std_mask & (1 << idx))) continue;
2494                cnt1 = pvr2_std_id_to_str(
2495                        hdw->std_mask_names[idx],
2496                        sizeof(hdw->std_mask_names[idx])-1,
2497                        1 << idx);
2498                hdw->std_mask_names[idx][cnt1] = 0;
2499        }
2500        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2501        if (cptr) {
2502                memcpy(&hdw->std_info_avail,cptr->info,
2503                       sizeof(hdw->std_info_avail));
2504                cptr->info = &hdw->std_info_avail;
2505                hdw->std_info_avail.def.type_bitmask.bit_names =
2506                        hdw->std_mask_ptrs;
2507                hdw->std_info_avail.def.type_bitmask.valid_bits =
2508                        valid_std_mask;
2509        }
2510        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2511        if (cptr) {
2512                memcpy(&hdw->std_info_cur,cptr->info,
2513                       sizeof(hdw->std_info_cur));
2514                cptr->info = &hdw->std_info_cur;
2515                hdw->std_info_cur.def.type_bitmask.bit_names =
2516                        hdw->std_mask_ptrs;
2517                hdw->std_info_cur.def.type_bitmask.valid_bits =
2518                        valid_std_mask;
2519        }
2520        cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDDETECT);
2521        if (cptr) {
2522                memcpy(&hdw->std_info_detect,cptr->info,
2523                       sizeof(hdw->std_info_detect));
2524                cptr->info = &hdw->std_info_detect;
2525                hdw->std_info_detect.def.type_bitmask.bit_names =
2526                        hdw->std_mask_ptrs;
2527                hdw->std_info_detect.def.type_bitmask.valid_bits =
2528                        valid_std_mask;
2529        }
2530
2531        hdw->cropcap_stale = !0;
2532        hdw->eeprom_addr = -1;
2533        hdw->unit_number = -1;
2534        hdw->v4l_minor_number_video = -1;
2535        hdw->v4l_minor_number_vbi = -1;
2536        hdw->v4l_minor_number_radio = -1;
2537        hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2538        if (!hdw->ctl_write_buffer) goto fail;
2539        hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2540        if (!hdw->ctl_read_buffer) goto fail;
2541        hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2542        if (!hdw->ctl_write_urb) goto fail;
2543        hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2544        if (!hdw->ctl_read_urb) goto fail;
2545
2546        if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2547                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2548                           "Error registering with v4l core, giving up");
2549                goto fail;
2550        }
2551        mutex_lock(&pvr2_unit_mtx);
2552        do {
2553                for (idx = 0; idx < PVR_NUM; idx++) {
2554                        if (unit_pointers[idx]) continue;
2555                        hdw->unit_number = idx;
2556                        unit_pointers[idx] = hdw;
2557                        break;
2558                }
2559        } while (0);
2560        mutex_unlock(&pvr2_unit_mtx);
2561
2562        cnt1 = 0;
2563        cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2564        cnt1 += cnt2;
2565        if (hdw->unit_number >= 0) {
2566                cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2567                                 ('a' + hdw->unit_number));
2568                cnt1 += cnt2;
2569        }
2570        if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2571        hdw->name[cnt1] = 0;
2572
2573        INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2574
2575        pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2576                   hdw->unit_number,hdw->name);
2577
2578        hdw->tuner_type = -1;
2579        hdw->flag_ok = !0;
2580
2581        hdw->usb_intf = intf;
2582        hdw->usb_dev = usb_dev;
2583
2584        usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2585
2586        ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2587        usb_set_interface(hdw->usb_dev,ifnum,0);
2588
2589        mutex_init(&hdw->ctl_lock_mutex);
2590        mutex_init(&hdw->big_lock_mutex);
2591
2592        return hdw;
2593 fail:
2594        if (hdw) {
2595                del_timer_sync(&hdw->quiescent_timer);
2596                del_timer_sync(&hdw->decoder_stabilization_timer);
2597                del_timer_sync(&hdw->encoder_run_timer);
2598                del_timer_sync(&hdw->encoder_wait_timer);
2599                flush_work(&hdw->workpoll);
2600                usb_free_urb(hdw->ctl_read_urb);
2601                usb_free_urb(hdw->ctl_write_urb);
2602                kfree(hdw->ctl_read_buffer);
2603                kfree(hdw->ctl_write_buffer);
2604                kfree(hdw->controls);
2605                kfree(hdw->mpeg_ctrl_info);
2606                kfree(hdw);
2607        }
2608        return NULL;
2609}
2610
2611
2612/* Remove _all_ associations between this driver and the underlying USB
2613   layer. */
2614static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2615{
2616        if (hdw->flag_disconnected) return;
2617        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2618        if (hdw->ctl_read_urb) {
2619                usb_kill_urb(hdw->ctl_read_urb);
2620                usb_free_urb(hdw->ctl_read_urb);
2621                hdw->ctl_read_urb = NULL;
2622        }
2623        if (hdw->ctl_write_urb) {
2624                usb_kill_urb(hdw->ctl_write_urb);
2625                usb_free_urb(hdw->ctl_write_urb);
2626                hdw->ctl_write_urb = NULL;
2627        }
2628        if (hdw->ctl_read_buffer) {
2629                kfree(hdw->ctl_read_buffer);
2630                hdw->ctl_read_buffer = NULL;
2631        }
2632        if (hdw->ctl_write_buffer) {
2633                kfree(hdw->ctl_write_buffer);
2634                hdw->ctl_write_buffer = NULL;
2635        }
2636        hdw->flag_disconnected = !0;
2637        /* If we don't do this, then there will be a dangling struct device
2638           reference to our disappearing device persisting inside the V4L
2639           core... */
2640        v4l2_device_disconnect(&hdw->v4l2_dev);
2641        hdw->usb_dev = NULL;
2642        hdw->usb_intf = NULL;
2643        pvr2_hdw_render_useless(hdw);
2644}
2645
2646void pvr2_hdw_set_v4l2_dev(struct pvr2_hdw *hdw, struct video_device *vdev)
2647{
2648        vdev->v4l2_dev = &hdw->v4l2_dev;
2649}
2650
2651/* Destroy hardware interaction structure */
2652void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2653{
2654        if (!hdw) return;
2655        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2656        flush_work(&hdw->workpoll);
2657        del_timer_sync(&hdw->quiescent_timer);
2658        del_timer_sync(&hdw->decoder_stabilization_timer);
2659        del_timer_sync(&hdw->encoder_run_timer);
2660        del_timer_sync(&hdw->encoder_wait_timer);
2661        if (hdw->fw_buffer) {
2662                kfree(hdw->fw_buffer);
2663                hdw->fw_buffer = NULL;
2664        }
2665        if (hdw->vid_stream) {
2666                pvr2_stream_destroy(hdw->vid_stream);
2667                hdw->vid_stream = NULL;
2668        }
2669        pvr2_i2c_core_done(hdw);
2670        v4l2_device_unregister(&hdw->v4l2_dev);
2671        pvr2_hdw_remove_usb_stuff(hdw);
2672        mutex_lock(&pvr2_unit_mtx);
2673        do {
2674                if ((hdw->unit_number >= 0) &&
2675                    (hdw->unit_number < PVR_NUM) &&
2676                    (unit_pointers[hdw->unit_number] == hdw)) {
2677                        unit_pointers[hdw->unit_number] = NULL;
2678                }
2679        } while (0);
2680        mutex_unlock(&pvr2_unit_mtx);
2681        kfree(hdw->controls);
2682        kfree(hdw->mpeg_ctrl_info);
2683        kfree(hdw);
2684}
2685
2686
2687int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2688{
2689        return (hdw && hdw->flag_ok);
2690}
2691
2692
2693/* Called when hardware has been unplugged */
2694void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2695{
2696        pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2697        LOCK_TAKE(hdw->big_lock);
2698        LOCK_TAKE(hdw->ctl_lock);
2699        pvr2_hdw_remove_usb_stuff(hdw);
2700        LOCK_GIVE(hdw->ctl_lock);
2701        LOCK_GIVE(hdw->big_lock);
2702}
2703
2704
2705/* Get the number of defined controls */
2706unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2707{
2708        return hdw->control_cnt;
2709}
2710
2711
2712/* Retrieve a control handle given its index (0..count-1) */
2713struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2714                                             unsigned int idx)
2715{
2716        if (idx >= hdw->control_cnt) return NULL;
2717        return hdw->controls + idx;
2718}
2719
2720
2721/* Retrieve a control handle given its index (0..count-1) */
2722struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2723                                          unsigned int ctl_id)
2724{
2725        struct pvr2_ctrl *cptr;
2726        unsigned int idx;
2727        int i;
2728
2729        /* This could be made a lot more efficient, but for now... */
2730        for (idx = 0; idx < hdw->control_cnt; idx++) {
2731                cptr = hdw->controls + idx;
2732                i = cptr->info->internal_id;
2733                if (i && (i == ctl_id)) return cptr;
2734        }
2735        return NULL;
2736}
2737
2738
2739/* Given a V4L ID, retrieve the control structure associated with it. */
2740struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2741{
2742        struct pvr2_ctrl *cptr;
2743        unsigned int idx;
2744        int i;
2745
2746        /* This could be made a lot more efficient, but for now... */
2747        for (idx = 0; idx < hdw->control_cnt; idx++) {
2748                cptr = hdw->controls + idx;
2749                i = cptr->info->v4l_id;
2750                if (i && (i == ctl_id)) return cptr;
2751        }
2752        return NULL;
2753}
2754
2755
2756/* Given a V4L ID for its immediate predecessor, retrieve the control
2757   structure associated with it. */
2758struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2759                                            unsigned int ctl_id)
2760{
2761        struct pvr2_ctrl *cptr,*cp2;
2762        unsigned int idx;
2763        int i;
2764
2765        /* This could be made a lot more efficient, but for now... */
2766        cp2 = NULL;
2767        for (idx = 0; idx < hdw->control_cnt; idx++) {
2768                cptr = hdw->controls + idx;
2769                i = cptr->info->v4l_id;
2770                if (!i) continue;
2771                if (i <= ctl_id) continue;
2772                if (cp2 && (cp2->info->v4l_id < i)) continue;
2773                cp2 = cptr;
2774        }
2775        return cp2;
2776        return NULL;
2777}
2778
2779
2780static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2781{
2782        switch (tp) {
2783        case pvr2_ctl_int: return "integer";
2784        case pvr2_ctl_enum: return "enum";
2785        case pvr2_ctl_bool: return "boolean";
2786        case pvr2_ctl_bitmask: return "bitmask";
2787        }
2788        return "";
2789}
2790
2791
2792static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2793                                    const char *name, int val)
2794{
2795        struct v4l2_control ctrl;
2796        struct v4l2_subdev *sd;
2797
2798        pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2799        memset(&ctrl, 0, sizeof(ctrl));
2800        ctrl.id = id;
2801        ctrl.value = val;
2802
2803        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev)
2804                v4l2_s_ctrl(NULL, sd->ctrl_handler, &ctrl);
2805}
2806
2807#define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2808        if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2809                pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2810        }
2811
2812static v4l2_std_id pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw)
2813{
2814        v4l2_std_id std;
2815        std = (v4l2_std_id)hdw->std_mask_avail;
2816        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2817                             video, querystd, &std);
2818        return std;
2819}
2820
2821/* Execute whatever commands are required to update the state of all the
2822   sub-devices so that they match our current control values. */
2823static void pvr2_subdev_update(struct pvr2_hdw *hdw)
2824{
2825        struct v4l2_subdev *sd;
2826        unsigned int id;
2827        pvr2_subdev_update_func fp;
2828
2829        pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
2830
2831        if (hdw->tuner_updated || hdw->force_dirty) {
2832                struct tuner_setup setup;
2833                pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
2834                           hdw->tuner_type);
2835                if (((int)(hdw->tuner_type)) >= 0) {
2836                        memset(&setup, 0, sizeof(setup));
2837                        setup.addr = ADDR_UNSET;
2838                        setup.type = hdw->tuner_type;
2839                        setup.mode_mask = T_RADIO | T_ANALOG_TV;
2840                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2841                                             tuner, s_type_addr, &setup);
2842                }
2843        }
2844
2845        if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
2846                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
2847                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2848                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2849                                             tuner, s_radio);
2850                } else {
2851                        v4l2_std_id vs;
2852                        vs = hdw->std_mask_cur;
2853                        v4l2_device_call_all(&hdw->v4l2_dev, 0,
2854                                             video, s_std, vs);
2855                        pvr2_hdw_cx25840_vbi_hack(hdw);
2856                }
2857                hdw->tuner_signal_stale = !0;
2858                hdw->cropcap_stale = !0;
2859        }
2860
2861        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
2862        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
2863        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
2864        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
2865        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
2866        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
2867        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
2868        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
2869        PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
2870
2871        if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
2872                struct v4l2_tuner vt;
2873                memset(&vt, 0, sizeof(vt));
2874                vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
2875                        V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
2876                vt.audmode = hdw->audiomode_val;
2877                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
2878        }
2879
2880        if (hdw->freqDirty || hdw->force_dirty) {
2881                unsigned long fv;
2882                struct v4l2_frequency freq;
2883                fv = pvr2_hdw_get_cur_freq(hdw);
2884                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
2885                if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
2886                memset(&freq, 0, sizeof(freq));
2887                if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
2888                        /* ((fv * 1000) / 62500) */
2889                        freq.frequency = (fv * 2) / 125;
2890                } else {
2891                        freq.frequency = fv / 62500;
2892                }
2893                /* tuner-core currently doesn't seem to care about this, but
2894                   let's set it anyway for completeness. */
2895                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
2896                        freq.type = V4L2_TUNER_RADIO;
2897                } else {
2898                        freq.type = V4L2_TUNER_ANALOG_TV;
2899                }
2900                freq.tuner = 0;
2901                v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
2902                                     s_frequency, &freq);
2903        }
2904
2905        if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
2906                struct v4l2_subdev_format format = {
2907                        .which = V4L2_SUBDEV_FORMAT_ACTIVE,
2908                };
2909
2910                format.format.width = hdw->res_hor_val;
2911                format.format.height = hdw->res_ver_val;
2912                format.format.code = MEDIA_BUS_FMT_FIXED;
2913                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
2914                           format.format.width, format.format.height);
2915                v4l2_device_call_all(&hdw->v4l2_dev, 0, pad, set_fmt,
2916                                     NULL, &format);
2917        }
2918
2919        if (hdw->srate_dirty || hdw->force_dirty) {
2920                u32 val;
2921                pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
2922                           hdw->srate_val);
2923                switch (hdw->srate_val) {
2924                default:
2925                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
2926                        val = 48000;
2927                        break;
2928                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
2929                        val = 44100;
2930                        break;
2931                case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
2932                        val = 32000;
2933                        break;
2934                }
2935                v4l2_device_call_all(&hdw->v4l2_dev, 0,
2936                                     audio, s_clock_freq, val);
2937        }
2938
2939        /* Unable to set crop parameters; there is apparently no equivalent
2940           for VIDIOC_S_CROP */
2941
2942        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
2943                id = sd->grp_id;
2944                if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
2945                fp = pvr2_module_update_functions[id];
2946                if (!fp) continue;
2947                (*fp)(hdw, sd);
2948        }
2949
2950        if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
2951                pvr2_hdw_status_poll(hdw);
2952        }
2953}
2954
2955
2956/* Figure out if we need to commit control changes.  If so, mark internal
2957   state flags to indicate this fact and return true.  Otherwise do nothing
2958   else and return false. */
2959static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2960{
2961        unsigned int idx;
2962        struct pvr2_ctrl *cptr;
2963        int value;
2964        int commit_flag = hdw->force_dirty;
2965        char buf[100];
2966        unsigned int bcnt,ccnt;
2967
2968        for (idx = 0; idx < hdw->control_cnt; idx++) {
2969                cptr = hdw->controls + idx;
2970                if (!cptr->info->is_dirty) continue;
2971                if (!cptr->info->is_dirty(cptr)) continue;
2972                commit_flag = !0;
2973
2974                if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2975                bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2976                                 cptr->info->name);
2977                value = 0;
2978                cptr->info->get_value(cptr,&value);
2979                pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2980                                                buf+bcnt,
2981                                                sizeof(buf)-bcnt,&ccnt);
2982                bcnt += ccnt;
2983                bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2984                                  get_ctrl_typename(cptr->info->type));
2985                pvr2_trace(PVR2_TRACE_CTL,
2986                           "/*--TRACE_COMMIT--*/ %.*s",
2987                           bcnt,buf);
2988        }
2989
2990        if (!commit_flag) {
2991                /* Nothing has changed */
2992                return 0;
2993        }
2994
2995        hdw->state_pipeline_config = 0;
2996        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2997        pvr2_hdw_state_sched(hdw);
2998
2999        return !0;
3000}
3001
3002
3003/* Perform all operations needed to commit all control changes.  This must
3004   be performed in synchronization with the pipeline state and is thus
3005   expected to be called as part of the driver's worker thread.  Return
3006   true if commit successful, otherwise return false to indicate that
3007   commit isn't possible at this time. */
3008static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3009{
3010        unsigned int idx;
3011        struct pvr2_ctrl *cptr;
3012        int disruptive_change;
3013
3014        if (hdw->input_dirty && hdw->state_pathway_ok &&
3015            (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3016              PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3017             hdw->pathway_state)) {
3018                /* Change of mode being asked for... */
3019                hdw->state_pathway_ok = 0;
3020                trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3021        }
3022        if (!hdw->state_pathway_ok) {
3023                /* Can't commit anything until pathway is ok. */
3024                return 0;
3025        }
3026
3027        /* Handle some required side effects when the video standard is
3028           changed.... */
3029        if (hdw->std_dirty) {
3030                int nvres;
3031                int gop_size;
3032                if (hdw->std_mask_cur & V4L2_STD_525_60) {
3033                        nvres = 480;
3034                        gop_size = 15;
3035                } else {
3036                        nvres = 576;
3037                        gop_size = 12;
3038                }
3039                /* Rewrite the vertical resolution to be appropriate to the
3040                   video standard that has been selected. */
3041                if (nvres != hdw->res_ver_val) {
3042                        hdw->res_ver_val = nvres;
3043                        hdw->res_ver_dirty = !0;
3044                }
3045                /* Rewrite the GOP size to be appropriate to the video
3046                   standard that has been selected. */
3047                if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3048                        struct v4l2_ext_controls cs;
3049                        struct v4l2_ext_control c1;
3050                        memset(&cs, 0, sizeof(cs));
3051                        memset(&c1, 0, sizeof(c1));
3052                        cs.controls = &c1;
3053                        cs.count = 1;
3054                        c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3055                        c1.value = gop_size;
3056                        cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3057                                          VIDIOC_S_EXT_CTRLS);
3058                }
3059        }
3060
3061        /* The broadcast decoder can only scale down, so if
3062         * res_*_dirty && crop window < output format ==> enlarge crop.
3063         *
3064         * The mpeg encoder receives fields of res_hor_val dots and
3065         * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3066         */
3067        if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3068                hdw->cropw_val = hdw->res_hor_val;
3069                hdw->cropw_dirty = !0;
3070        } else if (hdw->cropw_dirty) {
3071                hdw->res_hor_dirty = !0;           /* must rescale */
3072                hdw->res_hor_val = min(720, hdw->cropw_val);
3073        }
3074        if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3075                hdw->croph_val = hdw->res_ver_val;
3076                hdw->croph_dirty = !0;
3077        } else if (hdw->croph_dirty) {
3078                int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3079                hdw->res_ver_dirty = !0;
3080                hdw->res_ver_val = min(nvres, hdw->croph_val);
3081        }
3082
3083        /* If any of the below has changed, then we can't do the update
3084           while the pipeline is running.  Pipeline must be paused first
3085           and decoder -> encoder connection be made quiescent before we
3086           can proceed. */
3087        disruptive_change =
3088                (hdw->std_dirty ||
3089                 hdw->enc_unsafe_stale ||
3090                 hdw->srate_dirty ||
3091                 hdw->res_ver_dirty ||
3092                 hdw->res_hor_dirty ||
3093                 hdw->cropw_dirty ||
3094                 hdw->croph_dirty ||
3095                 hdw->input_dirty ||
3096                 (hdw->active_stream_type != hdw->desired_stream_type));
3097        if (disruptive_change && !hdw->state_pipeline_idle) {
3098                /* Pipeline is not idle; we can't proceed.  Arrange to
3099                   cause pipeline to stop so that we can try this again
3100                   later.... */
3101                hdw->state_pipeline_pause = !0;
3102                return 0;
3103        }
3104
3105        if (hdw->srate_dirty) {
3106                /* Write new sample rate into control structure since
3107                 * the master copy is stale.  We must track srate
3108                 * separate from the mpeg control structure because
3109                 * other logic also uses this value. */
3110                struct v4l2_ext_controls cs;
3111                struct v4l2_ext_control c1;
3112                memset(&cs,0,sizeof(cs));
3113                memset(&c1,0,sizeof(c1));
3114                cs.controls = &c1;
3115                cs.count = 1;
3116                c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3117                c1.value = hdw->srate_val;
3118                cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3119        }
3120
3121        if (hdw->active_stream_type != hdw->desired_stream_type) {
3122                /* Handle any side effects of stream config here */
3123                hdw->active_stream_type = hdw->desired_stream_type;
3124        }
3125
3126        if (hdw->hdw_desc->signal_routing_scheme ==
3127            PVR2_ROUTING_SCHEME_GOTVIEW) {
3128                u32 b;
3129                /* Handle GOTVIEW audio switching */
3130                pvr2_hdw_gpio_get_out(hdw,&b);
3131                if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3132                        /* Set GPIO 11 */
3133                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3134                } else {
3135                        /* Clear GPIO 11 */
3136                        pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3137                }
3138        }
3139
3140        /* Check and update state for all sub-devices. */
3141        pvr2_subdev_update(hdw);
3142
3143        hdw->tuner_updated = 0;
3144        hdw->force_dirty = 0;
3145        for (idx = 0; idx < hdw->control_cnt; idx++) {
3146                cptr = hdw->controls + idx;
3147                if (!cptr->info->clear_dirty) continue;
3148                cptr->info->clear_dirty(cptr);
3149        }
3150
3151        if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3152            hdw->state_encoder_run) {
3153                /* If encoder isn't running or it can't be touched, then
3154                   this will get worked out later when we start the
3155                   encoder. */
3156                if (pvr2_encoder_adjust(hdw) < 0) return !0;
3157        }
3158
3159        hdw->state_pipeline_config = !0;
3160        /* Hardware state may have changed in a way to cause the cropping
3161           capabilities to have changed.  So mark it stale, which will
3162           cause a later re-fetch. */
3163        trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3164        return !0;
3165}
3166
3167
3168int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3169{
3170        int fl;
3171        LOCK_TAKE(hdw->big_lock);
3172        fl = pvr2_hdw_commit_setup(hdw);
3173        LOCK_GIVE(hdw->big_lock);
3174        if (!fl) return 0;
3175        return pvr2_hdw_wait(hdw,0);
3176}
3177
3178
3179static void pvr2_hdw_worker_poll(struct work_struct *work)
3180{
3181        int fl = 0;
3182        struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3183        LOCK_TAKE(hdw->big_lock); do {
3184                fl = pvr2_hdw_state_eval(hdw);
3185        } while (0); LOCK_GIVE(hdw->big_lock);
3186        if (fl && hdw->state_func) {
3187                hdw->state_func(hdw->state_data);
3188        }
3189}
3190
3191
3192static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3193{
3194        return wait_event_interruptible(
3195                hdw->state_wait_data,
3196                (hdw->state_stale == 0) &&
3197                (!state || (hdw->master_state != state)));
3198}
3199
3200
3201/* Return name for this driver instance */
3202const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3203{
3204        return hdw->name;
3205}
3206
3207
3208const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3209{
3210        return hdw->hdw_desc->description;
3211}
3212
3213
3214const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3215{
3216        return hdw->hdw_desc->shortname;
3217}
3218
3219
3220int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3221{
3222        int result;
3223        LOCK_TAKE(hdw->ctl_lock); do {
3224                hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3225                result = pvr2_send_request(hdw,
3226                                           hdw->cmd_buffer,1,
3227                                           hdw->cmd_buffer,1);
3228                if (result < 0) break;
3229                result = (hdw->cmd_buffer[0] != 0);
3230        } while(0); LOCK_GIVE(hdw->ctl_lock);
3231        return result;
3232}
3233
3234
3235/* Execute poll of tuner status */
3236void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3237{
3238        LOCK_TAKE(hdw->big_lock); do {
3239                pvr2_hdw_status_poll(hdw);
3240        } while (0); LOCK_GIVE(hdw->big_lock);
3241}
3242
3243
3244static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3245{
3246        if (!hdw->cropcap_stale) {
3247                return 0;
3248        }
3249        pvr2_hdw_status_poll(hdw);
3250        if (hdw->cropcap_stale) {
3251                return -EIO;
3252        }
3253        return 0;
3254}
3255
3256
3257/* Return information about cropping capabilities */
3258int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3259{
3260        int stat = 0;
3261        LOCK_TAKE(hdw->big_lock);
3262        stat = pvr2_hdw_check_cropcap(hdw);
3263        if (!stat) {
3264                memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3265        }
3266        LOCK_GIVE(hdw->big_lock);
3267        return stat;
3268}
3269
3270
3271/* Return information about the tuner */
3272int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3273{
3274        LOCK_TAKE(hdw->big_lock); do {
3275                if (hdw->tuner_signal_stale) {
3276                        pvr2_hdw_status_poll(hdw);
3277                }
3278                memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3279        } while (0); LOCK_GIVE(hdw->big_lock);
3280        return 0;
3281}
3282
3283
3284/* Get handle to video output stream */
3285struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3286{
3287        return hp->vid_stream;
3288}
3289
3290
3291void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3292{
3293        int nr = pvr2_hdw_get_unit_number(hdw);
3294        LOCK_TAKE(hdw->big_lock);
3295        do {
3296                printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3297                v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3298                pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3299                cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3300                pvr2_hdw_state_log_state(hdw);
3301                printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3302        } while (0);
3303        LOCK_GIVE(hdw->big_lock);
3304}
3305
3306
3307/* Grab EEPROM contents, needed for direct method. */
3308#define EEPROM_SIZE 8192
3309#define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3310static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3311{
3312        struct i2c_msg msg[2];
3313        u8 *eeprom;
3314        u8 iadd[2];
3315        u8 addr;
3316        u16 eepromSize;
3317        unsigned int offs;
3318        int ret;
3319        int mode16 = 0;
3320        unsigned pcnt,tcnt;
3321        eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3322        if (!eeprom) {
3323                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3324                           "Failed to allocate memory required to read eeprom");
3325                return NULL;
3326        }
3327
3328        trace_eeprom("Value for eeprom addr from controller was 0x%x",
3329                     hdw->eeprom_addr);
3330        addr = hdw->eeprom_addr;
3331        /* Seems that if the high bit is set, then the *real* eeprom
3332           address is shifted right now bit position (noticed this in
3333           newer PVR USB2 hardware) */
3334        if (addr & 0x80) addr >>= 1;
3335
3336        /* FX2 documentation states that a 16bit-addressed eeprom is
3337           expected if the I2C address is an odd number (yeah, this is
3338           strange but it's what they do) */
3339        mode16 = (addr & 1);
3340        eepromSize = (mode16 ? EEPROM_SIZE : 256);
3341        trace_eeprom("Examining %d byte eeprom at location 0x%x using %d bit addressing",
3342                     eepromSize, addr,
3343                     mode16 ? 16 : 8);
3344
3345        msg[0].addr = addr;
3346        msg[0].flags = 0;
3347        msg[0].len = mode16 ? 2 : 1;
3348        msg[0].buf = iadd;
3349        msg[1].addr = addr;
3350        msg[1].flags = I2C_M_RD;
3351
3352        /* We have to do the actual eeprom data fetch ourselves, because
3353           (1) we're only fetching part of the eeprom, and (2) if we were
3354           getting the whole thing our I2C driver can't grab it in one
3355           pass - which is what tveeprom is otherwise going to attempt */
3356        memset(eeprom,0,EEPROM_SIZE);
3357        for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3358                pcnt = 16;
3359                if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3360                offs = tcnt + (eepromSize - EEPROM_SIZE);
3361                if (mode16) {
3362                        iadd[0] = offs >> 8;
3363                        iadd[1] = offs;
3364                } else {
3365                        iadd[0] = offs;
3366                }
3367                msg[1].len = pcnt;
3368                msg[1].buf = eeprom+tcnt;
3369                if ((ret = i2c_transfer(&hdw->i2c_adap,
3370                                        msg,ARRAY_SIZE(msg))) != 2) {
3371                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3372                                   "eeprom fetch set offs err=%d",ret);
3373                        kfree(eeprom);
3374                        return NULL;
3375                }
3376        }
3377        return eeprom;
3378}
3379
3380
3381void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3382                                int mode,
3383                                int enable_flag)
3384{
3385        int ret;
3386        u16 address;
3387        unsigned int pipe;
3388        LOCK_TAKE(hdw->big_lock); do {
3389                if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3390
3391                if (!enable_flag) {
3392                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3393                                   "Cleaning up after CPU firmware fetch");
3394                        kfree(hdw->fw_buffer);
3395                        hdw->fw_buffer = NULL;
3396                        hdw->fw_size = 0;
3397                        if (hdw->fw_cpu_flag) {
3398                                /* Now release the CPU.  It will disconnect
3399                                   and reconnect later. */
3400                                pvr2_hdw_cpureset_assert(hdw,0);
3401                        }
3402                        break;
3403                }
3404
3405                hdw->fw_cpu_flag = (mode != 2);
3406                if (hdw->fw_cpu_flag) {
3407                        hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3408                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3409                                   "Preparing to suck out CPU firmware (size=%u)",
3410                                   hdw->fw_size);
3411                        hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3412                        if (!hdw->fw_buffer) {
3413                                hdw->fw_size = 0;
3414                                break;
3415                        }
3416
3417                        /* We have to hold the CPU during firmware upload. */
3418                        pvr2_hdw_cpureset_assert(hdw,1);
3419
3420                        /* download the firmware from address 0000-1fff in 2048
3421                           (=0x800) bytes chunk. */
3422
3423                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3424                                   "Grabbing CPU firmware");
3425                        pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3426                        for(address = 0; address < hdw->fw_size;
3427                            address += 0x800) {
3428                                ret = usb_control_msg(hdw->usb_dev,pipe,
3429                                                      0xa0,0xc0,
3430                                                      address,0,
3431                                                      hdw->fw_buffer+address,
3432                                                      0x800,HZ);
3433                                if (ret < 0) break;
3434                        }
3435
3436                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3437                                   "Done grabbing CPU firmware");
3438                } else {
3439                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3440                                   "Sucking down EEPROM contents");
3441                        hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3442                        if (!hdw->fw_buffer) {
3443                                pvr2_trace(PVR2_TRACE_FIRMWARE,
3444                                           "EEPROM content suck failed.");
3445                                break;
3446                        }
3447                        hdw->fw_size = EEPROM_SIZE;
3448                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3449                                   "Done sucking down EEPROM contents");
3450                }
3451
3452        } while (0); LOCK_GIVE(hdw->big_lock);
3453}
3454
3455
3456/* Return true if we're in a mode for retrieval CPU firmware */
3457int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3458{
3459        return hdw->fw_buffer != NULL;
3460}
3461
3462
3463int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3464                       char *buf,unsigned int cnt)
3465{
3466        int ret = -EINVAL;
3467        LOCK_TAKE(hdw->big_lock); do {
3468                if (!buf) break;
3469                if (!cnt) break;
3470
3471                if (!hdw->fw_buffer) {
3472                        ret = -EIO;
3473                        break;
3474                }
3475
3476                if (offs >= hdw->fw_size) {
3477                        pvr2_trace(PVR2_TRACE_FIRMWARE,
3478                                   "Read firmware data offs=%d EOF",
3479                                   offs);
3480                        ret = 0;
3481                        break;
3482                }
3483
3484                if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3485
3486                memcpy(buf,hdw->fw_buffer+offs,cnt);
3487
3488                pvr2_trace(PVR2_TRACE_FIRMWARE,
3489                           "Read firmware data offs=%d cnt=%d",
3490                           offs,cnt);
3491                ret = cnt;
3492        } while (0); LOCK_GIVE(hdw->big_lock);
3493
3494        return ret;
3495}
3496
3497
3498int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3499                                  enum pvr2_v4l_type index)
3500{
3501        switch (index) {
3502        case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3503        case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3504        case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3505        default: return -1;
3506        }
3507}
3508
3509
3510/* Store a v4l minor device number */
3511void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3512                                     enum pvr2_v4l_type index,int v)
3513{
3514        switch (index) {
3515        case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;break;
3516        case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;break;
3517        case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;break;
3518        default: break;
3519        }
3520}
3521
3522
3523static void pvr2_ctl_write_complete(struct urb *urb)
3524{
3525        struct pvr2_hdw *hdw = urb->context;
3526        hdw->ctl_write_pend_flag = 0;
3527        if (hdw->ctl_read_pend_flag) return;
3528        complete(&hdw->ctl_done);
3529}
3530
3531
3532static void pvr2_ctl_read_complete(struct urb *urb)
3533{
3534        struct pvr2_hdw *hdw = urb->context;
3535        hdw->ctl_read_pend_flag = 0;
3536        if (hdw->ctl_write_pend_flag) return;
3537        complete(&hdw->ctl_done);
3538}
3539
3540struct hdw_timer {
3541        struct timer_list timer;
3542        struct pvr2_hdw *hdw;
3543};
3544
3545static void pvr2_ctl_timeout(struct timer_list *t)
3546{
3547        struct hdw_timer *timer = from_timer(timer, t, timer);
3548        struct pvr2_hdw *hdw = timer->hdw;
3549
3550        if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3551                hdw->ctl_timeout_flag = !0;
3552                if (hdw->ctl_write_pend_flag)
3553                        usb_unlink_urb(hdw->ctl_write_urb);
3554                if (hdw->ctl_read_pend_flag)
3555                        usb_unlink_urb(hdw->ctl_read_urb);
3556        }
3557}
3558
3559
3560/* Issue a command and get a response from the device.  This extended
3561   version includes a probe flag (which if set means that device errors
3562   should not be logged or treated as fatal) and a timeout in jiffies.
3563   This can be used to non-lethally probe the health of endpoint 1. */
3564static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3565                                unsigned int timeout,int probe_fl,
3566                                void *write_data,unsigned int write_len,
3567                                void *read_data,unsigned int read_len)
3568{
3569        unsigned int idx;
3570        int status = 0;
3571        struct hdw_timer timer = {
3572                .hdw = hdw,
3573        };
3574
3575        if (!hdw->ctl_lock_held) {
3576                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3577                           "Attempted to execute control transfer without lock!!");
3578                return -EDEADLK;
3579        }
3580        if (!hdw->flag_ok && !probe_fl) {
3581                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3582                           "Attempted to execute control transfer when device not ok");
3583                return -EIO;
3584        }
3585        if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3586                if (!probe_fl) {
3587                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3588                                   "Attempted to execute control transfer when USB is disconnected");
3589                }
3590                return -ENOTTY;
3591        }
3592
3593        /* Ensure that we have sane parameters */
3594        if (!write_data) write_len = 0;
3595        if (!read_data) read_len = 0;
3596        if (write_len > PVR2_CTL_BUFFSIZE) {
3597                pvr2_trace(
3598                        PVR2_TRACE_ERROR_LEGS,
3599                        "Attempted to execute %d byte control-write transfer (limit=%d)",
3600                        write_len,PVR2_CTL_BUFFSIZE);
3601                return -EINVAL;
3602        }
3603        if (read_len > PVR2_CTL_BUFFSIZE) {
3604                pvr2_trace(
3605                        PVR2_TRACE_ERROR_LEGS,
3606                        "Attempted to execute %d byte control-read transfer (limit=%d)",
3607                        write_len,PVR2_CTL_BUFFSIZE);
3608                return -EINVAL;
3609        }
3610        if ((!write_len) && (!read_len)) {
3611                pvr2_trace(
3612                        PVR2_TRACE_ERROR_LEGS,
3613                        "Attempted to execute null control transfer?");
3614                return -EINVAL;
3615        }
3616
3617
3618        hdw->cmd_debug_state = 1;
3619        if (write_len && write_data)
3620                hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3621        else
3622                hdw->cmd_debug_code = 0;
3623        hdw->cmd_debug_write_len = write_len;
3624        hdw->cmd_debug_read_len = read_len;
3625
3626        /* Initialize common stuff */
3627        init_completion(&hdw->ctl_done);
3628        hdw->ctl_timeout_flag = 0;
3629        hdw->ctl_write_pend_flag = 0;
3630        hdw->ctl_read_pend_flag = 0;
3631        timer_setup_on_stack(&timer.timer, pvr2_ctl_timeout, 0);
3632        timer.timer.expires = jiffies + timeout;
3633
3634        if (write_len && write_data) {
3635                hdw->cmd_debug_state = 2;
3636                /* Transfer write data to internal buffer */
3637                for (idx = 0; idx < write_len; idx++) {
3638                        hdw->ctl_write_buffer[idx] =
3639                                ((unsigned char *)write_data)[idx];
3640                }
3641                /* Initiate a write request */
3642                usb_fill_bulk_urb(hdw->ctl_write_urb,
3643                                  hdw->usb_dev,
3644                                  usb_sndbulkpipe(hdw->usb_dev,
3645                                                  PVR2_CTL_WRITE_ENDPOINT),
3646                                  hdw->ctl_write_buffer,
3647                                  write_len,
3648                                  pvr2_ctl_write_complete,
3649                                  hdw);
3650                hdw->ctl_write_urb->actual_length = 0;
3651                hdw->ctl_write_pend_flag = !0;
3652                if (usb_urb_ep_type_check(hdw->ctl_write_urb)) {
3653                        pvr2_trace(
3654                                PVR2_TRACE_ERROR_LEGS,
3655                                "Invalid write control endpoint");
3656                        return -EINVAL;
3657                }
3658                status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3659                if (status < 0) {
3660                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3661                                   "Failed to submit write-control URB status=%d",
3662status);
3663                        hdw->ctl_write_pend_flag = 0;
3664                        goto done;
3665                }
3666        }
3667
3668        if (read_len) {
3669                hdw->cmd_debug_state = 3;
3670                memset(hdw->ctl_read_buffer,0x43,read_len);
3671                /* Initiate a read request */
3672                usb_fill_bulk_urb(hdw->ctl_read_urb,
3673                                  hdw->usb_dev,
3674                                  usb_rcvbulkpipe(hdw->usb_dev,
3675                                                  PVR2_CTL_READ_ENDPOINT),
3676                                  hdw->ctl_read_buffer,
3677                                  read_len,
3678                                  pvr2_ctl_read_complete,
3679                                  hdw);
3680                hdw->ctl_read_urb->actual_length = 0;
3681                hdw->ctl_read_pend_flag = !0;
3682                if (usb_urb_ep_type_check(hdw->ctl_read_urb)) {
3683                        pvr2_trace(
3684                                PVR2_TRACE_ERROR_LEGS,
3685                                "Invalid read control endpoint");
3686                        return -EINVAL;
3687                }
3688                status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3689                if (status < 0) {
3690                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3691                                   "Failed to submit read-control URB status=%d",
3692status);
3693                        hdw->ctl_read_pend_flag = 0;
3694                        goto done;
3695                }
3696        }
3697
3698        /* Start timer */
3699        add_timer(&timer.timer);
3700
3701        /* Now wait for all I/O to complete */
3702        hdw->cmd_debug_state = 4;
3703        while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3704                wait_for_completion(&hdw->ctl_done);
3705        }
3706        hdw->cmd_debug_state = 5;
3707
3708        /* Stop timer */
3709        del_timer_sync(&timer.timer);
3710
3711        hdw->cmd_debug_state = 6;
3712        status = 0;
3713
3714        if (hdw->ctl_timeout_flag) {
3715                status = -ETIMEDOUT;
3716                if (!probe_fl) {
3717                        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3718                                   "Timed out control-write");
3719                }
3720                goto done;
3721        }
3722
3723        if (write_len) {
3724                /* Validate results of write request */
3725                if ((hdw->ctl_write_urb->status != 0) &&
3726                    (hdw->ctl_write_urb->status != -ENOENT) &&
3727                    (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3728                    (hdw->ctl_write_urb->status != -ECONNRESET)) {
3729                        /* USB subsystem is reporting some kind of failure
3730                           on the write */
3731                        status = hdw->ctl_write_urb->status;
3732                        if (!probe_fl) {
3733                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3734                                           "control-write URB failure, status=%d",
3735                                           status);
3736                        }
3737                        goto done;
3738                }
3739                if (hdw->ctl_write_urb->actual_length < write_len) {
3740                        /* Failed to write enough data */
3741                        status = -EIO;
3742                        if (!probe_fl) {
3743                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3744                                           "control-write URB short, expected=%d got=%d",
3745                                           write_len,
3746                                           hdw->ctl_write_urb->actual_length);
3747                        }
3748                        goto done;
3749                }
3750        }
3751        if (read_len && read_data) {
3752                /* Validate results of read request */
3753                if ((hdw->ctl_read_urb->status != 0) &&
3754                    (hdw->ctl_read_urb->status != -ENOENT) &&
3755                    (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3756                    (hdw->ctl_read_urb->status != -ECONNRESET)) {
3757                        /* USB subsystem is reporting some kind of failure
3758                           on the read */
3759                        status = hdw->ctl_read_urb->status;
3760                        if (!probe_fl) {
3761                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3762                                           "control-read URB failure, status=%d",
3763                                           status);
3764                        }
3765                        goto done;
3766                }
3767                if (hdw->ctl_read_urb->actual_length < read_len) {
3768                        /* Failed to read enough data */
3769                        status = -EIO;
3770                        if (!probe_fl) {
3771                                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3772                                           "control-read URB short, expected=%d got=%d",
3773                                           read_len,
3774                                           hdw->ctl_read_urb->actual_length);
3775                        }
3776                        goto done;
3777                }
3778                /* Transfer retrieved data out from internal buffer */
3779                for (idx = 0; idx < read_len; idx++) {
3780                        ((unsigned char *)read_data)[idx] =
3781                                hdw->ctl_read_buffer[idx];
3782                }
3783        }
3784
3785 done:
3786
3787        hdw->cmd_debug_state = 0;
3788        if ((status < 0) && (!probe_fl)) {
3789                pvr2_hdw_render_useless(hdw);
3790        }
3791        destroy_timer_on_stack(&timer.timer);
3792
3793        return status;
3794}
3795
3796
3797int pvr2_send_request(struct pvr2_hdw *hdw,
3798                      void *write_data,unsigned int write_len,
3799                      void *read_data,unsigned int read_len)
3800{
3801        return pvr2_send_request_ex(hdw,HZ*4,0,
3802                                    write_data,write_len,
3803                                    read_data,read_len);
3804}
3805
3806
3807static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3808{
3809        int ret;
3810        unsigned int cnt = 1;
3811        unsigned int args = 0;
3812        LOCK_TAKE(hdw->ctl_lock);
3813        hdw->cmd_buffer[0] = cmdcode & 0xffu;
3814        args = (cmdcode >> 8) & 0xffu;
3815        args = (args > 2) ? 2 : args;
3816        if (args) {
3817                cnt += args;
3818                hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3819                if (args > 1) {
3820                        hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3821                }
3822        }
3823        if (pvrusb2_debug & PVR2_TRACE_INIT) {
3824                unsigned int idx;
3825                unsigned int ccnt,bcnt;
3826                char tbuf[50];
3827                cmdcode &= 0xffu;
3828                bcnt = 0;
3829                ccnt = scnprintf(tbuf+bcnt,
3830                                 sizeof(tbuf)-bcnt,
3831                                 "Sending FX2 command 0x%x",cmdcode);
3832                bcnt += ccnt;
3833                for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
3834                        if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
3835                                ccnt = scnprintf(tbuf+bcnt,
3836                                                 sizeof(tbuf)-bcnt,
3837                                                 " \"%s\"",
3838                                                 pvr2_fx2cmd_desc[idx].desc);
3839                                bcnt += ccnt;
3840                                break;
3841                        }
3842                }
3843                if (args) {
3844                        ccnt = scnprintf(tbuf+bcnt,
3845                                         sizeof(tbuf)-bcnt,
3846                                         " (%u",hdw->cmd_buffer[1]);
3847                        bcnt += ccnt;
3848                        if (args > 1) {
3849                                ccnt = scnprintf(tbuf+bcnt,
3850                                                 sizeof(tbuf)-bcnt,
3851                                                 ",%u",hdw->cmd_buffer[2]);
3852                                bcnt += ccnt;
3853                        }
3854                        ccnt = scnprintf(tbuf+bcnt,
3855                                         sizeof(tbuf)-bcnt,
3856                                         ")");
3857                        bcnt += ccnt;
3858                }
3859                pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
3860        }
3861        ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
3862        LOCK_GIVE(hdw->ctl_lock);
3863        return ret;
3864}
3865
3866
3867int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3868{
3869        int ret;
3870
3871        LOCK_TAKE(hdw->ctl_lock);
3872
3873        hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
3874        PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3875        hdw->cmd_buffer[5] = 0;
3876        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3877        hdw->cmd_buffer[7] = reg & 0xff;
3878
3879
3880        ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3881
3882        LOCK_GIVE(hdw->ctl_lock);
3883
3884        return ret;
3885}
3886
3887
3888static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3889{
3890        int ret = 0;
3891
3892        LOCK_TAKE(hdw->ctl_lock);
3893
3894        hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
3895        hdw->cmd_buffer[1] = 0;
3896        hdw->cmd_buffer[2] = 0;
3897        hdw->cmd_buffer[3] = 0;
3898        hdw->cmd_buffer[4] = 0;
3899        hdw->cmd_buffer[5] = 0;
3900        hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3901        hdw->cmd_buffer[7] = reg & 0xff;
3902
3903        ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3904        *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3905
3906        LOCK_GIVE(hdw->ctl_lock);
3907
3908        return ret;
3909}
3910
3911
3912void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3913{
3914        if (!hdw->flag_ok) return;
3915        pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3916                   "Device being rendered inoperable");
3917        if (hdw->vid_stream) {
3918                pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3919        }
3920        hdw->flag_ok = 0;
3921        trace_stbit("flag_ok",hdw->flag_ok);
3922        pvr2_hdw_state_sched(hdw);
3923}
3924
3925
3926void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3927{
3928        int ret;
3929        pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3930        ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3931        if (ret == 0) {
3932                ret = usb_reset_device(hdw->usb_dev);
3933                usb_unlock_device(hdw->usb_dev);
3934        } else {
3935                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3936                           "Failed to lock USB device ret=%d",ret);
3937        }
3938        if (init_pause_msec) {
3939                pvr2_trace(PVR2_TRACE_INFO,
3940                           "Waiting %u msec for hardware to settle",
3941                           init_pause_msec);
3942                msleep(init_pause_msec);
3943        }
3944
3945}
3946
3947
3948void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3949{
3950        char *da;
3951        unsigned int pipe;
3952        int ret;
3953
3954        if (!hdw->usb_dev) return;
3955
3956        da = kmalloc(16, GFP_KERNEL);
3957
3958        if (da == NULL) {
3959                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3960                           "Unable to allocate memory to control CPU reset");
3961                return;
3962        }
3963
3964        pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3965
3966        da[0] = val ? 0x01 : 0x00;
3967
3968        /* Write the CPUCS register on the 8051.  The lsb of the register
3969           is the reset bit; a 1 asserts reset while a 0 clears it. */
3970        pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3971        ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3972        if (ret < 0) {
3973                pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3974                           "cpureset_assert(%d) error=%d",val,ret);
3975                pvr2_hdw_render_useless(hdw);
3976        }
3977
3978        kfree(da);
3979}
3980
3981
3982int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3983{
3984        return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
3985}
3986
3987
3988int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3989{
3990        return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
3991}
3992
3993
3994
3995int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3996{
3997        pvr2_trace(PVR2_TRACE_INIT,
3998                   "Requesting decoder reset");
3999        if (hdw->decoder_client_id) {
4000                v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4001                                     core, reset, 0);
4002                pvr2_hdw_cx25840_vbi_hack(hdw);
4003                return 0;
4004        }
4005        pvr2_trace(PVR2_TRACE_INIT,
4006                   "Unable to reset decoder: nothing attached");
4007        return -ENOTTY;
4008}
4009
4010
4011static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4012{
4013        hdw->flag_ok = !0;
4014        return pvr2_issue_simple_cmd(hdw,
4015                                     FX2CMD_HCW_DEMOD_RESETIN |
4016                                     (1 << 8) |
4017                                     ((onoff ? 1 : 0) << 16));
4018}
4019
4020
4021static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4022{
4023        hdw->flag_ok = !0;
4024        return pvr2_issue_simple_cmd(hdw,(onoff ?
4025                                          FX2CMD_ONAIR_DTV_POWER_ON :
4026                                          FX2CMD_ONAIR_DTV_POWER_OFF));
4027}
4028
4029
4030static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4031                                                int onoff)
4032{
4033        return pvr2_issue_simple_cmd(hdw,(onoff ?
4034                                          FX2CMD_ONAIR_DTV_STREAMING_ON :
4035                                          FX2CMD_ONAIR_DTV_STREAMING_OFF));
4036}
4037
4038
4039static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4040{
4041        int cmode;
4042        /* Compare digital/analog desired setting with current setting.  If
4043           they don't match, fix it... */
4044        cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4045        if (cmode == hdw->pathway_state) {
4046                /* They match; nothing to do */
4047                return;
4048        }
4049
4050        switch (hdw->hdw_desc->digital_control_scheme) {
4051        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4052                pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4053                if (cmode == PVR2_PATHWAY_ANALOG) {
4054                        /* If moving to analog mode, also force the decoder
4055                           to reset.  If no decoder is attached, then it's
4056                           ok to ignore this because if/when the decoder
4057                           attaches, it will reset itself at that time. */
4058                        pvr2_hdw_cmd_decoder_reset(hdw);
4059                }
4060                break;
4061        case PVR2_DIGITAL_SCHEME_ONAIR:
4062                /* Supposedly we should always have the power on whether in
4063                   digital or analog mode.  But for now do what appears to
4064                   work... */
4065                pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4066                break;
4067        default: break;
4068        }
4069
4070        pvr2_hdw_untrip_unlocked(hdw);
4071        hdw->pathway_state = cmode;
4072}
4073
4074
4075static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4076{
4077        /* change some GPIO data
4078         *
4079         * note: bit d7 of dir appears to control the LED,
4080         * so we shut it off here.
4081         *
4082         */
4083        if (onoff) {
4084                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4085        } else {
4086                pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4087        }
4088        pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4089}
4090
4091
4092typedef void (*led_method_func)(struct pvr2_hdw *,int);
4093
4094static led_method_func led_methods[] = {
4095        [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4096};
4097
4098
4099/* Toggle LED */
4100static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4101{
4102        unsigned int scheme_id;
4103        led_method_func fp;
4104
4105        if ((!onoff) == (!hdw->led_on)) return;
4106
4107        hdw->led_on = onoff != 0;
4108
4109        scheme_id = hdw->hdw_desc->led_scheme;
4110        if (scheme_id < ARRAY_SIZE(led_methods)) {
4111                fp = led_methods[scheme_id];
4112        } else {
4113                fp = NULL;
4114        }
4115
4116        if (fp) (*fp)(hdw,onoff);
4117}
4118
4119
4120/* Stop / start video stream transport */
4121static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4122{
4123        int ret;
4124
4125        /* If we're in analog mode, then just issue the usual analog
4126           command. */
4127        if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4128                return pvr2_issue_simple_cmd(hdw,
4129                                             (runFl ?
4130                                              FX2CMD_STREAMING_ON :
4131                                              FX2CMD_STREAMING_OFF));
4132                /*Note: Not reached */
4133        }
4134
4135        if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4136                /* Whoops, we don't know what mode we're in... */
4137                return -EINVAL;
4138        }
4139
4140        /* To get here we have to be in digital mode.  The mechanism here
4141           is unfortunately different for different vendors.  So we switch
4142           on the device's digital scheme attribute in order to figure out
4143           what to do. */
4144        switch (hdw->hdw_desc->digital_control_scheme) {
4145        case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4146                return pvr2_issue_simple_cmd(hdw,
4147                                             (runFl ?
4148                                              FX2CMD_HCW_DTV_STREAMING_ON :
4149                                              FX2CMD_HCW_DTV_STREAMING_OFF));
4150        case PVR2_DIGITAL_SCHEME_ONAIR:
4151                ret = pvr2_issue_simple_cmd(hdw,
4152                                            (runFl ?
4153                                             FX2CMD_STREAMING_ON :
4154                                             FX2CMD_STREAMING_OFF));
4155                if (ret) return ret;
4156                return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4157        default:
4158                return -EINVAL;
4159        }
4160}
4161
4162
4163/* Evaluate whether or not state_pathway_ok can change */
4164static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4165{
4166        if (hdw->state_pathway_ok) {
4167                /* Nothing to do if pathway is already ok */
4168                return 0;
4169        }
4170        if (!hdw->state_pipeline_idle) {
4171                /* Not allowed to change anything if pipeline is not idle */
4172                return 0;
4173        }
4174        pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4175        hdw->state_pathway_ok = !0;
4176        trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4177        return !0;
4178}
4179
4180
4181/* Evaluate whether or not state_encoder_ok can change */
4182static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4183{
4184        if (hdw->state_encoder_ok) return 0;
4185        if (hdw->flag_tripped) return 0;
4186        if (hdw->state_encoder_run) return 0;
4187        if (hdw->state_encoder_config) return 0;
4188        if (hdw->state_decoder_run) return 0;
4189        if (hdw->state_usbstream_run) return 0;
4190        if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4191                if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4192        } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4193                return 0;
4194        }
4195
4196        if (pvr2_upload_firmware2(hdw) < 0) {
4197                hdw->flag_tripped = !0;
4198                trace_stbit("flag_tripped",hdw->flag_tripped);
4199                return !0;
4200        }
4201        hdw->state_encoder_ok = !0;
4202        trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4203        return !0;
4204}
4205
4206
4207/* Evaluate whether or not state_encoder_config can change */
4208static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4209{
4210        if (hdw->state_encoder_config) {
4211                if (hdw->state_encoder_ok) {
4212                        if (hdw->state_pipeline_req &&
4213                            !hdw->state_pipeline_pause) return 0;
4214                }
4215                hdw->state_encoder_config = 0;
4216                hdw->state_encoder_waitok = 0;
4217                trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4218                /* paranoia - solve race if timer just completed */
4219                del_timer_sync(&hdw->encoder_wait_timer);
4220        } else {
4221                if (!hdw->state_pathway_ok ||
4222                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4223                    !hdw->state_encoder_ok ||
4224                    !hdw->state_pipeline_idle ||
4225                    hdw->state_pipeline_pause ||
4226                    !hdw->state_pipeline_req ||
4227                    !hdw->state_pipeline_config) {
4228                        /* We must reset the enforced wait interval if
4229                           anything has happened that might have disturbed
4230                           the encoder.  This should be a rare case. */
4231                        if (timer_pending(&hdw->encoder_wait_timer)) {
4232                                del_timer_sync(&hdw->encoder_wait_timer);
4233                        }
4234                        if (hdw->state_encoder_waitok) {
4235                                /* Must clear the state - therefore we did
4236                                   something to a state bit and must also
4237                                   return true. */
4238                                hdw->state_encoder_waitok = 0;
4239                                trace_stbit("state_encoder_waitok",
4240                                            hdw->state_encoder_waitok);
4241                                return !0;
4242                        }
4243                        return 0;
4244                }
4245                if (!hdw->state_encoder_waitok) {
4246                        if (!timer_pending(&hdw->encoder_wait_timer)) {
4247                                /* waitok flag wasn't set and timer isn't
4248                                   running.  Check flag once more to avoid
4249                                   a race then start the timer.  This is
4250                                   the point when we measure out a minimal
4251                                   quiet interval before doing something to
4252                                   the encoder. */
4253                                if (!hdw->state_encoder_waitok) {
4254                                        hdw->encoder_wait_timer.expires =
4255                                                jiffies + msecs_to_jiffies(
4256                                                TIME_MSEC_ENCODER_WAIT);
4257                                        add_timer(&hdw->encoder_wait_timer);
4258                                }
4259                        }
4260                        /* We can't continue until we know we have been
4261                           quiet for the interval measured by this
4262                           timer. */
4263                        return 0;
4264                }
4265                pvr2_encoder_configure(hdw);
4266                if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4267        }
4268        trace_stbit("state_encoder_config",hdw->state_encoder_config);
4269        return !0;
4270}
4271
4272
4273/* Return true if the encoder should not be running. */
4274static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4275{
4276        if (!hdw->state_encoder_ok) {
4277                /* Encoder isn't healthy at the moment, so stop it. */
4278                return !0;
4279        }
4280        if (!hdw->state_pathway_ok) {
4281                /* Mode is not understood at the moment (i.e. it wants to
4282                   change), so encoder must be stopped. */
4283                return !0;
4284        }
4285
4286        switch (hdw->pathway_state) {
4287        case PVR2_PATHWAY_ANALOG:
4288                if (!hdw->state_decoder_run) {
4289                        /* We're in analog mode and the decoder is not
4290                           running; thus the encoder should be stopped as
4291                           well. */
4292                        return !0;
4293                }
4294                break;
4295        case PVR2_PATHWAY_DIGITAL:
4296                if (hdw->state_encoder_runok) {
4297                        /* This is a funny case.  We're in digital mode so
4298                           really the encoder should be stopped.  However
4299                           if it really is running, only kill it after
4300                           runok has been set.  This gives a chance for the
4301                           onair quirk to function (encoder must run
4302                           briefly first, at least once, before onair
4303                           digital streaming can work). */
4304                        return !0;
4305                }
4306                break;
4307        default:
4308                /* Unknown mode; so encoder should be stopped. */
4309                return !0;
4310        }
4311
4312        /* If we get here, we haven't found a reason to stop the
4313           encoder. */
4314        return 0;
4315}
4316
4317
4318/* Return true if the encoder should be running. */
4319static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4320{
4321        if (!hdw->state_encoder_ok) {
4322                /* Don't run the encoder if it isn't healthy... */
4323                return 0;
4324        }
4325        if (!hdw->state_pathway_ok) {
4326                /* Don't run the encoder if we don't (yet) know what mode
4327                   we need to be in... */
4328                return 0;
4329        }
4330
4331        switch (hdw->pathway_state) {
4332        case PVR2_PATHWAY_ANALOG:
4333                if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4334                        /* In analog mode, if the decoder is running, then
4335                           run the encoder. */
4336                        return !0;
4337                }
4338                break;
4339        case PVR2_PATHWAY_DIGITAL:
4340                if ((hdw->hdw_desc->digital_control_scheme ==
4341                     PVR2_DIGITAL_SCHEME_ONAIR) &&
4342                    !hdw->state_encoder_runok) {
4343                        /* This is a quirk.  OnAir hardware won't stream
4344                           digital until the encoder has been run at least
4345                           once, for a minimal period of time (empiricially
4346                           measured to be 1/4 second).  So if we're on
4347                           OnAir hardware and the encoder has never been
4348                           run at all, then start the encoder.  Normal
4349                           state machine logic in the driver will
4350                           automatically handle the remaining bits. */
4351                        return !0;
4352                }
4353                break;
4354        default:
4355                /* For completeness (unknown mode; encoder won't run ever) */
4356                break;
4357        }
4358        /* If we get here, then we haven't found any reason to run the
4359           encoder, so don't run it. */
4360        return 0;
4361}
4362
4363
4364/* Evaluate whether or not state_encoder_run can change */
4365static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4366{
4367        if (hdw->state_encoder_run) {
4368                if (!state_check_disable_encoder_run(hdw)) return 0;
4369                if (hdw->state_encoder_ok) {
4370                        del_timer_sync(&hdw->encoder_run_timer);
4371                        if (pvr2_encoder_stop(hdw) < 0) return !0;
4372                }
4373                hdw->state_encoder_run = 0;
4374        } else {
4375                if (!state_check_enable_encoder_run(hdw)) return 0;
4376                if (pvr2_encoder_start(hdw) < 0) return !0;
4377                hdw->state_encoder_run = !0;
4378                if (!hdw->state_encoder_runok) {
4379                        hdw->encoder_run_timer.expires = jiffies +
4380                                 msecs_to_jiffies(TIME_MSEC_ENCODER_OK);
4381                        add_timer(&hdw->encoder_run_timer);
4382                }
4383        }
4384        trace_stbit("state_encoder_run",hdw->state_encoder_run);
4385        return !0;
4386}
4387
4388
4389/* Timeout function for quiescent timer. */
4390static void pvr2_hdw_quiescent_timeout(struct timer_list *t)
4391{
4392        struct pvr2_hdw *hdw = from_timer(hdw, t, quiescent_timer);
4393        hdw->state_decoder_quiescent = !0;
4394        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4395        hdw->state_stale = !0;
4396        schedule_work(&hdw->workpoll);
4397}
4398
4399
4400/* Timeout function for decoder stabilization timer. */
4401static void pvr2_hdw_decoder_stabilization_timeout(struct timer_list *t)
4402{
4403        struct pvr2_hdw *hdw = from_timer(hdw, t, decoder_stabilization_timer);
4404        hdw->state_decoder_ready = !0;
4405        trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4406        hdw->state_stale = !0;
4407        schedule_work(&hdw->workpoll);
4408}
4409
4410
4411/* Timeout function for encoder wait timer. */
4412static void pvr2_hdw_encoder_wait_timeout(struct timer_list *t)
4413{
4414        struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_wait_timer);
4415        hdw->state_encoder_waitok = !0;
4416        trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4417        hdw->state_stale = !0;
4418        schedule_work(&hdw->workpoll);
4419}
4420
4421
4422/* Timeout function for encoder run timer. */
4423static void pvr2_hdw_encoder_run_timeout(struct timer_list *t)
4424{
4425        struct pvr2_hdw *hdw = from_timer(hdw, t, encoder_run_timer);
4426        if (!hdw->state_encoder_runok) {
4427                hdw->state_encoder_runok = !0;
4428                trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4429                hdw->state_stale = !0;
4430                schedule_work(&hdw->workpoll);
4431        }
4432}
4433
4434
4435/* Evaluate whether or not state_decoder_run can change */
4436static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4437{
4438        if (hdw->state_decoder_run) {
4439                if (hdw->state_encoder_ok) {
4440                        if (hdw->state_pipeline_req &&
4441                            !hdw->state_pipeline_pause &&
4442                            hdw->state_pathway_ok) return 0;
4443                }
4444                if (!hdw->flag_decoder_missed) {
4445                        pvr2_decoder_enable(hdw,0);
4446                }
4447                hdw->state_decoder_quiescent = 0;
4448                hdw->state_decoder_run = 0;
4449                /* paranoia - solve race if timer(s) just completed */
4450                del_timer_sync(&hdw->quiescent_timer);
4451                /* Kill the stabilization timer, in case we're killing the
4452                   encoder before the previous stabilization interval has
4453                   been properly timed. */
4454                del_timer_sync(&hdw->decoder_stabilization_timer);
4455                hdw->state_decoder_ready = 0;
4456        } else {
4457                if (!hdw->state_decoder_quiescent) {
4458                        if (!timer_pending(&hdw->quiescent_timer)) {
4459                                /* We don't do something about the
4460                                   quiescent timer until right here because
4461                                   we also want to catch cases where the
4462                                   decoder was already not running (like
4463                                   after initialization) as opposed to
4464                                   knowing that we had just stopped it.
4465                                   The second flag check is here to cover a
4466                                   race - the timer could have run and set
4467                                   this flag just after the previous check
4468                                   but before we did the pending check. */
4469                                if (!hdw->state_decoder_quiescent) {
4470                                        hdw->quiescent_timer.expires =
4471                                                jiffies + msecs_to_jiffies(
4472                                                TIME_MSEC_DECODER_WAIT);
4473                                        add_timer(&hdw->quiescent_timer);
4474                                }
4475                        }
4476                        /* Don't allow decoder to start again until it has
4477                           been quiesced first.  This little detail should
4478                           hopefully further stabilize the encoder. */
4479                        return 0;
4480                }
4481                if (!hdw->state_pathway_ok ||
4482                    (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4483                    !hdw->state_pipeline_req ||
4484                    hdw->state_pipeline_pause ||
4485                    !hdw->state_pipeline_config ||
4486                    !hdw->state_encoder_config ||
4487                    !hdw->state_encoder_ok) return 0;
4488                del_timer_sync(&hdw->quiescent_timer);
4489                if (hdw->flag_decoder_missed) return 0;
4490                if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4491                hdw->state_decoder_quiescent = 0;
4492                hdw->state_decoder_ready = 0;
4493                hdw->state_decoder_run = !0;
4494                if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4495                        hdw->decoder_stabilization_timer.expires =
4496                                jiffies + msecs_to_jiffies(
4497                                TIME_MSEC_DECODER_STABILIZATION_WAIT);
4498                        add_timer(&hdw->decoder_stabilization_timer);
4499                } else {
4500                        hdw->state_decoder_ready = !0;
4501                }
4502        }
4503        trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4504        trace_stbit("state_decoder_run",hdw->state_decoder_run);
4505        trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4506        return !0;
4507}
4508
4509
4510/* Evaluate whether or not state_usbstream_run can change */
4511static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4512{
4513        if (hdw->state_usbstream_run) {
4514                int fl = !0;
4515                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4516                        fl = (hdw->state_encoder_ok &&
4517                              hdw->state_encoder_run);
4518                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4519                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4520                        fl = hdw->state_encoder_ok;
4521                }
4522                if (fl &&
4523                    hdw->state_pipeline_req &&
4524                    !hdw->state_pipeline_pause &&
4525                    hdw->state_pathway_ok) {
4526                        return 0;
4527                }
4528                pvr2_hdw_cmd_usbstream(hdw,0);
4529                hdw->state_usbstream_run = 0;
4530        } else {
4531                if (!hdw->state_pipeline_req ||
4532                    hdw->state_pipeline_pause ||
4533                    !hdw->state_pathway_ok) return 0;
4534                if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4535                        if (!hdw->state_encoder_ok ||
4536                            !hdw->state_encoder_run) return 0;
4537                } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4538                           (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4539                        if (!hdw->state_encoder_ok) return 0;
4540                        if (hdw->state_encoder_run) return 0;
4541                        if (hdw->hdw_desc->digital_control_scheme ==
4542                            PVR2_DIGITAL_SCHEME_ONAIR) {
4543                                /* OnAir digital receivers won't stream
4544                                   unless the analog encoder has run first.
4545                                   Why?  I have no idea.  But don't even
4546                                   try until we know the analog side is
4547                                   known to have run. */
4548                                if (!hdw->state_encoder_runok) return 0;
4549                        }
4550                }
4551                if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4552                hdw->state_usbstream_run = !0;
4553        }
4554        trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4555        return !0;
4556}
4557
4558
4559/* Attempt to configure pipeline, if needed */
4560static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4561{
4562        if (hdw->state_pipeline_config ||
4563            hdw->state_pipeline_pause) return 0;
4564        pvr2_hdw_commit_execute(hdw);
4565        return !0;
4566}
4567
4568
4569/* Update pipeline idle and pipeline pause tracking states based on other
4570   inputs.  This must be called whenever the other relevant inputs have
4571   changed. */
4572static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4573{
4574        unsigned int st;
4575        int updatedFl = 0;
4576        /* Update pipeline state */
4577        st = !(hdw->state_encoder_run ||
4578               hdw->state_decoder_run ||
4579               hdw->state_usbstream_run ||
4580               (!hdw->state_decoder_quiescent));
4581        if (!st != !hdw->state_pipeline_idle) {
4582                hdw->state_pipeline_idle = st;
4583                updatedFl = !0;
4584        }
4585        if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4586                hdw->state_pipeline_pause = 0;
4587                updatedFl = !0;
4588        }
4589        return updatedFl;
4590}
4591
4592
4593typedef int (*state_eval_func)(struct pvr2_hdw *);
4594
4595/* Set of functions to be run to evaluate various states in the driver. */
4596static const state_eval_func eval_funcs[] = {
4597        state_eval_pathway_ok,
4598        state_eval_pipeline_config,
4599        state_eval_encoder_ok,
4600        state_eval_encoder_config,
4601        state_eval_decoder_run,
4602        state_eval_encoder_run,
4603        state_eval_usbstream_run,
4604};
4605
4606
4607/* Process various states and return true if we did anything interesting. */
4608static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4609{
4610        unsigned int i;
4611        int state_updated = 0;
4612        int check_flag;
4613
4614        if (!hdw->state_stale) return 0;
4615        if ((hdw->fw1_state != FW1_STATE_OK) ||
4616            !hdw->flag_ok) {
4617                hdw->state_stale = 0;
4618                return !0;
4619        }
4620        /* This loop is the heart of the entire driver.  It keeps trying to
4621           evaluate various bits of driver state until nothing changes for
4622           one full iteration.  Each "bit of state" tracks some global
4623           aspect of the driver, e.g. whether decoder should run, if
4624           pipeline is configured, usb streaming is on, etc.  We separately
4625           evaluate each of those questions based on other driver state to
4626           arrive at the correct running configuration. */
4627        do {
4628                check_flag = 0;
4629                state_update_pipeline_state(hdw);
4630                /* Iterate over each bit of state */
4631                for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4632                        if ((*eval_funcs[i])(hdw)) {
4633                                check_flag = !0;
4634                                state_updated = !0;
4635                                state_update_pipeline_state(hdw);
4636                        }
4637                }
4638        } while (check_flag && hdw->flag_ok);
4639        hdw->state_stale = 0;
4640        trace_stbit("state_stale",hdw->state_stale);
4641        return state_updated;
4642}
4643
4644
4645static unsigned int print_input_mask(unsigned int msk,
4646                                     char *buf,unsigned int acnt)
4647{
4648        unsigned int idx,ccnt;
4649        unsigned int tcnt = 0;
4650        for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4651                if (!((1 << idx) & msk)) continue;
4652                ccnt = scnprintf(buf+tcnt,
4653                                 acnt-tcnt,
4654                                 "%s%s",
4655                                 (tcnt ? ", " : ""),
4656                                 control_values_input[idx]);
4657                tcnt += ccnt;
4658        }
4659        return tcnt;
4660}
4661
4662
4663static const char *pvr2_pathway_state_name(int id)
4664{
4665        switch (id) {
4666        case PVR2_PATHWAY_ANALOG: return "analog";
4667        case PVR2_PATHWAY_DIGITAL: return "digital";
4668        default: return "unknown";
4669        }
4670}
4671
4672
4673static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4674                                             char *buf,unsigned int acnt)
4675{
4676        switch (which) {
4677        case 0:
4678                return scnprintf(
4679                        buf,acnt,
4680                        "driver:%s%s%s%s%s <mode=%s>",
4681                        (hdw->flag_ok ? " <ok>" : " <fail>"),
4682                        (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4683                        (hdw->flag_disconnected ? " <disconnected>" :
4684                         " <connected>"),
4685                        (hdw->flag_tripped ? " <tripped>" : ""),
4686                        (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4687                        pvr2_pathway_state_name(hdw->pathway_state));
4688
4689        case 1:
4690                return scnprintf(
4691                        buf,acnt,
4692                        "pipeline:%s%s%s%s",
4693                        (hdw->state_pipeline_idle ? " <idle>" : ""),
4694                        (hdw->state_pipeline_config ?
4695                         " <configok>" : " <stale>"),
4696                        (hdw->state_pipeline_req ? " <req>" : ""),
4697                        (hdw->state_pipeline_pause ? " <pause>" : ""));
4698        case 2:
4699                return scnprintf(
4700                        buf,acnt,
4701                        "worker:%s%s%s%s%s%s%s",
4702                        (hdw->state_decoder_run ?
4703                         (hdw->state_decoder_ready ?
4704                          "<decode:run>" : " <decode:start>") :
4705                         (hdw->state_decoder_quiescent ?
4706                          "" : " <decode:stop>")),
4707                        (hdw->state_decoder_quiescent ?
4708                         " <decode:quiescent>" : ""),
4709                        (hdw->state_encoder_ok ?
4710                         "" : " <encode:init>"),
4711                        (hdw->state_encoder_run ?
4712                         (hdw->state_encoder_runok ?
4713                          " <encode:run>" :
4714                          " <encode:firstrun>") :
4715                         (hdw->state_encoder_runok ?
4716                          " <encode:stop>" :
4717                          " <encode:virgin>")),
4718                        (hdw->state_encoder_config ?
4719                         " <encode:configok>" :
4720                         (hdw->state_encoder_waitok ?
4721                          "" : " <encode:waitok>")),
4722                        (hdw->state_usbstream_run ?
4723                         " <usb:run>" : " <usb:stop>"),
4724                        (hdw->state_pathway_ok ?
4725                         " <pathway:ok>" : ""));
4726        case 3:
4727                return scnprintf(
4728                        buf,acnt,
4729                        "state: %s",
4730                        pvr2_get_state_name(hdw->master_state));
4731        case 4: {
4732                unsigned int tcnt = 0;
4733                unsigned int ccnt;
4734
4735                ccnt = scnprintf(buf,
4736                                 acnt,
4737                                 "Hardware supported inputs: ");
4738                tcnt += ccnt;
4739                tcnt += print_input_mask(hdw->input_avail_mask,
4740                                         buf+tcnt,
4741                                         acnt-tcnt);
4742                if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4743                        ccnt = scnprintf(buf+tcnt,
4744                                         acnt-tcnt,
4745                                         "; allowed inputs: ");
4746                        tcnt += ccnt;
4747                        tcnt += print_input_mask(hdw->input_allowed_mask,
4748                                                 buf+tcnt,
4749                                                 acnt-tcnt);
4750                }
4751                return tcnt;
4752        }
4753        case 5: {
4754                struct pvr2_stream_stats stats;
4755                if (!hdw->vid_stream) break;
4756                pvr2_stream_get_stats(hdw->vid_stream,
4757                                      &stats,
4758                                      0);
4759                return scnprintf(
4760                        buf,acnt,
4761                        "Bytes streamed=%u URBs: queued=%u idle=%u ready=%u processed=%u failed=%u",
4762                        stats.bytes_processed,
4763                        stats.buffers_in_queue,
4764                        stats.buffers_in_idle,
4765                        stats.buffers_in_ready,
4766                        stats.buffers_processed,
4767                        stats.buffers_failed);
4768        }
4769        case 6: {
4770                unsigned int id = hdw->ir_scheme_active;
4771                return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4772                                 (id >= ARRAY_SIZE(ir_scheme_names) ?
4773                                  "?" : ir_scheme_names[id]));
4774        }
4775        default: break;
4776        }
4777        return 0;
4778}
4779
4780
4781/* Generate report containing info about attached sub-devices and attached
4782   i2c clients, including an indication of which attached i2c clients are
4783   actually sub-devices. */
4784static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4785                                            char *buf, unsigned int acnt)
4786{
4787        struct v4l2_subdev *sd;
4788        unsigned int tcnt = 0;
4789        unsigned int ccnt;
4790        struct i2c_client *client;
4791        const char *p;
4792        unsigned int id;
4793
4794        ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4795        tcnt += ccnt;
4796        v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4797                id = sd->grp_id;
4798                p = NULL;
4799                if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4800                if (p) {
4801                        ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4802                        tcnt += ccnt;
4803                } else {
4804                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4805                                         "  (unknown id=%u):", id);
4806                        tcnt += ccnt;
4807                }
4808                client = v4l2_get_subdevdata(sd);
4809                if (client) {
4810                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4811                                         " %s @ %02x\n", client->name,
4812                                         client->addr);
4813                        tcnt += ccnt;
4814                } else {
4815                        ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4816                                         " no i2c client\n");
4817                        tcnt += ccnt;
4818                }
4819        }
4820        return tcnt;
4821}
4822
4823
4824unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
4825                                   char *buf,unsigned int acnt)
4826{
4827        unsigned int bcnt,ccnt,idx;
4828        bcnt = 0;
4829        LOCK_TAKE(hdw->big_lock);
4830        for (idx = 0; ; idx++) {
4831                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
4832                if (!ccnt) break;
4833                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4834                if (!acnt) break;
4835                buf[0] = '\n'; ccnt = 1;
4836                bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4837        }
4838        ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
4839        bcnt += ccnt; acnt -= ccnt; buf += ccnt;
4840        LOCK_GIVE(hdw->big_lock);
4841        return bcnt;
4842}
4843
4844
4845static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
4846{
4847        char buf[256];
4848        unsigned int idx, ccnt;
4849        unsigned int lcnt, ucnt;
4850
4851        for (idx = 0; ; idx++) {
4852                ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
4853                if (!ccnt) break;
4854                printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
4855        }
4856        ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
4857        if (ccnt >= sizeof(buf))
4858                ccnt = sizeof(buf);
4859
4860        ucnt = 0;
4861        while (ucnt < ccnt) {
4862                lcnt = 0;
4863                while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
4864                        lcnt++;
4865                }
4866                printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
4867                ucnt += lcnt + 1;
4868        }
4869}
4870
4871
4872/* Evaluate and update the driver's current state, taking various actions
4873   as appropriate for the update. */
4874static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
4875{
4876        unsigned int st;
4877        int state_updated = 0;
4878        int callback_flag = 0;
4879        int analog_mode;
4880
4881        pvr2_trace(PVR2_TRACE_STBITS,
4882                   "Drive state check START");
4883        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4884                pvr2_hdw_state_log_state(hdw);
4885        }
4886
4887        /* Process all state and get back over disposition */
4888        state_updated = pvr2_hdw_state_update(hdw);
4889
4890        analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
4891
4892        /* Update master state based upon all other states. */
4893        if (!hdw->flag_ok) {
4894                st = PVR2_STATE_DEAD;
4895        } else if (hdw->fw1_state != FW1_STATE_OK) {
4896                st = PVR2_STATE_COLD;
4897        } else if ((analog_mode ||
4898                    hdw->hdw_desc->flag_digital_requires_cx23416) &&
4899                   !hdw->state_encoder_ok) {
4900                st = PVR2_STATE_WARM;
4901        } else if (hdw->flag_tripped ||
4902                   (analog_mode && hdw->flag_decoder_missed)) {
4903                st = PVR2_STATE_ERROR;
4904        } else if (hdw->state_usbstream_run &&
4905                   (!analog_mode ||
4906                    (hdw->state_encoder_run && hdw->state_decoder_run))) {
4907                st = PVR2_STATE_RUN;
4908        } else {
4909                st = PVR2_STATE_READY;
4910        }
4911        if (hdw->master_state != st) {
4912                pvr2_trace(PVR2_TRACE_STATE,
4913                           "Device state change from %s to %s",
4914                           pvr2_get_state_name(hdw->master_state),
4915                           pvr2_get_state_name(st));
4916                pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
4917                hdw->master_state = st;
4918                state_updated = !0;
4919                callback_flag = !0;
4920        }
4921        if (state_updated) {
4922                /* Trigger anyone waiting on any state changes here. */
4923                wake_up(&hdw->state_wait_data);
4924        }
4925
4926        if (pvrusb2_debug & PVR2_TRACE_STBITS) {
4927                pvr2_hdw_state_log_state(hdw);
4928        }
4929        pvr2_trace(PVR2_TRACE_STBITS,
4930                   "Drive state check DONE callback=%d",callback_flag);
4931
4932        return callback_flag;
4933}
4934
4935
4936/* Cause kernel thread to check / update driver state */
4937static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
4938{
4939        if (hdw->state_stale) return;
4940        hdw->state_stale = !0;
4941        trace_stbit("state_stale",hdw->state_stale);
4942        schedule_work(&hdw->workpoll);
4943}
4944
4945
4946int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
4947{
4948        return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
4949}
4950
4951
4952int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
4953{
4954        return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
4955}
4956
4957
4958int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
4959{
4960        return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
4961}
4962
4963
4964int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
4965{
4966        u32 cval,nval;
4967        int ret;
4968        if (~msk) {
4969                ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
4970                if (ret) return ret;
4971                nval = (cval & ~msk) | (val & msk);
4972                pvr2_trace(PVR2_TRACE_GPIO,
4973                           "GPIO direction changing 0x%x:0x%x from 0x%x to 0x%x",
4974                           msk,val,cval,nval);
4975        } else {
4976                nval = val;
4977                pvr2_trace(PVR2_TRACE_GPIO,
4978                           "GPIO direction changing to 0x%x",nval);
4979        }
4980        return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
4981}
4982
4983
4984int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
4985{
4986        u32 cval,nval;
4987        int ret;
4988        if (~msk) {
4989                ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
4990                if (ret) return ret;
4991                nval = (cval & ~msk) | (val & msk);
4992                pvr2_trace(PVR2_TRACE_GPIO,
4993                           "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
4994                           msk,val,cval,nval);
4995        } else {
4996                nval = val;
4997                pvr2_trace(PVR2_TRACE_GPIO,
4998                           "GPIO output changing to 0x%x",nval);
4999        }
5000        return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5001}
5002
5003
5004void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5005{
5006        struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5007        memset(vtp, 0, sizeof(*vtp));
5008        vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5009                V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5010        hdw->tuner_signal_stale = 0;
5011        /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5012           using v4l2-subdev - therefore we can't support that AT ALL right
5013           now.  (Of course, no sub-drivers seem to implement it either.
5014           But now it's a a chicken and egg problem...) */
5015        v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5016        pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll type=%u strength=%u audio=0x%x cap=0x%x low=%u hi=%u",
5017                   vtp->type,
5018                   vtp->signal, vtp->rxsubchans, vtp->capability,
5019                   vtp->rangelow, vtp->rangehigh);
5020
5021        /* We have to do this to avoid getting into constant polling if
5022           there's nobody to answer a poll of cropcap info. */
5023        hdw->cropcap_stale = 0;
5024}
5025
5026
5027unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5028{
5029        return hdw->input_avail_mask;
5030}
5031
5032
5033unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5034{
5035        return hdw->input_allowed_mask;
5036}
5037
5038
5039static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5040{
5041        if (hdw->input_val != v) {
5042                hdw->input_val = v;
5043                hdw->input_dirty = !0;
5044        }
5045
5046        /* Handle side effects - if we switch to a mode that needs the RF
5047           tuner, then select the right frequency choice as well and mark
5048           it dirty. */
5049        if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5050                hdw->freqSelector = 0;
5051                hdw->freqDirty = !0;
5052        } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5053                   (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5054                hdw->freqSelector = 1;
5055                hdw->freqDirty = !0;
5056        }
5057        return 0;
5058}
5059
5060
5061int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5062                               unsigned int change_mask,
5063                               unsigned int change_val)
5064{
5065        int ret = 0;
5066        unsigned int nv,m,idx;
5067        LOCK_TAKE(hdw->big_lock);
5068        do {
5069                nv = hdw->input_allowed_mask & ~change_mask;
5070                nv |= (change_val & change_mask);
5071                nv &= hdw->input_avail_mask;
5072                if (!nv) {
5073                        /* No legal modes left; return error instead. */
5074                        ret = -EPERM;
5075                        break;
5076                }
5077                hdw->input_allowed_mask = nv;
5078                if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5079                        /* Current mode is still in the allowed mask, so
5080                           we're done. */
5081                        break;
5082                }
5083                /* Select and switch to a mode that is still in the allowed
5084                   mask */
5085                if (!hdw->input_allowed_mask) {
5086                        /* Nothing legal; give up */
5087                        break;
5088                }
5089                m = hdw->input_allowed_mask;
5090                for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5091                        if (!((1 << idx) & m)) continue;
5092                        pvr2_hdw_set_input(hdw,idx);
5093                        break;
5094                }
5095        } while (0);
5096        LOCK_GIVE(hdw->big_lock);
5097        return ret;
5098}
5099
5100
5101/* Find I2C address of eeprom */
5102static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5103{
5104        int result;
5105        LOCK_TAKE(hdw->ctl_lock); do {
5106                hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5107                result = pvr2_send_request(hdw,
5108                                           hdw->cmd_buffer,1,
5109                                           hdw->cmd_buffer,1);
5110                if (result < 0) break;
5111                result = hdw->cmd_buffer[0];
5112        } while(0); LOCK_GIVE(hdw->ctl_lock);
5113        return result;
5114}
5115