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23#include <linux/module.h>
24#include <linux/bitops.h>
25#include <linux/delay.h>
26#include <linux/rtsx_pci.h>
27
28#include "rtsx_pcr.h"
29
30static u8 rtl8411_get_ic_version(struct rtsx_pcr *pcr)
31{
32 u8 val;
33
34 rtsx_pci_read_register(pcr, SYS_VER, &val);
35 return val & 0x0F;
36}
37
38static int rtl8411b_is_qfn48(struct rtsx_pcr *pcr)
39{
40 u8 val = 0;
41
42 rtsx_pci_read_register(pcr, RTL8411B_PACKAGE_MODE, &val);
43
44 if (val & 0x2)
45 return 1;
46 else
47 return 0;
48}
49
50static void rtl8411_fetch_vendor_settings(struct rtsx_pcr *pcr)
51{
52 u32 reg1 = 0;
53 u8 reg3 = 0;
54
55 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1);
56 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1);
57
58 if (!rtsx_vendor_setting_valid(reg1))
59 return;
60
61 pcr->aspm_en = rtsx_reg_to_aspm(reg1);
62 pcr->sd30_drive_sel_1v8 =
63 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1));
64 pcr->card_drive_sel &= 0x3F;
65 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1);
66
67 rtsx_pci_read_config_byte(pcr, PCR_SETTING_REG3, ®3);
68 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG3, reg3);
69 pcr->sd30_drive_sel_3v3 = rtl8411_reg_to_sd30_drive_sel_3v3(reg3);
70}
71
72static void rtl8411b_fetch_vendor_settings(struct rtsx_pcr *pcr)
73{
74 u32 reg = 0;
75
76 rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®);
77 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
78
79 if (!rtsx_vendor_setting_valid(reg))
80 return;
81
82 pcr->aspm_en = rtsx_reg_to_aspm(reg);
83 pcr->sd30_drive_sel_1v8 =
84 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg));
85 pcr->sd30_drive_sel_3v3 =
86 map_sd_drive(rtl8411b_reg_to_sd30_drive_sel_3v3(reg));
87}
88
89static void rtl8411_force_power_down(struct rtsx_pcr *pcr, u8 pm_state)
90{
91 rtsx_pci_write_register(pcr, FPDCTL, 0x07, 0x07);
92}
93
94static int rtl8411_extra_init_hw(struct rtsx_pcr *pcr)
95{
96 rtsx_pci_init_cmd(pcr);
97
98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
99 0xFF, pcr->sd30_drive_sel_3v3);
100 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
101 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
102
103 return rtsx_pci_send_cmd(pcr, 100);
104}
105
106static int rtl8411b_extra_init_hw(struct rtsx_pcr *pcr)
107{
108 rtsx_pci_init_cmd(pcr);
109
110 if (rtl8411b_is_qfn48(pcr))
111 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
112 CARD_PULL_CTL3, 0xFF, 0xF5);
113 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DRIVE_SEL,
114 0xFF, pcr->sd30_drive_sel_3v3);
115 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CD_PAD_CTL,
116 CD_DISABLE_MASK | CD_AUTO_DISABLE, CD_ENABLE);
117 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, FUNC_FORCE_CTL,
118 0x06, 0x00);
119
120 return rtsx_pci_send_cmd(pcr, 100);
121}
122
123static int rtl8411_turn_on_led(struct rtsx_pcr *pcr)
124{
125 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x00);
126}
127
128static int rtl8411_turn_off_led(struct rtsx_pcr *pcr)
129{
130 return rtsx_pci_write_register(pcr, CARD_GPIO, 0x01, 0x01);
131}
132
133static int rtl8411_enable_auto_blink(struct rtsx_pcr *pcr)
134{
135 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0xFF, 0x0D);
136}
137
138static int rtl8411_disable_auto_blink(struct rtsx_pcr *pcr)
139{
140 return rtsx_pci_write_register(pcr, CARD_AUTO_BLINK, 0x08, 0x00);
141}
142
143static int rtl8411_card_power_on(struct rtsx_pcr *pcr, int card)
144{
145 int err;
146
147 rtsx_pci_init_cmd(pcr);
148 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
149 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
150 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_CTL,
151 BPP_LDO_POWB, BPP_LDO_SUSPEND);
152 err = rtsx_pci_send_cmd(pcr, 100);
153 if (err < 0)
154 return err;
155
156
157 udelay(150);
158
159 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
160 BPP_POWER_MASK, BPP_POWER_10_PERCENT_ON);
161 if (err < 0)
162 return err;
163
164 udelay(150);
165
166 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
167 BPP_POWER_MASK, BPP_POWER_15_PERCENT_ON);
168 if (err < 0)
169 return err;
170
171 udelay(150);
172
173 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
174 BPP_POWER_MASK, BPP_POWER_ON);
175 if (err < 0)
176 return err;
177
178 return rtsx_pci_write_register(pcr, LDO_CTL, BPP_LDO_POWB, BPP_LDO_ON);
179}
180
181static int rtl8411_card_power_off(struct rtsx_pcr *pcr, int card)
182{
183 int err;
184
185 err = rtsx_pci_write_register(pcr, CARD_PWR_CTL,
186 BPP_POWER_MASK, BPP_POWER_OFF);
187 if (err < 0)
188 return err;
189
190 return rtsx_pci_write_register(pcr, LDO_CTL,
191 BPP_LDO_POWB, BPP_LDO_SUSPEND);
192}
193
194static int rtl8411_do_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage,
195 int bpp_tuned18_shift, int bpp_asic_1v8)
196{
197 u8 mask, val;
198 int err;
199
200 mask = (BPP_REG_TUNED18 << bpp_tuned18_shift) | BPP_PAD_MASK;
201 if (voltage == OUTPUT_3V3) {
202 err = rtsx_pci_write_register(pcr,
203 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_3v3);
204 if (err < 0)
205 return err;
206 val = (BPP_ASIC_3V3 << bpp_tuned18_shift) | BPP_PAD_3V3;
207 } else if (voltage == OUTPUT_1V8) {
208 err = rtsx_pci_write_register(pcr,
209 SD30_DRIVE_SEL, 0x07, pcr->sd30_drive_sel_1v8);
210 if (err < 0)
211 return err;
212 val = (bpp_asic_1v8 << bpp_tuned18_shift) | BPP_PAD_1V8;
213 } else {
214 return -EINVAL;
215 }
216
217 return rtsx_pci_write_register(pcr, LDO_CTL, mask, val);
218}
219
220static int rtl8411_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
221{
222 return rtl8411_do_switch_output_voltage(pcr, voltage,
223 BPP_TUNED18_SHIFT_8411, BPP_ASIC_1V8);
224}
225
226static int rtl8402_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
227{
228 return rtl8411_do_switch_output_voltage(pcr, voltage,
229 BPP_TUNED18_SHIFT_8402, BPP_ASIC_2V0);
230}
231
232static unsigned int rtl8411_cd_deglitch(struct rtsx_pcr *pcr)
233{
234 unsigned int card_exist;
235
236 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
237 card_exist &= CARD_EXIST;
238 if (!card_exist) {
239
240 rtsx_pci_write_register(pcr, CD_PAD_CTL,
241 CD_DISABLE_MASK, CD_ENABLE);
242
243 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x00);
244 return 0;
245 }
246
247 if (hweight32(card_exist) > 1) {
248 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
249 BPP_POWER_MASK, BPP_POWER_5_PERCENT_ON);
250 msleep(100);
251
252 card_exist = rtsx_pci_readl(pcr, RTSX_BIPR);
253 if (card_exist & MS_EXIST)
254 card_exist = MS_EXIST;
255 else if (card_exist & SD_EXIST)
256 card_exist = SD_EXIST;
257 else
258 card_exist = 0;
259
260 rtsx_pci_write_register(pcr, CARD_PWR_CTL,
261 BPP_POWER_MASK, BPP_POWER_OFF);
262
263 pcr_dbg(pcr, "After CD deglitch, card_exist = 0x%x\n",
264 card_exist);
265 }
266
267 if (card_exist & MS_EXIST) {
268
269 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x40);
270 rtsx_pci_write_register(pcr, CD_PAD_CTL,
271 CD_DISABLE_MASK, MS_CD_EN_ONLY);
272 } else if (card_exist & SD_EXIST) {
273
274 rtsx_pci_write_register(pcr, EFUSE_CONTENT, 0xe0, 0x80);
275 rtsx_pci_write_register(pcr, CD_PAD_CTL,
276 CD_DISABLE_MASK, SD_CD_EN_ONLY);
277 }
278
279 return card_exist;
280}
281
282static int rtl8411_conv_clk_and_div_n(int input, int dir)
283{
284 int output;
285
286 if (dir == CLK_TO_DIV_N)
287 output = input * 4 / 5 - 2;
288 else
289 output = (input + 2) * 5 / 4;
290
291 return output;
292}
293
294static const struct pcr_ops rtl8411_pcr_ops = {
295 .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
296 .extra_init_hw = rtl8411_extra_init_hw,
297 .optimize_phy = NULL,
298 .turn_on_led = rtl8411_turn_on_led,
299 .turn_off_led = rtl8411_turn_off_led,
300 .enable_auto_blink = rtl8411_enable_auto_blink,
301 .disable_auto_blink = rtl8411_disable_auto_blink,
302 .card_power_on = rtl8411_card_power_on,
303 .card_power_off = rtl8411_card_power_off,
304 .switch_output_voltage = rtl8411_switch_output_voltage,
305 .cd_deglitch = rtl8411_cd_deglitch,
306 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
307 .force_power_down = rtl8411_force_power_down,
308};
309
310static const struct pcr_ops rtl8402_pcr_ops = {
311 .fetch_vendor_settings = rtl8411_fetch_vendor_settings,
312 .extra_init_hw = rtl8411_extra_init_hw,
313 .optimize_phy = NULL,
314 .turn_on_led = rtl8411_turn_on_led,
315 .turn_off_led = rtl8411_turn_off_led,
316 .enable_auto_blink = rtl8411_enable_auto_blink,
317 .disable_auto_blink = rtl8411_disable_auto_blink,
318 .card_power_on = rtl8411_card_power_on,
319 .card_power_off = rtl8411_card_power_off,
320 .switch_output_voltage = rtl8402_switch_output_voltage,
321 .cd_deglitch = rtl8411_cd_deglitch,
322 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
323 .force_power_down = rtl8411_force_power_down,
324};
325
326static const struct pcr_ops rtl8411b_pcr_ops = {
327 .fetch_vendor_settings = rtl8411b_fetch_vendor_settings,
328 .extra_init_hw = rtl8411b_extra_init_hw,
329 .optimize_phy = NULL,
330 .turn_on_led = rtl8411_turn_on_led,
331 .turn_off_led = rtl8411_turn_off_led,
332 .enable_auto_blink = rtl8411_enable_auto_blink,
333 .disable_auto_blink = rtl8411_disable_auto_blink,
334 .card_power_on = rtl8411_card_power_on,
335 .card_power_off = rtl8411_card_power_off,
336 .switch_output_voltage = rtl8411_switch_output_voltage,
337 .cd_deglitch = rtl8411_cd_deglitch,
338 .conv_clk_and_div_n = rtl8411_conv_clk_and_div_n,
339 .force_power_down = rtl8411_force_power_down,
340};
341
342
343
344
345
346
347
348
349static const u32 rtl8411_sd_pull_ctl_enable_tbl[] = {
350 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
351 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
352 RTSX_REG_PAIR(CARD_PULL_CTL3, 0xA9),
353 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
354 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x09),
355 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
356 0,
357};
358
359
360
361
362
363
364
365
366static const u32 rtl8411_sd_pull_ctl_disable_tbl[] = {
367 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
368 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
369 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
370 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
371 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
372 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
373 0,
374};
375
376
377
378
379
380static const u32 rtl8411_ms_pull_ctl_enable_tbl[] = {
381 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
382 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
383 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
384 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05),
385 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
386 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
387 0,
388};
389
390
391
392
393
394static const u32 rtl8411_ms_pull_ctl_disable_tbl[] = {
395 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
396 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
397 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x95),
398 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09),
399 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05),
400 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04),
401 0,
402};
403
404static const u32 rtl8411b_qfn64_sd_pull_ctl_enable_tbl[] = {
405 RTSX_REG_PAIR(CARD_PULL_CTL1, 0xAA),
406 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
407 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x09 | 0xD0),
408 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
409 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
410 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
411 0,
412};
413
414static const u32 rtl8411b_qfn48_sd_pull_ctl_enable_tbl[] = {
415 RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
416 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x69 | 0x90),
417 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x08 | 0x11),
418 0,
419};
420
421static const u32 rtl8411b_qfn64_sd_pull_ctl_disable_tbl[] = {
422 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
423 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
424 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
425 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
426 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
427 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
428 0,
429};
430
431static const u32 rtl8411b_qfn48_sd_pull_ctl_disable_tbl[] = {
432 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
433 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
434 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
435 0,
436};
437
438static const u32 rtl8411b_qfn64_ms_pull_ctl_enable_tbl[] = {
439 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
440 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
441 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
442 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x05 | 0x50),
443 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
444 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
445 0,
446};
447
448static const u32 rtl8411b_qfn48_ms_pull_ctl_enable_tbl[] = {
449 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
450 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
451 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
452 0,
453};
454
455static const u32 rtl8411b_qfn64_ms_pull_ctl_disable_tbl[] = {
456 RTSX_REG_PAIR(CARD_PULL_CTL1, 0x65),
457 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
458 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x05 | 0xD0),
459 RTSX_REG_PAIR(CARD_PULL_CTL4, 0x09 | 0x50),
460 RTSX_REG_PAIR(CARD_PULL_CTL5, 0x05 | 0x50),
461 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
462 0,
463};
464
465static const u32 rtl8411b_qfn48_ms_pull_ctl_disable_tbl[] = {
466 RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
467 RTSX_REG_PAIR(CARD_PULL_CTL3, 0x65 | 0x90),
468 RTSX_REG_PAIR(CARD_PULL_CTL6, 0x04 | 0x11),
469 0,
470};
471
472static void rtl8411_init_common_params(struct rtsx_pcr *pcr)
473{
474 pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
475 pcr->num_slots = 2;
476 pcr->flags = 0;
477 pcr->card_drive_sel = RTL8411_CARD_DRIVE_DEFAULT;
478 pcr->sd30_drive_sel_1v8 = DRIVER_TYPE_B;
479 pcr->sd30_drive_sel_3v3 = DRIVER_TYPE_D;
480 pcr->aspm_en = ASPM_L1_EN;
481 pcr->tx_initial_phase = SET_CLOCK_PHASE(23, 7, 14);
482 pcr->rx_initial_phase = SET_CLOCK_PHASE(4, 3, 10);
483 pcr->ic_version = rtl8411_get_ic_version(pcr);
484}
485
486void rtl8411_init_params(struct rtsx_pcr *pcr)
487{
488 rtl8411_init_common_params(pcr);
489 pcr->ops = &rtl8411_pcr_ops;
490 set_pull_ctrl_tables(pcr, rtl8411);
491}
492
493void rtl8411b_init_params(struct rtsx_pcr *pcr)
494{
495 rtl8411_init_common_params(pcr);
496 pcr->ops = &rtl8411b_pcr_ops;
497 if (rtl8411b_is_qfn48(pcr))
498 set_pull_ctrl_tables(pcr, rtl8411b_qfn48);
499 else
500 set_pull_ctrl_tables(pcr, rtl8411b_qfn64);
501}
502
503void rtl8402_init_params(struct rtsx_pcr *pcr)
504{
505 rtl8411_init_common_params(pcr);
506 pcr->ops = &rtl8402_pcr_ops;
507 set_pull_ctrl_tables(pcr, rtl8411);
508}
509
