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7#ifndef _SGISEEQ_H
8#define _SGISEEQ_H
9
10struct sgiseeq_wregs {
11 volatile unsigned int multicase_high[2];
12 volatile unsigned int frame_gap;
13 volatile unsigned int control;
14};
15
16struct sgiseeq_rregs {
17 volatile unsigned int collision_tx[2];
18 volatile unsigned int collision_all[2];
19 volatile unsigned int _unused0;
20 volatile unsigned int rflags;
21};
22
23struct sgiseeq_regs {
24 union {
25 volatile unsigned int eth_addr[6];
26 volatile unsigned int multicast_low[6];
27 struct sgiseeq_wregs wregs;
28 struct sgiseeq_rregs rregs;
29 } rw;
30 volatile unsigned int rstat;
31 volatile unsigned int tstat;
32};
33
34
35#define SEEQ_RSTAT_OVERF 0x001
36#define SEEQ_RSTAT_CERROR 0x002
37#define SEEQ_RSTAT_DERROR 0x004
38#define SEEQ_RSTAT_SFRAME 0x008
39#define SEEQ_RSTAT_REOF 0x010
40#define SEEQ_RSTAT_FIG 0x020
41#define SEEQ_RSTAT_TIMEO 0x040
42#define SEEQ_RSTAT_WHICH 0x080
43#define SEEQ_RSTAT_LITTLE 0x100
44#define SEEQ_RSTAT_SDMA 0x200
45#define SEEQ_RSTAT_ADMA 0x400
46#define SEEQ_RSTAT_ROVERF 0x800
47
48
49#define SEEQ_RCMD_RDISAB 0x000
50#define SEEQ_RCMD_IOVERF 0x001
51#define SEEQ_RCMD_ICRC 0x002
52#define SEEQ_RCMD_IDRIB 0x004
53#define SEEQ_RCMD_ISHORT 0x008
54#define SEEQ_RCMD_IEOF 0x010
55#define SEEQ_RCMD_IGOOD 0x020
56#define SEEQ_RCMD_RANY 0x040
57#define SEEQ_RCMD_RBCAST 0x080
58#define SEEQ_RCMD_RBMCAST 0x0c0
59
60
61#define SEEQ_TSTAT_UFLOW 0x001
62#define SEEQ_TSTAT_CLS 0x002
63#define SEEQ_TSTAT_R16 0x004
64#define SEEQ_TSTAT_PTRANS 0x008
65#define SEEQ_TSTAT_LCLS 0x010
66#define SEEQ_TSTAT_WHICH 0x080
67#define SEEQ_TSTAT_TLE 0x100
68#define SEEQ_TSTAT_SDMA 0x200
69#define SEEQ_TSTAT_ADMA 0x400
70
71
72#define SEEQ_TCMD_RB0 0x00
73#define SEEQ_TCMD_IUF 0x01
74#define SEEQ_TCMD_IC 0x02
75#define SEEQ_TCMD_I16 0x04
76#define SEEQ_TCMD_IPT 0x08
77#define SEEQ_TCMD_RB1 0x20
78#define SEEQ_TCMD_RB2 0x40
79
80
81#define SEEQ_CTRL_XCNT 0x01
82#define SEEQ_CTRL_ACCNT 0x02
83#define SEEQ_CTRL_SFLAG 0x04
84#define SEEQ_CTRL_EMULTI 0x08
85#define SEEQ_CTRL_ESHORT 0x10
86#define SEEQ_CTRL_ENCARR 0x20
87
88
89#define SEEQ_HPIO_P1BITS 0x00000001
90#define SEEQ_HPIO_P2BITS 0x00000060
91#define SEEQ_HPIO_P3BITS 0x00000100
92#define SEEQ_HDMA_D1BITS 0x00000006
93#define SEEQ_HDMA_D2BITS 0x00000020
94#define SEEQ_HDMA_D3BITS 0x00000000
95#define SEEQ_HDMA_TIMEO 0x00030000
96#define SEEQ_HCTL_NORM 0x00000000
97#define SEEQ_HCTL_RESET 0x00000001
98#define SEEQ_HCTL_IPEND 0x00000002
99#define SEEQ_HCTL_IPG 0x00001000
100#define SEEQ_HCTL_RFIX 0x00002000
101#define SEEQ_HCTL_EFIX 0x00004000
102#define SEEQ_HCTL_IFIX 0x00008000
103
104#endif
105