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17#include "hw.h"
18#include "hw-ops.h"
19#include "../regd.h"
20#include "ar9002_phy.h"
21#include "ar5008_initvals.h"
22
23
24
25#define AR5008_OFDM_RATES 8
26#define AR5008_HT_SS_RATES 8
27#define AR5008_HT_DS_RATES 8
28
29#define AR5008_HT20_SHIFT 16
30#define AR5008_HT40_SHIFT 24
31
32#define AR5008_11NA_OFDM_SHIFT 0
33#define AR5008_11NA_HT_SS_SHIFT 8
34#define AR5008_11NA_HT_DS_SHIFT 16
35
36#define AR5008_11NG_OFDM_SHIFT 4
37#define AR5008_11NG_HT_SS_SHIFT 12
38#define AR5008_11NG_HT_DS_SHIFT 20
39
40static const int firstep_table[] =
41
42 { -4, -2, 0, 2, 4, 6, 8, 10, 12 };
43
44
45
46
47static const int m1ThreshLow_off = 127;
48static const int m2ThreshLow_off = 127;
49static const int m1Thresh_off = 127;
50static const int m2Thresh_off = 127;
51static const int m2CountThr_off = 31;
52static const int m2CountThrLow_off = 63;
53static const int m1ThreshLowExt_off = 127;
54static const int m2ThreshLowExt_off = 127;
55static const int m1ThreshExt_off = 127;
56static const int m2ThreshExt_off = 127;
57
58static const struct ar5416IniArray bank0 = STATIC_INI_ARRAY(ar5416Bank0);
59static const struct ar5416IniArray bank1 = STATIC_INI_ARRAY(ar5416Bank1);
60static const struct ar5416IniArray bank2 = STATIC_INI_ARRAY(ar5416Bank2);
61static const struct ar5416IniArray bank3 = STATIC_INI_ARRAY(ar5416Bank3);
62static const struct ar5416IniArray bank7 = STATIC_INI_ARRAY(ar5416Bank7);
63
64static void ar5008_write_bank6(struct ath_hw *ah, unsigned int *writecnt)
65{
66 struct ar5416IniArray *array = &ah->iniBank6;
67 u32 *data = ah->analogBank6Data;
68 int r;
69
70 ENABLE_REGWRITE_BUFFER(ah);
71
72 for (r = 0; r < array->ia_rows; r++) {
73 REG_WRITE(ah, INI_RA(array, r, 0), data[r]);
74 DO_DELAY(*writecnt);
75 }
76
77 REGWRITE_BUFFER_FLUSH(ah);
78}
79
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89
90
91static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
92 u32 numBits, u32 firstBit,
93 u32 column)
94{
95 u32 tmp32, mask, arrayEntry, lastBit;
96 int32_t bitPosition, bitsLeft;
97
98 tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
99 arrayEntry = (firstBit - 1) / 8;
100 bitPosition = (firstBit - 1) % 8;
101 bitsLeft = numBits;
102 while (bitsLeft > 0) {
103 lastBit = (bitPosition + bitsLeft > 8) ?
104 8 : bitPosition + bitsLeft;
105 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
106 (column * 8);
107 rfBuf[arrayEntry] &= ~mask;
108 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
109 (column * 8)) & mask;
110 bitsLeft -= 8 - bitPosition;
111 tmp32 = tmp32 >> (8 - bitPosition);
112 bitPosition = 0;
113 arrayEntry++;
114 }
115}
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143
144static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
145{
146 struct ath_common *common = ath9k_hw_common(ah);
147 u32 tmp_reg;
148 int reg_writes = 0;
149 u32 new_bias = 0;
150
151 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
152 return;
153
154 BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
155
156 if (synth_freq < 2412)
157 new_bias = 0;
158 else if (synth_freq < 2422)
159 new_bias = 1;
160 else
161 new_bias = 2;
162
163
164 tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
165
166 ath_dbg(common, CONFIG, "Force rf_pwd_icsyndiv to %1d on %4d\n",
167 new_bias, synth_freq);
168
169
170 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
171
172
173 ar5008_write_bank6(ah, ®_writes);
174}
175
176
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179
180
181
182
183
184
185static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
186{
187 struct ath_common *common = ath9k_hw_common(ah);
188 u32 channelSel = 0;
189 u32 bModeSynth = 0;
190 u32 aModeRefSel = 0;
191 u32 reg32 = 0;
192 u16 freq;
193 struct chan_centers centers;
194
195 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
196 freq = centers.synth_center;
197
198 if (freq < 4800) {
199 u32 txctl;
200
201 if (((freq - 2192) % 5) == 0) {
202 channelSel = ((freq - 672) * 2 - 3040) / 10;
203 bModeSynth = 0;
204 } else if (((freq - 2224) % 5) == 0) {
205 channelSel = ((freq - 704) * 2 - 3040) / 10;
206 bModeSynth = 1;
207 } else {
208 ath_err(common, "Invalid channel %u MHz\n", freq);
209 return -EINVAL;
210 }
211
212 channelSel = (channelSel << 2) & 0xff;
213 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
214
215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
216 if (freq == 2484) {
217
218 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
219 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
220 } else {
221 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
222 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
223 }
224
225 } else if ((freq % 20) == 0 && freq >= 5120) {
226 channelSel =
227 ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
228 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
229 } else if ((freq % 10) == 0) {
230 channelSel =
231 ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
232 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
233 aModeRefSel = ath9k_hw_reverse_bits(2, 2);
234 else
235 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
236 } else if ((freq % 5) == 0) {
237 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
238 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
239 } else {
240 ath_err(common, "Invalid channel %u MHz\n", freq);
241 return -EINVAL;
242 }
243
244 ar5008_hw_force_bias(ah, freq);
245
246 reg32 =
247 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
248 (1 << 5) | 0x1;
249
250 REG_WRITE(ah, AR_PHY(0x37), reg32);
251
252 ah->curchan = chan;
253
254 return 0;
255}
256
257void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
258 struct ath9k_channel *chan, int bin)
259{
260 int cur_bin;
261 int upper, lower, cur_vit_mask;
262 int i;
263 int8_t mask_m[123] = {0};
264 int8_t mask_p[123] = {0};
265 int8_t mask_amt;
266 int tmp_mask;
267 static const int pilot_mask_reg[4] = {
268 AR_PHY_TIMING7, AR_PHY_TIMING8,
269 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
270 };
271 static const int chan_mask_reg[4] = {
272 AR_PHY_TIMING9, AR_PHY_TIMING10,
273 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
274 };
275 static const int inc[4] = { 0, 100, 0, 0 };
276
277 cur_bin = -6000;
278 upper = bin + 100;
279 lower = bin - 100;
280
281 for (i = 0; i < 4; i++) {
282 int pilot_mask = 0;
283 int chan_mask = 0;
284 int bp = 0;
285
286 for (bp = 0; bp < 30; bp++) {
287 if ((cur_bin > lower) && (cur_bin < upper)) {
288 pilot_mask = pilot_mask | 0x1 << bp;
289 chan_mask = chan_mask | 0x1 << bp;
290 }
291 cur_bin += 100;
292 }
293 cur_bin += inc[i];
294 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
295 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
296 }
297
298 cur_vit_mask = 6100;
299 upper = bin + 120;
300 lower = bin - 120;
301
302 for (i = 0; i < ARRAY_SIZE(mask_m); i++) {
303 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
304
305 volatile int tmp_v = abs(cur_vit_mask - bin);
306
307 if (tmp_v < 75)
308 mask_amt = 1;
309 else
310 mask_amt = 0;
311 if (cur_vit_mask < 0)
312 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
313 else
314 mask_p[cur_vit_mask / 100] = mask_amt;
315 }
316 cur_vit_mask -= 100;
317 }
318
319 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
320 | (mask_m[48] << 26) | (mask_m[49] << 24)
321 | (mask_m[50] << 22) | (mask_m[51] << 20)
322 | (mask_m[52] << 18) | (mask_m[53] << 16)
323 | (mask_m[54] << 14) | (mask_m[55] << 12)
324 | (mask_m[56] << 10) | (mask_m[57] << 8)
325 | (mask_m[58] << 6) | (mask_m[59] << 4)
326 | (mask_m[60] << 2) | (mask_m[61] << 0);
327 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
328 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
329
330 tmp_mask = (mask_m[31] << 28)
331 | (mask_m[32] << 26) | (mask_m[33] << 24)
332 | (mask_m[34] << 22) | (mask_m[35] << 20)
333 | (mask_m[36] << 18) | (mask_m[37] << 16)
334 | (mask_m[48] << 14) | (mask_m[39] << 12)
335 | (mask_m[40] << 10) | (mask_m[41] << 8)
336 | (mask_m[42] << 6) | (mask_m[43] << 4)
337 | (mask_m[44] << 2) | (mask_m[45] << 0);
338 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
339 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
340
341 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
342 | (mask_m[18] << 26) | (mask_m[18] << 24)
343 | (mask_m[20] << 22) | (mask_m[20] << 20)
344 | (mask_m[22] << 18) | (mask_m[22] << 16)
345 | (mask_m[24] << 14) | (mask_m[24] << 12)
346 | (mask_m[25] << 10) | (mask_m[26] << 8)
347 | (mask_m[27] << 6) | (mask_m[28] << 4)
348 | (mask_m[29] << 2) | (mask_m[30] << 0);
349 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
350 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
351
352 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
353 | (mask_m[2] << 26) | (mask_m[3] << 24)
354 | (mask_m[4] << 22) | (mask_m[5] << 20)
355 | (mask_m[6] << 18) | (mask_m[7] << 16)
356 | (mask_m[8] << 14) | (mask_m[9] << 12)
357 | (mask_m[10] << 10) | (mask_m[11] << 8)
358 | (mask_m[12] << 6) | (mask_m[13] << 4)
359 | (mask_m[14] << 2) | (mask_m[15] << 0);
360 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
361 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
362
363 tmp_mask = (mask_p[15] << 28)
364 | (mask_p[14] << 26) | (mask_p[13] << 24)
365 | (mask_p[12] << 22) | (mask_p[11] << 20)
366 | (mask_p[10] << 18) | (mask_p[9] << 16)
367 | (mask_p[8] << 14) | (mask_p[7] << 12)
368 | (mask_p[6] << 10) | (mask_p[5] << 8)
369 | (mask_p[4] << 6) | (mask_p[3] << 4)
370 | (mask_p[2] << 2) | (mask_p[1] << 0);
371 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
372 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
373
374 tmp_mask = (mask_p[30] << 28)
375 | (mask_p[29] << 26) | (mask_p[28] << 24)
376 | (mask_p[27] << 22) | (mask_p[26] << 20)
377 | (mask_p[25] << 18) | (mask_p[24] << 16)
378 | (mask_p[23] << 14) | (mask_p[22] << 12)
379 | (mask_p[21] << 10) | (mask_p[20] << 8)
380 | (mask_p[19] << 6) | (mask_p[18] << 4)
381 | (mask_p[17] << 2) | (mask_p[16] << 0);
382 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
383 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
384
385 tmp_mask = (mask_p[45] << 28)
386 | (mask_p[44] << 26) | (mask_p[43] << 24)
387 | (mask_p[42] << 22) | (mask_p[41] << 20)
388 | (mask_p[40] << 18) | (mask_p[39] << 16)
389 | (mask_p[38] << 14) | (mask_p[37] << 12)
390 | (mask_p[36] << 10) | (mask_p[35] << 8)
391 | (mask_p[34] << 6) | (mask_p[33] << 4)
392 | (mask_p[32] << 2) | (mask_p[31] << 0);
393 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
394 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
395
396 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
397 | (mask_p[59] << 26) | (mask_p[58] << 24)
398 | (mask_p[57] << 22) | (mask_p[56] << 20)
399 | (mask_p[55] << 18) | (mask_p[54] << 16)
400 | (mask_p[53] << 14) | (mask_p[52] << 12)
401 | (mask_p[51] << 10) | (mask_p[50] << 8)
402 | (mask_p[49] << 6) | (mask_p[48] << 4)
403 | (mask_p[47] << 2) | (mask_p[46] << 0);
404 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
405 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
406}
407
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413
414
415
416static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
417 struct ath9k_channel *chan)
418{
419 int bb_spur = AR_NO_SPUR;
420 int bin;
421 int spur_freq_sd;
422 int spur_delta_phase;
423 int denominator;
424 int tmp, new;
425 int i;
426
427 int cur_bb_spur;
428 bool is2GHz = IS_CHAN_2GHZ(chan);
429
430 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
431 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
432 if (AR_NO_SPUR == cur_bb_spur)
433 break;
434 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
435 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
436 bb_spur = cur_bb_spur;
437 break;
438 }
439 }
440
441 if (AR_NO_SPUR == bb_spur)
442 return;
443
444 bin = bb_spur * 32;
445
446 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
447 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
448 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
449 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
450 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
451
452 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
453
454 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
455 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
456 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
457 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
458 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
459 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
460
461 spur_delta_phase = ((bb_spur * 524288) / 100) &
462 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
463
464 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
465 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
466
467 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
468 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
469 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
470 REG_WRITE(ah, AR_PHY_TIMING11, new);
471
472 ar5008_hw_cmn_spur_mitigate(ah, chan, bin);
473}
474
475
476
477
478
479
480
481static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
482{
483 int size = ah->iniBank6.ia_rows * sizeof(u32);
484
485 if (AR_SREV_9280_20_OR_LATER(ah))
486 return 0;
487
488 ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);
489 if (!ah->analogBank6Data)
490 return -ENOMEM;
491
492 return 0;
493}
494
495
496
497
498
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505
506
507
508static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
509 struct ath9k_channel *chan,
510 u16 modesIndex)
511{
512 u32 eepMinorRev;
513 u32 ob5GHz = 0, db5GHz = 0;
514 u32 ob2GHz = 0, db2GHz = 0;
515 int regWrites = 0;
516 int i;
517
518
519
520
521
522
523 if (AR_SREV_9280_20_OR_LATER(ah))
524 return true;
525
526
527 eepMinorRev = ah->eep_ops->get_eeprom_rev(ah);
528
529 for (i = 0; i < ah->iniBank6.ia_rows; i++)
530 ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);
531
532
533 if (eepMinorRev >= 2) {
534 if (IS_CHAN_2GHZ(chan)) {
535 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
536 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
537 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
538 ob2GHz, 3, 197, 0);
539 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
540 db2GHz, 3, 194, 0);
541 } else {
542 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
543 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
544 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
545 ob5GHz, 3, 203, 0);
546 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
547 db5GHz, 3, 200, 0);
548 }
549 }
550
551
552 REG_WRITE_ARRAY(&bank0, 1, regWrites);
553 REG_WRITE_ARRAY(&bank1, 1, regWrites);
554 REG_WRITE_ARRAY(&bank2, 1, regWrites);
555 REG_WRITE_ARRAY(&bank3, modesIndex, regWrites);
556 ar5008_write_bank6(ah, ®Writes);
557 REG_WRITE_ARRAY(&bank7, 1, regWrites);
558
559 return true;
560}
561
562static void ar5008_hw_init_bb(struct ath_hw *ah,
563 struct ath9k_channel *chan)
564{
565 u32 synthDelay;
566
567 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
568
569 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
570
571 ath9k_hw_synth_delay(ah, chan, synthDelay);
572}
573
574static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
575{
576 int rx_chainmask, tx_chainmask;
577
578 rx_chainmask = ah->rxchainmask;
579 tx_chainmask = ah->txchainmask;
580
581
582 switch (rx_chainmask) {
583 case 0x5:
584 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
585 AR_PHY_SWAP_ALT_CHAIN);
586
587 case 0x3:
588 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
589 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
590 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
591 break;
592 }
593
594 case 0x1:
595 case 0x2:
596 case 0x7:
597 ENABLE_REGWRITE_BUFFER(ah);
598 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
599 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
600 break;
601 default:
602 ENABLE_REGWRITE_BUFFER(ah);
603 break;
604 }
605
606 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
607
608 REGWRITE_BUFFER_FLUSH(ah);
609
610 if (tx_chainmask == 0x5) {
611 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
612 AR_PHY_SWAP_ALT_CHAIN);
613 }
614 if (AR_SREV_9100(ah))
615 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
616 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
617}
618
619static void ar5008_hw_override_ini(struct ath_hw *ah,
620 struct ath9k_channel *chan)
621{
622 u32 val;
623
624
625
626
627
628
629 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
630
631 if (AR_SREV_9280_20_OR_LATER(ah)) {
632
633
634
635
636
637
638
639 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
640 (~AR_ADHOC_MCAST_KEYID_ENABLE);
641
642 if (!AR_SREV_9271(ah))
643 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
644
645 if (AR_SREV_9287_11_OR_LATER(ah))
646 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
647
648 val |= AR_PCU_MISC_MODE2_CFP_IGNORE;
649
650 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
651 }
652
653 if (AR_SREV_9280_20_OR_LATER(ah))
654 return;
655
656
657
658
659 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
660
661
662
663
664
665 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
666 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
667 val &= ~AR_PHY_RIFS_INIT_DELAY;
668 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
669 }
670}
671
672static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
673 struct ath9k_channel *chan)
674{
675 u32 phymode;
676 u32 enableDacFifo = 0;
677
678 if (AR_SREV_9285_12_OR_LATER(ah))
679 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
680 AR_PHY_FC_ENABLE_DAC_FIFO);
681
682 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
683 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
684
685 if (IS_CHAN_HT40(chan)) {
686 phymode |= AR_PHY_FC_DYN2040_EN;
687
688 if (IS_CHAN_HT40PLUS(chan))
689 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
690
691 }
692 ENABLE_REGWRITE_BUFFER(ah);
693 REG_WRITE(ah, AR_PHY_TURBO, phymode);
694
695
696
697 ath9k_hw_set11nmac2040(ah, chan);
698
699 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
700 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
701
702 REGWRITE_BUFFER_FLUSH(ah);
703}
704
705
706static int ar5008_hw_process_ini(struct ath_hw *ah,
707 struct ath9k_channel *chan)
708{
709 struct ath_common *common = ath9k_hw_common(ah);
710 int i, regWrites = 0;
711 u32 modesIndex, freqIndex;
712
713 if (IS_CHAN_5GHZ(chan)) {
714 freqIndex = 1;
715 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
716 } else {
717 freqIndex = 2;
718 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
719 }
720
721
722
723
724
725 REG_WRITE(ah, AR_PHY(0), 0x00000007);
726
727
728 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
729 if (ah->eep_ops->set_addac)
730 ah->eep_ops->set_addac(ah, chan);
731
732 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
733 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
734
735 ENABLE_REGWRITE_BUFFER(ah);
736
737 for (i = 0; i < ah->iniModes.ia_rows; i++) {
738 u32 reg = INI_RA(&ah->iniModes, i, 0);
739 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
740
741 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
742 val &= ~AR_AN_TOP2_PWDCLKIND;
743
744 REG_WRITE(ah, reg, val);
745
746 if (reg >= 0x7800 && reg < 0x78a0
747 && ah->config.analog_shiftreg
748 && (common->bus_ops->ath_bus_type != ATH_USB)) {
749 udelay(100);
750 }
751
752 DO_DELAY(regWrites);
753 }
754
755 REGWRITE_BUFFER_FLUSH(ah);
756
757 if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
758 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
759
760 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
761 AR_SREV_9287_11_OR_LATER(ah))
762 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
763
764 if (AR_SREV_9271_10(ah)) {
765 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA);
766 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_ADC_ON, 0xa);
767 }
768
769 ENABLE_REGWRITE_BUFFER(ah);
770
771
772 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
773 u32 reg = INI_RA(&ah->iniCommon, i, 0);
774 u32 val = INI_RA(&ah->iniCommon, i, 1);
775
776 REG_WRITE(ah, reg, val);
777
778 if (reg >= 0x7800 && reg < 0x78a0
779 && ah->config.analog_shiftreg
780 && (common->bus_ops->ath_bus_type != ATH_USB)) {
781 udelay(100);
782 }
783
784 DO_DELAY(regWrites);
785 }
786
787 REGWRITE_BUFFER_FLUSH(ah);
788
789 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
790
791 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
792 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,
793 regWrites);
794
795 ar5008_hw_override_ini(ah, chan);
796 ar5008_hw_set_channel_regs(ah, chan);
797 ar5008_hw_init_chain_masks(ah);
798 ath9k_olc_init(ah);
799 ath9k_hw_apply_txpower(ah, chan, false);
800
801
802 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
803 ath_err(ath9k_hw_common(ah), "ar5416SetRfRegs failed\n");
804 return -EIO;
805 }
806
807 return 0;
808}
809
810static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
811{
812 u32 rfMode = 0;
813
814 if (chan == NULL)
815 return;
816
817 if (IS_CHAN_2GHZ(chan))
818 rfMode |= AR_PHY_MODE_DYNAMIC;
819 else
820 rfMode |= AR_PHY_MODE_OFDM;
821
822 if (!AR_SREV_9280_20_OR_LATER(ah))
823 rfMode |= (IS_CHAN_5GHZ(chan)) ?
824 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
825
826 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
827 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
828
829 REG_WRITE(ah, AR_PHY_MODE, rfMode);
830}
831
832static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
833{
834 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
835}
836
837static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
838 struct ath9k_channel *chan)
839{
840 u32 coef_scaled, ds_coef_exp, ds_coef_man;
841 u32 clockMhzScaled = 0x64000000;
842 struct chan_centers centers;
843
844 if (IS_CHAN_HALF_RATE(chan))
845 clockMhzScaled = clockMhzScaled >> 1;
846 else if (IS_CHAN_QUARTER_RATE(chan))
847 clockMhzScaled = clockMhzScaled >> 2;
848
849 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
850 coef_scaled = clockMhzScaled / centers.synth_center;
851
852 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
853 &ds_coef_exp);
854
855 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
856 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
857 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
858 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
859
860 coef_scaled = (9 * coef_scaled) / 10;
861
862 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
863 &ds_coef_exp);
864
865 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
866 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
867 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
868 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
869}
870
871static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
872{
873 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
874 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
875 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
876}
877
878static void ar5008_hw_rfbus_done(struct ath_hw *ah)
879{
880 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
881
882 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
883
884 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
885}
886
887static void ar5008_restore_chainmask(struct ath_hw *ah)
888{
889 int rx_chainmask = ah->rxchainmask;
890
891 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
892 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
893 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
894 }
895}
896
897static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
898 struct ath9k_channel *chan)
899{
900 u32 pll;
901
902 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
903
904 if (chan && IS_CHAN_HALF_RATE(chan))
905 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
906 else if (chan && IS_CHAN_QUARTER_RATE(chan))
907 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
908
909 if (chan && IS_CHAN_5GHZ(chan))
910 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
911 else
912 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
913
914 return pll;
915}
916
917static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
918 struct ath9k_channel *chan)
919{
920 u32 pll;
921
922 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
923
924 if (chan && IS_CHAN_HALF_RATE(chan))
925 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
926 else if (chan && IS_CHAN_QUARTER_RATE(chan))
927 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
928
929 if (chan && IS_CHAN_5GHZ(chan))
930 pll |= SM(0xa, AR_RTC_PLL_DIV);
931 else
932 pll |= SM(0xb, AR_RTC_PLL_DIV);
933
934 return pll;
935}
936
937static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
938 enum ath9k_ani_cmd cmd,
939 int param)
940{
941 struct ath_common *common = ath9k_hw_common(ah);
942 struct ath9k_channel *chan = ah->curchan;
943 struct ar5416AniState *aniState = &ah->ani;
944 s32 value;
945
946 switch (cmd & ah->ani_function) {
947 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
948
949
950
951
952
953
954
955 u32 on = param ? 1 : 0;
956
957
958
959
960 int m1ThreshLow = on ?
961 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
962 int m2ThreshLow = on ?
963 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
964 int m1Thresh = on ?
965 aniState->iniDef.m1Thresh : m1Thresh_off;
966 int m2Thresh = on ?
967 aniState->iniDef.m2Thresh : m2Thresh_off;
968 int m2CountThr = on ?
969 aniState->iniDef.m2CountThr : m2CountThr_off;
970 int m2CountThrLow = on ?
971 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
972 int m1ThreshLowExt = on ?
973 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
974 int m2ThreshLowExt = on ?
975 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
976 int m1ThreshExt = on ?
977 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
978 int m2ThreshExt = on ?
979 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
980
981 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
982 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
983 m1ThreshLow);
984 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
985 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
986 m2ThreshLow);
987 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
988 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
989 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
990 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
991 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
992 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
993 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
994 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
995 m2CountThrLow);
996
997 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
998 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
999 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1000 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1001 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1002 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1003 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1004 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1005
1006 if (on)
1007 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1008 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1009 else
1010 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1011 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1012
1013 if (on != aniState->ofdmWeakSigDetect) {
1014 ath_dbg(common, ANI,
1015 "** ch %d: ofdm weak signal: %s=>%s\n",
1016 chan->channel,
1017 aniState->ofdmWeakSigDetect ?
1018 "on" : "off",
1019 on ? "on" : "off");
1020 if (on)
1021 ah->stats.ast_ani_ofdmon++;
1022 else
1023 ah->stats.ast_ani_ofdmoff++;
1024 aniState->ofdmWeakSigDetect = on;
1025 }
1026 break;
1027 }
1028 case ATH9K_ANI_FIRSTEP_LEVEL:{
1029 u32 level = param;
1030
1031 value = level * 2;
1032 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1033 AR_PHY_FIND_SIG_FIRSTEP, value);
1034 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1035 AR_PHY_FIND_SIG_FIRSTEP_LOW, value);
1036
1037 if (level != aniState->firstepLevel) {
1038 ath_dbg(common, ANI,
1039 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1040 chan->channel,
1041 aniState->firstepLevel,
1042 level,
1043 ATH9K_ANI_FIRSTEP_LVL,
1044 value,
1045 aniState->iniDef.firstep);
1046 ath_dbg(common, ANI,
1047 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1048 chan->channel,
1049 aniState->firstepLevel,
1050 level,
1051 ATH9K_ANI_FIRSTEP_LVL,
1052 value,
1053 aniState->iniDef.firstepLow);
1054 if (level > aniState->firstepLevel)
1055 ah->stats.ast_ani_stepup++;
1056 else if (level < aniState->firstepLevel)
1057 ah->stats.ast_ani_stepdown++;
1058 aniState->firstepLevel = level;
1059 }
1060 break;
1061 }
1062 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1063 u32 level = param;
1064
1065 value = (level + 1) * 2;
1066 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1067 AR_PHY_TIMING5_CYCPWR_THR1, value);
1068
1069 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1070 AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);
1071
1072 if (level != aniState->spurImmunityLevel) {
1073 ath_dbg(common, ANI,
1074 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1075 chan->channel,
1076 aniState->spurImmunityLevel,
1077 level,
1078 ATH9K_ANI_SPUR_IMMUNE_LVL,
1079 value,
1080 aniState->iniDef.cycpwrThr1);
1081 ath_dbg(common, ANI,
1082 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1083 chan->channel,
1084 aniState->spurImmunityLevel,
1085 level,
1086 ATH9K_ANI_SPUR_IMMUNE_LVL,
1087 value,
1088 aniState->iniDef.cycpwrThr1Ext);
1089 if (level > aniState->spurImmunityLevel)
1090 ah->stats.ast_ani_spurup++;
1091 else if (level < aniState->spurImmunityLevel)
1092 ah->stats.ast_ani_spurdown++;
1093 aniState->spurImmunityLevel = level;
1094 }
1095 break;
1096 }
1097 case ATH9K_ANI_MRC_CCK:
1098
1099
1100
1101
1102 WARN_ON(1);
1103 break;
1104 default:
1105 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1106 return false;
1107 }
1108
1109 ath_dbg(common, ANI,
1110 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1111 aniState->spurImmunityLevel,
1112 aniState->ofdmWeakSigDetect ? "on" : "off",
1113 aniState->firstepLevel,
1114 aniState->mrcCCK ? "on" : "off",
1115 aniState->listenTime,
1116 aniState->ofdmPhyErrCount,
1117 aniState->cckPhyErrCount);
1118 return true;
1119}
1120
1121static void ar5008_hw_do_getnf(struct ath_hw *ah,
1122 int16_t nfarray[NUM_NF_READINGS])
1123{
1124 int16_t nf;
1125
1126 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1127 nfarray[0] = sign_extend32(nf, 8);
1128
1129 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1130 nfarray[1] = sign_extend32(nf, 8);
1131
1132 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1133 nfarray[2] = sign_extend32(nf, 8);
1134
1135 if (!IS_CHAN_HT40(ah->curchan))
1136 return;
1137
1138 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1139 nfarray[3] = sign_extend32(nf, 8);
1140
1141 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1142 nfarray[4] = sign_extend32(nf, 8);
1143
1144 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1145 nfarray[5] = sign_extend32(nf, 8);
1146}
1147
1148
1149
1150
1151
1152
1153static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1154{
1155 struct ath_common *common = ath9k_hw_common(ah);
1156 struct ath9k_channel *chan = ah->curchan;
1157 struct ar5416AniState *aniState = &ah->ani;
1158 struct ath9k_ani_default *iniDef;
1159 u32 val;
1160
1161 iniDef = &aniState->iniDef;
1162
1163 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1164 ah->hw_version.macVersion,
1165 ah->hw_version.macRev,
1166 ah->opmode,
1167 chan->channel);
1168
1169 val = REG_READ(ah, AR_PHY_SFCORR);
1170 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1171 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1172 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1173
1174 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1175 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1176 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1177 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1178
1179 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1180 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1181 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1182 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1183 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1184 iniDef->firstep = REG_READ_FIELD(ah,
1185 AR_PHY_FIND_SIG,
1186 AR_PHY_FIND_SIG_FIRSTEP);
1187 iniDef->firstepLow = REG_READ_FIELD(ah,
1188 AR_PHY_FIND_SIG_LOW,
1189 AR_PHY_FIND_SIG_FIRSTEP_LOW);
1190 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1191 AR_PHY_TIMING5,
1192 AR_PHY_TIMING5_CYCPWR_THR1);
1193 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1194 AR_PHY_EXT_CCA,
1195 AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1196
1197
1198 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1199 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1200 aniState->ofdmWeakSigDetect = true;
1201 aniState->mrcCCK = false;
1202}
1203
1204static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1205{
1206 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1207 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1208 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1209 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1210 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1211 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1212}
1213
1214static void ar5008_hw_set_radar_params(struct ath_hw *ah,
1215 struct ath_hw_radar_conf *conf)
1216{
1217 u32 radar_0 = 0, radar_1;
1218
1219 if (!conf) {
1220 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1221 return;
1222 }
1223
1224 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1225 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1226 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1227 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1228 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1229 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1230
1231 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1232 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1233 AR_PHY_RADAR_1_RELPWR_THRESH);
1234 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1235 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1236 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1237 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1238 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1239
1240 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1241 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1242 if (conf->ext_channel)
1243 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1244 else
1245 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1246}
1247
1248static void ar5008_hw_set_radar_conf(struct ath_hw *ah)
1249{
1250 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1251
1252 conf->fir_power = -33;
1253 conf->radar_rssi = 20;
1254 conf->pulse_height = 10;
1255 conf->pulse_rssi = 15;
1256 conf->pulse_inband = 15;
1257 conf->pulse_maxlen = 255;
1258 conf->pulse_inband_step = 12;
1259 conf->radar_inband = 8;
1260}
1261
1262static void ar5008_hw_init_txpower_cck(struct ath_hw *ah, int16_t *rate_array)
1263{
1264#define CCK_DELTA(x) ((OLC_FOR_AR9280_20_LATER) ? max((x) - 2, 0) : (x))
1265 ah->tx_power[0] = CCK_DELTA(rate_array[rate1l]);
1266 ah->tx_power[1] = CCK_DELTA(min(rate_array[rate2l],
1267 rate_array[rate2s]));
1268 ah->tx_power[2] = CCK_DELTA(min(rate_array[rate5_5l],
1269 rate_array[rate5_5s]));
1270 ah->tx_power[3] = CCK_DELTA(min(rate_array[rate11l],
1271 rate_array[rate11s]));
1272#undef CCK_DELTA
1273}
1274
1275static void ar5008_hw_init_txpower_ofdm(struct ath_hw *ah, int16_t *rate_array,
1276 int offset)
1277{
1278 int i, idx = 0;
1279
1280 for (i = offset; i < offset + AR5008_OFDM_RATES; i++) {
1281 ah->tx_power[i] = rate_array[idx];
1282 idx++;
1283 }
1284}
1285
1286static void ar5008_hw_init_txpower_ht(struct ath_hw *ah, int16_t *rate_array,
1287 int ss_offset, int ds_offset,
1288 bool is_40, int ht40_delta)
1289{
1290 int i, mcs_idx = (is_40) ? AR5008_HT40_SHIFT : AR5008_HT20_SHIFT;
1291
1292 for (i = ss_offset; i < ss_offset + AR5008_HT_SS_RATES; i++) {
1293 ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta;
1294 mcs_idx++;
1295 }
1296 memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset],
1297 AR5008_HT_SS_RATES);
1298}
1299
1300void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1301 struct ath9k_channel *chan, int ht40_delta)
1302{
1303 if (IS_CHAN_5GHZ(chan)) {
1304 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1305 AR5008_11NA_OFDM_SHIFT);
1306 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1307 ar5008_hw_init_txpower_ht(ah, rate_array,
1308 AR5008_11NA_HT_SS_SHIFT,
1309 AR5008_11NA_HT_DS_SHIFT,
1310 IS_CHAN_HT40(chan),
1311 ht40_delta);
1312 }
1313 } else {
1314 ar5008_hw_init_txpower_cck(ah, rate_array);
1315 ar5008_hw_init_txpower_ofdm(ah, rate_array,
1316 AR5008_11NG_OFDM_SHIFT);
1317 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1318 ar5008_hw_init_txpower_ht(ah, rate_array,
1319 AR5008_11NG_HT_SS_SHIFT,
1320 AR5008_11NG_HT_DS_SHIFT,
1321 IS_CHAN_HT40(chan),
1322 ht40_delta);
1323 }
1324 }
1325}
1326
1327int ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1328{
1329 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1330 static const u32 ar5416_cca_regs[6] = {
1331 AR_PHY_CCA,
1332 AR_PHY_CH1_CCA,
1333 AR_PHY_CH2_CCA,
1334 AR_PHY_EXT_CCA,
1335 AR_PHY_CH1_EXT_CCA,
1336 AR_PHY_CH2_EXT_CCA
1337 };
1338 int ret;
1339
1340 ret = ar5008_hw_rf_alloc_ext_banks(ah);
1341 if (ret)
1342 return ret;
1343
1344 priv_ops->rf_set_freq = ar5008_hw_set_channel;
1345 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1346
1347 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1348 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1349 priv_ops->init_bb = ar5008_hw_init_bb;
1350 priv_ops->process_ini = ar5008_hw_process_ini;
1351 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1352 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1353 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1354 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1355 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1356 priv_ops->restore_chainmask = ar5008_restore_chainmask;
1357 priv_ops->do_getnf = ar5008_hw_do_getnf;
1358 priv_ops->set_radar_params = ar5008_hw_set_radar_params;
1359
1360 priv_ops->ani_control = ar5008_hw_ani_control_new;
1361 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1362
1363 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
1364 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1365 else
1366 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1367
1368 ar5008_hw_set_nf_limits(ah);
1369 ar5008_hw_set_radar_conf(ah);
1370 memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1371 return 0;
1372}
1373