1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#ifndef __RTL92D_DEF_H__
27#define __RTL92D_DEF_H__
28
29
30#define MAX_MSS_DENSITY_2T 0x13
31#define MAX_MSS_DENSITY_1T 0x0A
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_PATH 2
35
36#define PHY_RSSI_SLID_WIN_MAX 100
37#define PHY_LINKQUALITY_SLID_WIN_MAX 20
38#define PHY_BEACON_RSSI_SLID_WIN_MAX 10
39
40#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
41
42#define RX_SMOOTH_FACTOR 20
43
44#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
45#define HAL_PRIME_CHNL_OFFSET_LOWER 1
46#define HAL_PRIME_CHNL_OFFSET_UPPER 2
47
48#define RX_MPDU_QUEUE 0
49#define RX_CMD_QUEUE 1
50
51#define C2H_RX_CMD_HDR_LEN 8
52#define GET_C2H_CMD_CMD_LEN(__prxhdr) \
53 LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
54#define GET_C2H_CMD_ELEMENT_ID(__prxhdr) \
55 LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
56#define GET_C2H_CMD_CMD_SEQ(__prxhdr) \
57 LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
58#define GET_C2H_CMD_CONTINUE(__prxhdr) \
59 LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
60#define GET_C2H_CMD_CONTENT(__prxhdr) \
61 ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
62
63#define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr) \
64 LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
65#define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr) \
66 LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
67#define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr) \
68 LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
69#define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr) \
70 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
71#define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr) \
72 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
73#define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
74 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
75#define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr) \
76 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
77#define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr) \
78 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
79#define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr) \
80 LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
81
82enum version_8192d {
83 VERSION_TEST_CHIP_88C = 0x0000,
84 VERSION_TEST_CHIP_92C = 0x0020,
85 VERSION_TEST_UMC_CHIP_8723 = 0x0081,
86 VERSION_NORMAL_TSMC_CHIP_88C = 0x0008,
87 VERSION_NORMAL_TSMC_CHIP_92C = 0x0028,
88 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018,
89 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088,
90 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8,
91 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098,
92 VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089,
93 VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089,
94 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088,
95 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8,
96 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090,
97 VERSION_TEST_CHIP_92D_SINGLEPHY = 0x0022,
98 VERSION_TEST_CHIP_92D_DUALPHY = 0x0002,
99 VERSION_NORMAL_CHIP_92D_SINGLEPHY = 0x002a,
100 VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a,
101 VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a,
102 VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a,
103 VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a,
104 VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a,
105 VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a,
106 VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a,
107};
108
109
110#define CHIP_92D_SINGLEPHY BIT(9)
111
112
113#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
114#define CHIP_BONDING_92C_1T2R 0x1
115#define CHIP_BONDING_88C_USB_MCARD 0x2
116#define CHIP_BONDING_88C_USB_HP 0x1
117
118
119
120
121
122
123#define CHIP_8723 BIT(0)
124#define CHIP_92D BIT(1)
125#define NORMAL_CHIP BIT(3)
126#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6)))
127#define RF_TYPE_1T2R BIT(4)
128#define RF_TYPE_2T2R BIT(5)
129#define CHIP_VENDOR_UMC BIT(7)
130#define CHIP_92D_B_CUT BIT(12)
131#define CHIP_92D_C_CUT BIT(13)
132#define CHIP_92D_D_CUT (BIT(13)|BIT(12))
133#define CHIP_92D_E_CUT BIT(14)
134
135
136#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2))
137#define CHIP_TYPE_MASK BIT(3)
138#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6))
139#define MANUFACTUER_MASK BIT(7)
140#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8))
141#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12))
142
143
144
145#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK)
146#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK)
147#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK)
148#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK)
149#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK)
150#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK)
151
152#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version)) ? \
153 false : true)
154#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == \
155 RF_TYPE_1T2R) ? true : false)
156#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == \
157 RF_TYPE_2T2R) ? true : false)
158
159#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? \
160 (IS_2T2R(version) ? true : false) : false)
161#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == \
162 CHIP_92D) ? true : false)
163#define IS_92D_C_CUT(version) ((IS_92D(version)) ? \
164 ((GET_CVID_CUT_VERSION(version) == \
165 CHIP_92D_C_CUT) ? true : false) : false)
166#define IS_92D_D_CUT(version) ((IS_92D(version)) ? \
167 ((GET_CVID_CUT_VERSION(version) == \
168 CHIP_92D_D_CUT) ? true : false) : false)
169#define IS_92D_E_CUT(version) ((IS_92D(version)) ? \
170 ((GET_CVID_CUT_VERSION(version) == \
171 CHIP_92D_E_CUT) ? true : false) : false)
172
173enum rf_optype {
174 RF_OP_BY_SW_3WIRE = 0,
175 RF_OP_BY_FW,
176 RF_OP_MAX
177};
178
179enum rtl_desc_qsel {
180 QSLT_BK = 0x2,
181 QSLT_BE = 0x0,
182 QSLT_VI = 0x5,
183 QSLT_VO = 0x7,
184 QSLT_BEACON = 0x10,
185 QSLT_HIGH = 0x11,
186 QSLT_MGNT = 0x12,
187 QSLT_CMD = 0x13,
188};
189
190enum channel_plan {
191 CHPL_FCC = 0,
192 CHPL_IC = 1,
193 CHPL_ETSI = 2,
194 CHPL_SPAIN = 3,
195 CHPL_FRANCE = 4,
196 CHPL_MKK = 5,
197 CHPL_MKK1 = 6,
198 CHPL_ISRAEL = 7,
199 CHPL_TELEC = 8,
200 CHPL_GLOBAL = 9,
201 CHPL_WORLD = 10,
202};
203
204struct phy_sts_cck_8192d {
205 u8 adc_pwdb_X[4];
206 u8 sq_rpt;
207 u8 cck_agc_rpt;
208};
209
210struct h2c_cmd_8192c {
211 u8 element_id;
212 u32 cmd_len;
213 u8 *p_cmdbuffer;
214};
215
216struct txpower_info {
217 u8 cck_index[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
218 u8 ht40_1sindex[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
219 u8 ht40_2sindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
220 u8 ht20indexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
221 u8 ofdmindexdiff[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
222 u8 ht40maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
223 u8 ht20maxoffset[RF6052_MAX_PATH][CHANNEL_GROUP_MAX];
224 u8 tssi_a[3];
225 u8 tssi_b[3];
226};
227
228#endif
229
