LXR linux/drivers/rtc/rtc-stm32.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) STMicroelectronics 2017
   4 * Author:  Amelie Delaunay <amelie.delaunay@st.com>
   5 */
   6
   7#include <linux/bcd.h>
   8#include <linux/clk.h>
   9#include <linux/iopoll.h>
  10#include <linux/ioport.h>
  11#include <linux/mfd/syscon.h>
  12#include <linux/module.h>
  13#include <linux/of_device.h>
  14#include <linux/pm_wakeirq.h>
  15#include <linux/regmap.h>
  16#include <linux/rtc.h>
  17
  18#define DRIVER_NAME "stm32_rtc"
  19
  20/* STM32_RTC_TR bit fields  */
  21#define STM32_RTC_TR_SEC_SHIFT          0
  22#define STM32_RTC_TR_SEC                GENMASK(6, 0)
  23#define STM32_RTC_TR_MIN_SHIFT          8
  24#define STM32_RTC_TR_MIN                GENMASK(14, 8)
  25#define STM32_RTC_TR_HOUR_SHIFT         16
  26#define STM32_RTC_TR_HOUR               GENMASK(21, 16)
  27
  28/* STM32_RTC_DR bit fields */
  29#define STM32_RTC_DR_DATE_SHIFT         0
  30#define STM32_RTC_DR_DATE               GENMASK(5, 0)
  31#define STM32_RTC_DR_MONTH_SHIFT        8
  32#define STM32_RTC_DR_MONTH              GENMASK(12, 8)
  33#define STM32_RTC_DR_WDAY_SHIFT         13
  34#define STM32_RTC_DR_WDAY               GENMASK(15, 13)
  35#define STM32_RTC_DR_YEAR_SHIFT         16
  36#define STM32_RTC_DR_YEAR               GENMASK(23, 16)
  37
  38/* STM32_RTC_CR bit fields */
  39#define STM32_RTC_CR_FMT                BIT(6)
  40#define STM32_RTC_CR_ALRAE              BIT(8)
  41#define STM32_RTC_CR_ALRAIE             BIT(12)
  42
  43/* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */
  44#define STM32_RTC_ISR_ALRAWF            BIT(0)
  45#define STM32_RTC_ISR_INITS             BIT(4)
  46#define STM32_RTC_ISR_RSF               BIT(5)
  47#define STM32_RTC_ISR_INITF             BIT(6)
  48#define STM32_RTC_ISR_INIT              BIT(7)
  49#define STM32_RTC_ISR_ALRAF             BIT(8)
  50
  51/* STM32_RTC_PRER bit fields */
  52#define STM32_RTC_PRER_PRED_S_SHIFT     0
  53#define STM32_RTC_PRER_PRED_S           GENMASK(14, 0)
  54#define STM32_RTC_PRER_PRED_A_SHIFT     16
  55#define STM32_RTC_PRER_PRED_A           GENMASK(22, 16)
  56
  57/* STM32_RTC_ALRMAR and STM32_RTC_ALRMBR bit fields */
  58#define STM32_RTC_ALRMXR_SEC_SHIFT      0
  59#define STM32_RTC_ALRMXR_SEC            GENMASK(6, 0)
  60#define STM32_RTC_ALRMXR_SEC_MASK       BIT(7)
  61#define STM32_RTC_ALRMXR_MIN_SHIFT      8
  62#define STM32_RTC_ALRMXR_MIN            GENMASK(14, 8)
  63#define STM32_RTC_ALRMXR_MIN_MASK       BIT(15)
  64#define STM32_RTC_ALRMXR_HOUR_SHIFT     16
  65#define STM32_RTC_ALRMXR_HOUR           GENMASK(21, 16)
  66#define STM32_RTC_ALRMXR_PM             BIT(22)
  67#define STM32_RTC_ALRMXR_HOUR_MASK      BIT(23)
  68#define STM32_RTC_ALRMXR_DATE_SHIFT     24
  69#define STM32_RTC_ALRMXR_DATE           GENMASK(29, 24)
  70#define STM32_RTC_ALRMXR_WDSEL          BIT(30)
  71#define STM32_RTC_ALRMXR_WDAY_SHIFT     24
  72#define STM32_RTC_ALRMXR_WDAY           GENMASK(27, 24)
  73#define STM32_RTC_ALRMXR_DATE_MASK      BIT(31)
  74
  75/* STM32_RTC_SR/_SCR bit fields */
  76#define STM32_RTC_SR_ALRA               BIT(0)
  77
  78/* STM32_RTC_VERR bit fields */
  79#define STM32_RTC_VERR_MINREV_SHIFT     0
  80#define STM32_RTC_VERR_MINREV           GENMASK(3, 0)
  81#define STM32_RTC_VERR_MAJREV_SHIFT     4
  82#define STM32_RTC_VERR_MAJREV           GENMASK(7, 4)
  83
  84/* STM32_RTC_WPR key constants */
  85#define RTC_WPR_1ST_KEY                 0xCA
  86#define RTC_WPR_2ND_KEY                 0x53
  87#define RTC_WPR_WRONG_KEY               0xFF
  88
  89/* Max STM32 RTC register offset is 0x3FC */
  90#define UNDEF_REG                       0xFFFF
  91
  92struct stm32_rtc;
  93
  94struct stm32_rtc_registers {
  95        u16 tr;
  96        u16 dr;
  97        u16 cr;
  98        u16 isr;
  99        u16 prer;
 100        u16 alrmar;
 101        u16 wpr;
 102        u16 sr;
 103        u16 scr;
 104        u16 verr;
 105};
 106
 107struct stm32_rtc_events {
 108        u32 alra;
 109};
 110
 111struct stm32_rtc_data {
 112        const struct stm32_rtc_registers regs;
 113        const struct stm32_rtc_events events;
 114        void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
 115        bool has_pclk;
 116        bool need_dbp;
 117        bool has_wakeirq;
 118};
 119
 120struct stm32_rtc {
 121        struct rtc_device *rtc_dev;
 122        void __iomem *base;
 123        struct regmap *dbp;
 124        unsigned int dbp_reg;
 125        unsigned int dbp_mask;
 126        struct clk *pclk;
 127        struct clk *rtc_ck;
 128        const struct stm32_rtc_data *data;
 129        int irq_alarm;
 130        int wakeirq_alarm;
 131};
 132
 133static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
 134{
 135        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 136
 137        writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
 138        writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
 139}
 140
 141static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
 142{
 143        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 144
 145        writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
 146}
 147
 148static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
 149{
 150        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 151        unsigned int isr = readl_relaxed(rtc->base + regs->isr);
 152
 153        if (!(isr & STM32_RTC_ISR_INITF)) {
 154                isr |= STM32_RTC_ISR_INIT;
 155                writel_relaxed(isr, rtc->base + regs->isr);
 156
 157                /*
 158                 * It takes around 2 rtc_ck clock cycles to enter in
 159                 * initialization phase mode (and have INITF flag set). As
 160                 * slowest rtc_ck frequency may be 32kHz and highest should be
 161                 * 1MHz, we poll every 10 us with a timeout of 100ms.
 162                 */
 163                return readl_relaxed_poll_timeout_atomic(
 164                                        rtc->base + regs->isr,
 165                                        isr, (isr & STM32_RTC_ISR_INITF),
 166                                        10, 100000);
 167        }
 168
 169        return 0;
 170}
 171
 172static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
 173{
 174        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 175        unsigned int isr = readl_relaxed(rtc->base + regs->isr);
 176
 177        isr &= ~STM32_RTC_ISR_INIT;
 178        writel_relaxed(isr, rtc->base + regs->isr);
 179}
 180
 181static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
 182{
 183        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 184        unsigned int isr = readl_relaxed(rtc->base + regs->isr);
 185
 186        isr &= ~STM32_RTC_ISR_RSF;
 187        writel_relaxed(isr, rtc->base + regs->isr);
 188
 189        /*
 190         * Wait for RSF to be set to ensure the calendar registers are
 191         * synchronised, it takes around 2 rtc_ck clock cycles
 192         */
 193        return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
 194                                                 isr,
 195                                                 (isr & STM32_RTC_ISR_RSF),
 196                                                 10, 100000);
 197}
 198
 199static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
 200                                        unsigned int flags)
 201{
 202        rtc->data->clear_events(rtc, flags);
 203}
 204
 205static irqreturn_t stm32_rtc_alarm_irq(int irq, void *dev_id)
 206{
 207        struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
 208        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 209        const struct stm32_rtc_events *evts = &rtc->data->events;
 210        unsigned int status, cr;
 211
 212        mutex_lock(&rtc->rtc_dev->ops_lock);
 213
 214        status = readl_relaxed(rtc->base + regs->sr);
 215        cr = readl_relaxed(rtc->base + regs->cr);
 216
 217        if ((status & evts->alra) &&
 218            (cr & STM32_RTC_CR_ALRAIE)) {
 219                /* Alarm A flag - Alarm interrupt */
 220                dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
 221
 222                /* Pass event to the kernel */
 223                rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
 224
 225                /* Clear event flags, otherwise new events won't be received */
 226                stm32_rtc_clear_event_flags(rtc, evts->alra);
 227        }
 228
 229        mutex_unlock(&rtc->rtc_dev->ops_lock);
 230
 231        return IRQ_HANDLED;
 232}
 233
 234/* Convert rtc_time structure from bin to bcd format */
 235static void tm2bcd(struct rtc_time *tm)
 236{
 237        tm->tm_sec = bin2bcd(tm->tm_sec);
 238        tm->tm_min = bin2bcd(tm->tm_min);
 239        tm->tm_hour = bin2bcd(tm->tm_hour);
 240
 241        tm->tm_mday = bin2bcd(tm->tm_mday);
 242        tm->tm_mon = bin2bcd(tm->tm_mon + 1);
 243        tm->tm_year = bin2bcd(tm->tm_year - 100);
 244        /*
 245         * Number of days since Sunday
 246         * - on kernel side, 0=Sunday...6=Saturday
 247         * - on rtc side, 0=invalid,1=Monday...7=Sunday
 248         */
 249        tm->tm_wday = (!tm->tm_wday) ? 7 : tm->tm_wday;
 250}
 251
 252/* Convert rtc_time structure from bcd to bin format */
 253static void bcd2tm(struct rtc_time *tm)
 254{
 255        tm->tm_sec = bcd2bin(tm->tm_sec);
 256        tm->tm_min = bcd2bin(tm->tm_min);
 257        tm->tm_hour = bcd2bin(tm->tm_hour);
 258
 259        tm->tm_mday = bcd2bin(tm->tm_mday);
 260        tm->tm_mon = bcd2bin(tm->tm_mon) - 1;
 261        tm->tm_year = bcd2bin(tm->tm_year) + 100;
 262        /*
 263         * Number of days since Sunday
 264         * - on kernel side, 0=Sunday...6=Saturday
 265         * - on rtc side, 0=invalid,1=Monday...7=Sunday
 266         */
 267        tm->tm_wday %= 7;
 268}
 269
 270static int stm32_rtc_read_time(struct device *dev, struct rtc_time *tm)
 271{
 272        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 273        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 274        unsigned int tr, dr;
 275
 276        /* Time and Date in BCD format */
 277        tr = readl_relaxed(rtc->base + regs->tr);
 278        dr = readl_relaxed(rtc->base + regs->dr);
 279
 280        tm->tm_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
 281        tm->tm_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
 282        tm->tm_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
 283
 284        tm->tm_mday = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
 285        tm->tm_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
 286        tm->tm_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
 287        tm->tm_wday = (dr & STM32_RTC_DR_WDAY) >> STM32_RTC_DR_WDAY_SHIFT;
 288
 289        /* We don't report tm_yday and tm_isdst */
 290
 291        bcd2tm(tm);
 292
 293        return 0;
 294}
 295
 296static int stm32_rtc_set_time(struct device *dev, struct rtc_time *tm)
 297{
 298        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 299        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 300        unsigned int tr, dr;
 301        int ret = 0;
 302
 303        tm2bcd(tm);
 304
 305        /* Time in BCD format */
 306        tr = ((tm->tm_sec << STM32_RTC_TR_SEC_SHIFT) & STM32_RTC_TR_SEC) |
 307             ((tm->tm_min << STM32_RTC_TR_MIN_SHIFT) & STM32_RTC_TR_MIN) |
 308             ((tm->tm_hour << STM32_RTC_TR_HOUR_SHIFT) & STM32_RTC_TR_HOUR);
 309
 310        /* Date in BCD format */
 311        dr = ((tm->tm_mday << STM32_RTC_DR_DATE_SHIFT) & STM32_RTC_DR_DATE) |
 312             ((tm->tm_mon << STM32_RTC_DR_MONTH_SHIFT) & STM32_RTC_DR_MONTH) |
 313             ((tm->tm_year << STM32_RTC_DR_YEAR_SHIFT) & STM32_RTC_DR_YEAR) |
 314             ((tm->tm_wday << STM32_RTC_DR_WDAY_SHIFT) & STM32_RTC_DR_WDAY);
 315
 316        stm32_rtc_wpr_unlock(rtc);
 317
 318        ret = stm32_rtc_enter_init_mode(rtc);
 319        if (ret) {
 320                dev_err(dev, "Can't enter in init mode. Set time aborted.\n");
 321                goto end;
 322        }
 323
 324        writel_relaxed(tr, rtc->base + regs->tr);
 325        writel_relaxed(dr, rtc->base + regs->dr);
 326
 327        stm32_rtc_exit_init_mode(rtc);
 328
 329        ret = stm32_rtc_wait_sync(rtc);
 330end:
 331        stm32_rtc_wpr_lock(rtc);
 332
 333        return ret;
 334}
 335
 336static int stm32_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 337{
 338        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 339        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 340        const struct stm32_rtc_events *evts = &rtc->data->events;
 341        struct rtc_time *tm = &alrm->time;
 342        unsigned int alrmar, cr, status;
 343
 344        alrmar = readl_relaxed(rtc->base + regs->alrmar);
 345        cr = readl_relaxed(rtc->base + regs->cr);
 346        status = readl_relaxed(rtc->base + regs->sr);
 347
 348        if (alrmar & STM32_RTC_ALRMXR_DATE_MASK) {
 349                /*
 350                 * Date/day doesn't matter in Alarm comparison so alarm
 351                 * triggers every day
 352                 */
 353                tm->tm_mday = -1;
 354                tm->tm_wday = -1;
 355        } else {
 356                if (alrmar & STM32_RTC_ALRMXR_WDSEL) {
 357                        /* Alarm is set to a day of week */
 358                        tm->tm_mday = -1;
 359                        tm->tm_wday = (alrmar & STM32_RTC_ALRMXR_WDAY) >>
 360                                      STM32_RTC_ALRMXR_WDAY_SHIFT;
 361                        tm->tm_wday %= 7;
 362                } else {
 363                        /* Alarm is set to a day of month */
 364                        tm->tm_wday = -1;
 365                        tm->tm_mday = (alrmar & STM32_RTC_ALRMXR_DATE) >>
 366                                       STM32_RTC_ALRMXR_DATE_SHIFT;
 367                }
 368        }
 369
 370        if (alrmar & STM32_RTC_ALRMXR_HOUR_MASK) {
 371                /* Hours don't matter in Alarm comparison */
 372                tm->tm_hour = -1;
 373        } else {
 374                tm->tm_hour = (alrmar & STM32_RTC_ALRMXR_HOUR) >>
 375                               STM32_RTC_ALRMXR_HOUR_SHIFT;
 376                if (alrmar & STM32_RTC_ALRMXR_PM)
 377                        tm->tm_hour += 12;
 378        }
 379
 380        if (alrmar & STM32_RTC_ALRMXR_MIN_MASK) {
 381                /* Minutes don't matter in Alarm comparison */
 382                tm->tm_min = -1;
 383        } else {
 384                tm->tm_min = (alrmar & STM32_RTC_ALRMXR_MIN) >>
 385                              STM32_RTC_ALRMXR_MIN_SHIFT;
 386        }
 387
 388        if (alrmar & STM32_RTC_ALRMXR_SEC_MASK) {
 389                /* Seconds don't matter in Alarm comparison */
 390                tm->tm_sec = -1;
 391        } else {
 392                tm->tm_sec = (alrmar & STM32_RTC_ALRMXR_SEC) >>
 393                              STM32_RTC_ALRMXR_SEC_SHIFT;
 394        }
 395
 396        bcd2tm(tm);
 397
 398        alrm->enabled = (cr & STM32_RTC_CR_ALRAE) ? 1 : 0;
 399        alrm->pending = (status & evts->alra) ? 1 : 0;
 400
 401        return 0;
 402}
 403
 404static int stm32_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 405{
 406        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 407        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 408        const struct stm32_rtc_events *evts = &rtc->data->events;
 409        unsigned int cr;
 410
 411        cr = readl_relaxed(rtc->base + regs->cr);
 412
 413        stm32_rtc_wpr_unlock(rtc);
 414
 415        /* We expose Alarm A to the kernel */
 416        if (enabled)
 417                cr |= (STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
 418        else
 419                cr &= ~(STM32_RTC_CR_ALRAIE | STM32_RTC_CR_ALRAE);
 420        writel_relaxed(cr, rtc->base + regs->cr);
 421
 422        /* Clear event flags, otherwise new events won't be received */
 423        stm32_rtc_clear_event_flags(rtc, evts->alra);
 424
 425        stm32_rtc_wpr_lock(rtc);
 426
 427        return 0;
 428}
 429
 430static int stm32_rtc_valid_alrm(struct stm32_rtc *rtc, struct rtc_time *tm)
 431{
 432        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 433        int cur_day, cur_mon, cur_year, cur_hour, cur_min, cur_sec;
 434        unsigned int dr = readl_relaxed(rtc->base + regs->dr);
 435        unsigned int tr = readl_relaxed(rtc->base + regs->tr);
 436
 437        cur_day = (dr & STM32_RTC_DR_DATE) >> STM32_RTC_DR_DATE_SHIFT;
 438        cur_mon = (dr & STM32_RTC_DR_MONTH) >> STM32_RTC_DR_MONTH_SHIFT;
 439        cur_year = (dr & STM32_RTC_DR_YEAR) >> STM32_RTC_DR_YEAR_SHIFT;
 440        cur_sec = (tr & STM32_RTC_TR_SEC) >> STM32_RTC_TR_SEC_SHIFT;
 441        cur_min = (tr & STM32_RTC_TR_MIN) >> STM32_RTC_TR_MIN_SHIFT;
 442        cur_hour = (tr & STM32_RTC_TR_HOUR) >> STM32_RTC_TR_HOUR_SHIFT;
 443
 444        /*
 445         * Assuming current date is M-D-Y H:M:S.
 446         * RTC alarm can't be set on a specific month and year.
 447         * So the valid alarm range is:
 448         *      M-D-Y H:M:S < alarm <= (M+1)-D-Y H:M:S
 449         * with a specific case for December...
 450         */
 451        if ((((tm->tm_year > cur_year) &&
 452              (tm->tm_mon == 0x1) && (cur_mon == 0x12)) ||
 453             ((tm->tm_year == cur_year) &&
 454              (tm->tm_mon <= cur_mon + 1))) &&
 455            ((tm->tm_mday > cur_day) ||
 456             ((tm->tm_mday == cur_day) &&
 457             ((tm->tm_hour > cur_hour) ||
 458              ((tm->tm_hour == cur_hour) && (tm->tm_min > cur_min)) ||
 459              ((tm->tm_hour == cur_hour) && (tm->tm_min == cur_min) &&
 460               (tm->tm_sec >= cur_sec))))))
 461                return 0;
 462
 463        return -EINVAL;
 464}
 465
 466static int stm32_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 467{
 468        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 469        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 470        struct rtc_time *tm = &alrm->time;
 471        unsigned int cr, isr, alrmar;
 472        int ret = 0;
 473
 474        tm2bcd(tm);
 475
 476        /*
 477         * RTC alarm can't be set on a specific date, unless this date is
 478         * up to the same day of month next month.
 479         */
 480        if (stm32_rtc_valid_alrm(rtc, tm) < 0) {
 481                dev_err(dev, "Alarm can be set only on upcoming month.\n");
 482                return -EINVAL;
 483        }
 484
 485        alrmar = 0;
 486        /* tm_year and tm_mon are not used because not supported by RTC */
 487        alrmar |= (tm->tm_mday << STM32_RTC_ALRMXR_DATE_SHIFT) &
 488                  STM32_RTC_ALRMXR_DATE;
 489        /* 24-hour format */
 490        alrmar &= ~STM32_RTC_ALRMXR_PM;
 491        alrmar |= (tm->tm_hour << STM32_RTC_ALRMXR_HOUR_SHIFT) &
 492                  STM32_RTC_ALRMXR_HOUR;
 493        alrmar |= (tm->tm_min << STM32_RTC_ALRMXR_MIN_SHIFT) &
 494                  STM32_RTC_ALRMXR_MIN;
 495        alrmar |= (tm->tm_sec << STM32_RTC_ALRMXR_SEC_SHIFT) &
 496                  STM32_RTC_ALRMXR_SEC;
 497
 498        stm32_rtc_wpr_unlock(rtc);
 499
 500        /* Disable Alarm */
 501        cr = readl_relaxed(rtc->base + regs->cr);
 502        cr &= ~STM32_RTC_CR_ALRAE;
 503        writel_relaxed(cr, rtc->base + regs->cr);
 504
 505        /*
 506         * Poll Alarm write flag to be sure that Alarm update is allowed: it
 507         * takes around 2 rtc_ck clock cycles
 508         */
 509        ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
 510                                                isr,
 511                                                (isr & STM32_RTC_ISR_ALRAWF),
 512                                                10, 100000);
 513
 514        if (ret) {
 515                dev_err(dev, "Alarm update not allowed\n");
 516                goto end;
 517        }
 518
 519        /* Write to Alarm register */
 520        writel_relaxed(alrmar, rtc->base + regs->alrmar);
 521
 522        if (alrm->enabled)
 523                stm32_rtc_alarm_irq_enable(dev, 1);
 524        else
 525                stm32_rtc_alarm_irq_enable(dev, 0);
 526
 527end:
 528        stm32_rtc_wpr_lock(rtc);
 529
 530        return ret;
 531}
 532
 533static const struct rtc_class_ops stm32_rtc_ops = {
 534        .read_time      = stm32_rtc_read_time,
 535        .set_time       = stm32_rtc_set_time,
 536        .read_alarm     = stm32_rtc_read_alarm,
 537        .set_alarm      = stm32_rtc_set_alarm,
 538        .alarm_irq_enable = stm32_rtc_alarm_irq_enable,
 539};
 540
 541static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
 542                                   unsigned int flags)
 543{
 544        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 545
 546        /* Flags are cleared by writing 0 in RTC_ISR */
 547        writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
 548                       rtc->base + regs->isr);
 549}
 550
 551static const struct stm32_rtc_data stm32_rtc_data = {
 552        .has_pclk = false,
 553        .need_dbp = true,
 554        .has_wakeirq = false,
 555        .regs = {
 556                .tr = 0x00,
 557                .dr = 0x04,
 558                .cr = 0x08,
 559                .isr = 0x0C,
 560                .prer = 0x10,
 561                .alrmar = 0x1C,
 562                .wpr = 0x24,
 563                .sr = 0x0C, /* set to ISR offset to ease alarm management */
 564                .scr = UNDEF_REG,
 565                .verr = UNDEF_REG,
 566        },
 567        .events = {
 568                .alra = STM32_RTC_ISR_ALRAF,
 569        },
 570        .clear_events = stm32_rtc_clear_events,
 571};
 572
 573static const struct stm32_rtc_data stm32h7_rtc_data = {
 574        .has_pclk = true,
 575        .need_dbp = true,
 576        .has_wakeirq = false,
 577        .regs = {
 578                .tr = 0x00,
 579                .dr = 0x04,
 580                .cr = 0x08,
 581                .isr = 0x0C,
 582                .prer = 0x10,
 583                .alrmar = 0x1C,
 584                .wpr = 0x24,
 585                .sr = 0x0C, /* set to ISR offset to ease alarm management */
 586                .scr = UNDEF_REG,
 587                .verr = UNDEF_REG,
 588        },
 589        .events = {
 590                .alra = STM32_RTC_ISR_ALRAF,
 591        },
 592        .clear_events = stm32_rtc_clear_events,
 593};
 594
 595static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
 596                                      unsigned int flags)
 597{
 598        struct stm32_rtc_registers regs = rtc->data->regs;
 599
 600        /* Flags are cleared by writing 1 in RTC_SCR */
 601        writel_relaxed(flags, rtc->base + regs.scr);
 602}
 603
 604static const struct stm32_rtc_data stm32mp1_data = {
 605        .has_pclk = true,
 606        .need_dbp = false,
 607        .has_wakeirq = true,
 608        .regs = {
 609                .tr = 0x00,
 610                .dr = 0x04,
 611                .cr = 0x18,
 612                .isr = 0x0C, /* named RTC_ICSR on stm32mp1 */
 613                .prer = 0x10,
 614                .alrmar = 0x40,
 615                .wpr = 0x24,
 616                .sr = 0x50,
 617                .scr = 0x5C,
 618                .verr = 0x3F4,
 619        },
 620        .events = {
 621                .alra = STM32_RTC_SR_ALRA,
 622        },
 623        .clear_events = stm32mp1_rtc_clear_events,
 624};
 625
 626static const struct of_device_id stm32_rtc_of_match[] = {
 627        { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
 628        { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
 629        { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
 630        {}
 631};
 632MODULE_DEVICE_TABLE(of, stm32_rtc_of_match);
 633
 634static int stm32_rtc_init(struct platform_device *pdev,
 635                          struct stm32_rtc *rtc)
 636{
 637        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 638        unsigned int prer, pred_a, pred_s, pred_a_max, pred_s_max, cr;
 639        unsigned int rate;
 640        int ret = 0;
 641
 642        rate = clk_get_rate(rtc->rtc_ck);
 643
 644        /* Find prediv_a and prediv_s to obtain the 1Hz calendar clock */
 645        pred_a_max = STM32_RTC_PRER_PRED_A >> STM32_RTC_PRER_PRED_A_SHIFT;
 646        pred_s_max = STM32_RTC_PRER_PRED_S >> STM32_RTC_PRER_PRED_S_SHIFT;
 647
 648        for (pred_a = pred_a_max; pred_a + 1 > 0; pred_a--) {
 649                pred_s = (rate / (pred_a + 1)) - 1;
 650
 651                if (((pred_s + 1) * (pred_a + 1)) == rate)
 652                        break;
 653        }
 654
 655        /*
 656         * Can't find a 1Hz, so give priority to RTC power consumption
 657         * by choosing the higher possible value for prediv_a
 658         */
 659        if ((pred_s > pred_s_max) || (pred_a > pred_a_max)) {
 660                pred_a = pred_a_max;
 661                pred_s = (rate / (pred_a + 1)) - 1;
 662
 663                dev_warn(&pdev->dev, "rtc_ck is %s\n",
 664                         (rate < ((pred_a + 1) * (pred_s + 1))) ?
 665                         "fast" : "slow");
 666        }
 667
 668        stm32_rtc_wpr_unlock(rtc);
 669
 670        ret = stm32_rtc_enter_init_mode(rtc);
 671        if (ret) {
 672                dev_err(&pdev->dev,
 673                        "Can't enter in init mode. Prescaler config failed.\n");
 674                goto end;
 675        }
 676
 677        prer = (pred_s << STM32_RTC_PRER_PRED_S_SHIFT) & STM32_RTC_PRER_PRED_S;
 678        writel_relaxed(prer, rtc->base + regs->prer);
 679        prer |= (pred_a << STM32_RTC_PRER_PRED_A_SHIFT) & STM32_RTC_PRER_PRED_A;
 680        writel_relaxed(prer, rtc->base + regs->prer);
 681
 682        /* Force 24h time format */
 683        cr = readl_relaxed(rtc->base + regs->cr);
 684        cr &= ~STM32_RTC_CR_FMT;
 685        writel_relaxed(cr, rtc->base + regs->cr);
 686
 687        stm32_rtc_exit_init_mode(rtc);
 688
 689        ret = stm32_rtc_wait_sync(rtc);
 690end:
 691        stm32_rtc_wpr_lock(rtc);
 692
 693        return ret;
 694}
 695
 696static int stm32_rtc_probe(struct platform_device *pdev)
 697{
 698        struct stm32_rtc *rtc;
 699        const struct stm32_rtc_registers *regs;
 700        struct resource *res;
 701        int ret;
 702
 703        rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 704        if (!rtc)
 705                return -ENOMEM;
 706
 707        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 708        rtc->base = devm_ioremap_resource(&pdev->dev, res);
 709        if (IS_ERR(rtc->base))
 710                return PTR_ERR(rtc->base);
 711
 712        rtc->data = (struct stm32_rtc_data *)
 713                    of_device_get_match_data(&pdev->dev);
 714        regs = &rtc->data->regs;
 715
 716        if (rtc->data->need_dbp) {
 717                rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
 718                                                           "st,syscfg");
 719                if (IS_ERR(rtc->dbp)) {
 720                        dev_err(&pdev->dev, "no st,syscfg\n");
 721                        return PTR_ERR(rtc->dbp);
 722                }
 723
 724                ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
 725                                                 1, &rtc->dbp_reg);
 726                if (ret) {
 727                        dev_err(&pdev->dev, "can't read DBP register offset\n");
 728                        return ret;
 729                }
 730
 731                ret = of_property_read_u32_index(pdev->dev.of_node, "st,syscfg",
 732                                                 2, &rtc->dbp_mask);
 733                if (ret) {
 734                        dev_err(&pdev->dev, "can't read DBP register mask\n");
 735                        return ret;
 736                }
 737        }
 738
 739        if (!rtc->data->has_pclk) {
 740                rtc->pclk = NULL;
 741                rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
 742        } else {
 743                rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
 744                if (IS_ERR(rtc->pclk)) {
 745                        dev_err(&pdev->dev, "no pclk clock");
 746                        return PTR_ERR(rtc->pclk);
 747                }
 748                rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
 749        }
 750        if (IS_ERR(rtc->rtc_ck)) {
 751                dev_err(&pdev->dev, "no rtc_ck clock");
 752                return PTR_ERR(rtc->rtc_ck);
 753        }
 754
 755        if (rtc->data->has_pclk) {
 756                ret = clk_prepare_enable(rtc->pclk);
 757                if (ret)
 758                        return ret;
 759        }
 760
 761        ret = clk_prepare_enable(rtc->rtc_ck);
 762        if (ret)
 763                goto err;
 764
 765        if (rtc->data->need_dbp)
 766                regmap_update_bits(rtc->dbp, rtc->dbp_reg,
 767                                   rtc->dbp_mask, rtc->dbp_mask);
 768
 769        /*
 770         * After a system reset, RTC_ISR.INITS flag can be read to check if
 771         * the calendar has been initialized or not. INITS flag is reset by a
 772         * power-on reset (no vbat, no power-supply). It is not reset if
 773         * rtc_ck parent clock has changed (so RTC prescalers need to be
 774         * changed). That's why we cannot rely on this flag to know if RTC
 775         * init has to be done.
 776         */
 777        ret = stm32_rtc_init(pdev, rtc);
 778        if (ret)
 779                goto err;
 780
 781        rtc->irq_alarm = platform_get_irq(pdev, 0);
 782        if (rtc->irq_alarm <= 0) {
 783                dev_err(&pdev->dev, "no alarm irq\n");
 784                ret = rtc->irq_alarm;
 785                goto err;
 786        }
 787
 788        ret = device_init_wakeup(&pdev->dev, true);
 789        if (rtc->data->has_wakeirq) {
 790                rtc->wakeirq_alarm = platform_get_irq(pdev, 1);
 791                if (rtc->wakeirq_alarm <= 0)
 792                        ret = rtc->wakeirq_alarm;
 793                else
 794                        ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
 795                                                            rtc->wakeirq_alarm);
 796        }
 797        if (ret)
 798                dev_warn(&pdev->dev, "alarm can't wake up the system: %d", ret);
 799
 800        platform_set_drvdata(pdev, rtc);
 801
 802        rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
 803                                                &stm32_rtc_ops, THIS_MODULE);
 804        if (IS_ERR(rtc->rtc_dev)) {
 805                ret = PTR_ERR(rtc->rtc_dev);
 806                dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
 807                        ret);
 808                goto err;
 809        }
 810
 811        /* Handle RTC alarm interrupts */
 812        ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
 813                                        stm32_rtc_alarm_irq, IRQF_ONESHOT,
 814                                        pdev->name, rtc);
 815        if (ret) {
 816                dev_err(&pdev->dev, "IRQ%d (alarm interrupt) already claimed\n",
 817                        rtc->irq_alarm);
 818                goto err;
 819        }
 820
 821        /*
 822         * If INITS flag is reset (calendar year field set to 0x00), calendar
 823         * must be initialized
 824         */
 825        if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
 826                dev_warn(&pdev->dev, "Date/Time must be initialized\n");
 827
 828        if (regs->verr != UNDEF_REG) {
 829                u32 ver = readl_relaxed(rtc->base + regs->verr);
 830
 831                dev_info(&pdev->dev, "registered rev:%d.%d\n",
 832                         (ver >> STM32_RTC_VERR_MAJREV_SHIFT) & 0xF,
 833                         (ver >> STM32_RTC_VERR_MINREV_SHIFT) & 0xF);
 834        }
 835
 836        return 0;
 837err:
 838        if (rtc->data->has_pclk)
 839                clk_disable_unprepare(rtc->pclk);
 840        clk_disable_unprepare(rtc->rtc_ck);
 841
 842        if (rtc->data->need_dbp)
 843                regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
 844
 845        dev_pm_clear_wake_irq(&pdev->dev);
 846        device_init_wakeup(&pdev->dev, false);
 847
 848        return ret;
 849}
 850
 851static int stm32_rtc_remove(struct platform_device *pdev)
 852{
 853        struct stm32_rtc *rtc = platform_get_drvdata(pdev);
 854        const struct stm32_rtc_registers *regs = &rtc->data->regs;
 855        unsigned int cr;
 856
 857        /* Disable interrupts */
 858        stm32_rtc_wpr_unlock(rtc);
 859        cr = readl_relaxed(rtc->base + regs->cr);
 860        cr &= ~STM32_RTC_CR_ALRAIE;
 861        writel_relaxed(cr, rtc->base + regs->cr);
 862        stm32_rtc_wpr_lock(rtc);
 863
 864        clk_disable_unprepare(rtc->rtc_ck);
 865        if (rtc->data->has_pclk)
 866                clk_disable_unprepare(rtc->pclk);
 867
 868        /* Enable backup domain write protection if needed */
 869        if (rtc->data->need_dbp)
 870                regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
 871
 872        dev_pm_clear_wake_irq(&pdev->dev);
 873        device_init_wakeup(&pdev->dev, false);
 874
 875        return 0;
 876}
 877
 878#ifdef CONFIG_PM_SLEEP
 879static int stm32_rtc_suspend(struct device *dev)
 880{
 881        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 882
 883        if (rtc->data->has_pclk)
 884                clk_disable_unprepare(rtc->pclk);
 885
 886        if (device_may_wakeup(dev))
 887                return enable_irq_wake(rtc->irq_alarm);
 888
 889        return 0;
 890}
 891
 892static int stm32_rtc_resume(struct device *dev)
 893{
 894        struct stm32_rtc *rtc = dev_get_drvdata(dev);
 895        int ret = 0;
 896
 897        if (rtc->data->has_pclk) {
 898                ret = clk_prepare_enable(rtc->pclk);
 899                if (ret)
 900                        return ret;
 901        }
 902
 903        ret = stm32_rtc_wait_sync(rtc);
 904        if (ret < 0)
 905                return ret;
 906
 907        if (device_may_wakeup(dev))
 908                return disable_irq_wake(rtc->irq_alarm);
 909
 910        return ret;
 911}
 912#endif
 913
 914static SIMPLE_DEV_PM_OPS(stm32_rtc_pm_ops,
 915                         stm32_rtc_suspend, stm32_rtc_resume);
 916
 917static struct platform_driver stm32_rtc_driver = {
 918        .probe          = stm32_rtc_probe,
 919        .remove         = stm32_rtc_remove,
 920        .driver         = {
 921                .name   = DRIVER_NAME,
 922                .pm     = &stm32_rtc_pm_ops,
 923                .of_match_table = stm32_rtc_of_match,
 924        },
 925};
 926
 927module_platform_driver(stm32_rtc_driver);
 928
 929MODULE_ALIAS("platform:" DRIVER_NAME);
 930MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
 931MODULE_DESCRIPTION("STMicroelectronics STM32 Real Time Clock driver");
 932MODULE_LICENSE("GPL v2");
 933