1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50#ifndef _IPS_H_
51 #define _IPS_H_
52
53#include <linux/nmi.h>
54#include <linux/uaccess.h>
55 #include <asm/io.h>
56
57
58
59
60 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
61 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
62 #define IPS_IS_TROMBONE(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
63 (ha->pcidev->revision >= IPS_REVID_TROMBONE32) && \
64 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) ? 1 : 0)
65 #define IPS_IS_CLARINET(ha) (((ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) && \
66 (ha->pcidev->revision >= IPS_REVID_CLARINETP1) && \
67 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) ? 1 : 0)
68 #define IPS_IS_MORPHEUS(ha) (ha->pcidev->device == IPS_DEVICEID_MORPHEUS)
69 #define IPS_IS_MARCO(ha) (ha->pcidev->device == IPS_DEVICEID_MARCO)
70 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
71 (IPS_IS_TROMBONE(ha) && \
72 (ips_force_i2o))) ? 1 : 0)
73 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
74 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
75 (ips_force_memio))) ? 1 : 0)
76
77 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
78 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
79 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
80 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
81
82 #define IPS_PRINTK(level, pcidev, format, arg...) \
83 dev_printk(level , &((pcidev)->dev) , format , ## arg)
84
85 #define MDELAY(n) \
86 do { \
87 mdelay(n); \
88 touch_nmi_watchdog(); \
89 } while (0)
90
91 #ifndef min
92 #define min(x,y) ((x) < (y) ? x : y)
93 #endif
94
95 #ifndef __iomem
96 #define __iomem
97 #endif
98
99 #define pci_dma_hi32(a) ((a >> 16) >> 16)
100 #define pci_dma_lo32(a) (a & 0xffffffff)
101
102 #if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
103 #define IPS_ENABLE_DMA64 (1)
104 #else
105 #define IPS_ENABLE_DMA64 (0)
106 #endif
107
108
109
110
111 #define IPS_REG_HISR 0x08
112 #define IPS_REG_CCSAR 0x10
113 #define IPS_REG_CCCR 0x14
114 #define IPS_REG_SQHR 0x20
115 #define IPS_REG_SQTR 0x24
116 #define IPS_REG_SQER 0x28
117 #define IPS_REG_SQSR 0x2C
118 #define IPS_REG_SCPR 0x05
119 #define IPS_REG_ISPR 0x06
120 #define IPS_REG_CBSP 0x07
121 #define IPS_REG_FLAP 0x18
122 #define IPS_REG_FLDP 0x1C
123 #define IPS_REG_NDAE 0x38
124 #define IPS_REG_I2O_INMSGQ 0x40
125 #define IPS_REG_I2O_OUTMSGQ 0x44
126 #define IPS_REG_I2O_HIR 0x30
127 #define IPS_REG_I960_IDR 0x20
128 #define IPS_REG_I960_MSG0 0x18
129 #define IPS_REG_I960_MSG1 0x1C
130 #define IPS_REG_I960_OIMR 0x34
131
132
133
134
135 #define IPS_BIT_GHI 0x04
136 #define IPS_BIT_SQO 0x02
137 #define IPS_BIT_SCE 0x01
138 #define IPS_BIT_SEM 0x08
139 #define IPS_BIT_ILE 0x10
140 #define IPS_BIT_START_CMD 0x101A
141 #define IPS_BIT_START_STOP 0x0002
142 #define IPS_BIT_RST 0x80
143 #define IPS_BIT_EBM 0x02
144 #define IPS_BIT_EI 0x80
145 #define IPS_BIT_OP 0x01
146 #define IPS_BIT_I2O_OPQI 0x08
147 #define IPS_BIT_I960_MSG0I 0x01
148 #define IPS_BIT_I960_MSG1I 0x02
149
150
151
152
153 #define IPS_CMD_GET_LD_INFO 0x19
154 #define IPS_CMD_GET_SUBSYS 0x40
155 #define IPS_CMD_READ_CONF 0x38
156 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
157 #define IPS_CMD_READ 0x02
158 #define IPS_CMD_WRITE 0x03
159 #define IPS_CMD_FFDC 0xD7
160 #define IPS_CMD_ENQUIRY 0x05
161 #define IPS_CMD_FLUSH 0x0A
162 #define IPS_CMD_READ_SG 0x82
163 #define IPS_CMD_WRITE_SG 0x83
164 #define IPS_CMD_DCDB 0x04
165 #define IPS_CMD_DCDB_SG 0x84
166 #define IPS_CMD_EXTENDED_DCDB 0x95
167 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
168 #define IPS_CMD_CONFIG_SYNC 0x58
169 #define IPS_CMD_ERROR_TABLE 0x17
170 #define IPS_CMD_DOWNLOAD 0x20
171 #define IPS_CMD_RW_BIOSFW 0x22
172 #define IPS_CMD_GET_VERSION_INFO 0xC6
173 #define IPS_CMD_RESET_CHANNEL 0x1A
174
175
176
177
178 #define IPS_CSL 0xFF
179 #define IPS_POCL 0x30
180 #define IPS_NORM_STATE 0x00
181 #define IPS_MAX_ADAPTER_TYPES 3
182 #define IPS_MAX_ADAPTERS 16
183 #define IPS_MAX_IOCTL 1
184 #define IPS_MAX_IOCTL_QUEUE 8
185 #define IPS_MAX_QUEUE 128
186 #define IPS_BLKSIZE 512
187 #define IPS_MAX_SG 17
188 #define IPS_MAX_LD 8
189 #define IPS_MAX_CHANNELS 4
190 #define IPS_MAX_TARGETS 15
191 #define IPS_MAX_CHUNKS 16
192 #define IPS_MAX_CMDS 128
193 #define IPS_MAX_XFER 0x10000
194 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
195 #define IPS_MAX_POST_BYTES 0x02
196 #define IPS_MAX_CONFIG_BYTES 0x02
197 #define IPS_GOOD_POST_STATUS 0x80
198 #define IPS_SEM_TIMEOUT 2000
199 #define IPS_IOCTL_COMMAND 0x0D
200 #define IPS_INTR_ON 0
201 #define IPS_INTR_IORL 1
202 #define IPS_FFDC 99
203 #define IPS_ADAPTER_ID 0xF
204 #define IPS_VENDORID_IBM 0x1014
205 #define IPS_VENDORID_ADAPTEC 0x9005
206 #define IPS_DEVICEID_COPPERHEAD 0x002E
207 #define IPS_DEVICEID_MORPHEUS 0x01BD
208 #define IPS_DEVICEID_MARCO 0x0250
209 #define IPS_SUBDEVICEID_4M 0x01BE
210 #define IPS_SUBDEVICEID_4L 0x01BF
211 #define IPS_SUBDEVICEID_4MX 0x0208
212 #define IPS_SUBDEVICEID_4LX 0x020E
213 #define IPS_SUBDEVICEID_5I2 0x0259
214 #define IPS_SUBDEVICEID_5I1 0x0258
215 #define IPS_SUBDEVICEID_6M 0x0279
216 #define IPS_SUBDEVICEID_6I 0x028C
217 #define IPS_SUBDEVICEID_7k 0x028E
218 #define IPS_SUBDEVICEID_7M 0x028F
219 #define IPS_IOCTL_SIZE 8192
220 #define IPS_STATUS_SIZE 4
221 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
222 #define IPS_IMAGE_SIZE 500 * 1024
223 #define IPS_MEMMAP_SIZE 128
224 #define IPS_ONE_MSEC 1
225 #define IPS_ONE_SEC 1000
226
227
228
229
230 #define IPS_COMP_HEADS 128
231 #define IPS_COMP_SECTORS 32
232 #define IPS_NORM_HEADS 254
233 #define IPS_NORM_SECTORS 63
234
235
236
237
238 #define IPS_BASIC_STATUS_MASK 0xFF
239 #define IPS_GSC_STATUS_MASK 0x0F
240 #define IPS_CMD_SUCCESS 0x00
241 #define IPS_CMD_RECOVERED_ERROR 0x01
242 #define IPS_INVAL_OPCO 0x03
243 #define IPS_INVAL_CMD_BLK 0x04
244 #define IPS_INVAL_PARM_BLK 0x05
245 #define IPS_BUSY 0x08
246 #define IPS_CMD_CMPLT_WERROR 0x0C
247 #define IPS_LD_ERROR 0x0D
248 #define IPS_CMD_TIMEOUT 0x0E
249 #define IPS_PHYS_DRV_ERROR 0x0F
250
251
252
253
254 #define IPS_ERR_SEL_TO 0xF0
255 #define IPS_ERR_OU_RUN 0xF2
256 #define IPS_ERR_HOST_RESET 0xF7
257 #define IPS_ERR_DEV_RESET 0xF8
258 #define IPS_ERR_RECOVERY 0xFC
259 #define IPS_ERR_CKCOND 0xFF
260
261
262
263
264 #define IPS_OS_WINDOWS_NT 0x01
265 #define IPS_OS_NETWARE 0x02
266 #define IPS_OS_OPENSERVER 0x03
267 #define IPS_OS_UNIXWARE 0x04
268 #define IPS_OS_SOLARIS 0x05
269 #define IPS_OS_OS2 0x06
270 #define IPS_OS_LINUX 0x07
271 #define IPS_OS_FREEBSD 0x08
272
273
274
275
276 #define IPS_REVID_SERVERAID 0x02
277 #define IPS_REVID_NAVAJO 0x03
278 #define IPS_REVID_SERVERAID2 0x04
279 #define IPS_REVID_CLARINETP1 0x05
280 #define IPS_REVID_CLARINETP2 0x07
281 #define IPS_REVID_CLARINETP3 0x0D
282 #define IPS_REVID_TROMBONE32 0x0F
283 #define IPS_REVID_TROMBONE64 0x10
284
285
286
287
288 #define IPS_ADTYPE_SERVERAID 0x01
289 #define IPS_ADTYPE_SERVERAID2 0x02
290 #define IPS_ADTYPE_NAVAJO 0x03
291 #define IPS_ADTYPE_KIOWA 0x04
292 #define IPS_ADTYPE_SERVERAID3 0x05
293 #define IPS_ADTYPE_SERVERAID3L 0x06
294 #define IPS_ADTYPE_SERVERAID4H 0x07
295 #define IPS_ADTYPE_SERVERAID4M 0x08
296 #define IPS_ADTYPE_SERVERAID4L 0x09
297 #define IPS_ADTYPE_SERVERAID4MX 0x0A
298 #define IPS_ADTYPE_SERVERAID4LX 0x0B
299 #define IPS_ADTYPE_SERVERAID5I2 0x0C
300 #define IPS_ADTYPE_SERVERAID5I1 0x0D
301 #define IPS_ADTYPE_SERVERAID6M 0x0E
302 #define IPS_ADTYPE_SERVERAID6I 0x0F
303 #define IPS_ADTYPE_SERVERAID7t 0x10
304 #define IPS_ADTYPE_SERVERAID7k 0x11
305 #define IPS_ADTYPE_SERVERAID7M 0x12
306
307
308
309
310 #define IPS_SUCCESS 0x01
311 #define IPS_SUCCESS_IMM 0x02
312 #define IPS_FAILURE 0x04
313
314
315
316
317 #define IPS_LD_OFFLINE 0x02
318 #define IPS_LD_OKAY 0x03
319 #define IPS_LD_FREE 0x00
320 #define IPS_LD_SYS 0x06
321 #define IPS_LD_CRS 0x24
322
323
324
325
326 #define IPS_NO_DISCONNECT 0x00
327 #define IPS_DISCONNECT_ALLOWED 0x80
328 #define IPS_NO_AUTO_REQSEN 0x40
329 #define IPS_DATA_NONE 0x00
330 #define IPS_DATA_UNK 0x00
331 #define IPS_DATA_IN 0x01
332 #define IPS_DATA_OUT 0x02
333 #define IPS_TRANSFER64K 0x08
334 #define IPS_NOTIMEOUT 0x00
335 #define IPS_TIMEOUT10 0x10
336 #define IPS_TIMEOUT60 0x20
337 #define IPS_TIMEOUT20M 0x30
338
339
340
341
342 #define IPS_SCSI_INQ_TYPE_DASD 0x00
343 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
344 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
345 #define IPS_SCSI_INQ_RD_REV2 0x02
346 #define IPS_SCSI_INQ_REV2 0x02
347 #define IPS_SCSI_INQ_REV3 0x03
348 #define IPS_SCSI_INQ_Address16 0x01
349 #define IPS_SCSI_INQ_Address32 0x02
350 #define IPS_SCSI_INQ_MedChanger 0x08
351 #define IPS_SCSI_INQ_MultiPort 0x10
352 #define IPS_SCSI_INQ_EncServ 0x40
353 #define IPS_SCSI_INQ_SoftReset 0x01
354 #define IPS_SCSI_INQ_CmdQue 0x02
355 #define IPS_SCSI_INQ_Linked 0x08
356 #define IPS_SCSI_INQ_Sync 0x10
357 #define IPS_SCSI_INQ_WBus16 0x20
358 #define IPS_SCSI_INQ_WBus32 0x40
359 #define IPS_SCSI_INQ_RelAdr 0x80
360
361
362
363
364 #define IPS_SCSI_REQSEN_VALID 0x80
365 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
366 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
367
368
369
370
371 #define IPS_SCSI_MP3_SoftSector 0x01
372 #define IPS_SCSI_MP3_HardSector 0x02
373 #define IPS_SCSI_MP3_Removeable 0x04
374 #define IPS_SCSI_MP3_AllocateSurface 0x08
375
376
377
378
379
380 #define IPS_HA_ENH_SG 0x1
381
382
383
384
385 #define IPS_SCB_MAP_SG 0x00008
386 #define IPS_SCB_MAP_SINGLE 0X00010
387
388
389
390
391 #define IPS_COPPUSRCMD (('C'<<8) | 65)
392 #define IPS_COPPIOCCMD (('C'<<8) | 66)
393 #define IPS_NUMCTRLS (('C'<<8) | 68)
394 #define IPS_CTRLINFO (('C'<<8) | 69)
395
396
397 #define IPS_FW_IMAGE 0x00
398 #define IPS_BIOS_IMAGE 0x01
399 #define IPS_WRITE_FW 0x01
400 #define IPS_WRITE_BIOS 0x02
401 #define IPS_ERASE_BIOS 0x03
402 #define IPS_BIOS_HEADER 0xC0
403
404
405 #define IPS_SECS_8HOURS 28800
406
407
408
409
410 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
411 sector_t capacity, int geom[]);
412 static int ips_slave_configure(struct scsi_device *SDptr);
413
414
415
416
417typedef struct {
418 uint8_t op_code;
419 uint8_t command_id;
420 uint8_t log_drv;
421 uint8_t sg_count;
422 uint32_t lba;
423 uint32_t sg_addr;
424 uint16_t sector_count;
425 uint8_t segment_4G;
426 uint8_t enhanced_sg;
427 uint32_t ccsar;
428 uint32_t cccr;
429} IPS_IO_CMD, *PIPS_IO_CMD;
430
431typedef struct {
432 uint8_t op_code;
433 uint8_t command_id;
434 uint16_t reserved;
435 uint32_t reserved2;
436 uint32_t buffer_addr;
437 uint32_t reserved3;
438 uint32_t ccsar;
439 uint32_t cccr;
440} IPS_LD_CMD, *PIPS_LD_CMD;
441
442typedef struct {
443 uint8_t op_code;
444 uint8_t command_id;
445 uint8_t reserved;
446 uint8_t reserved2;
447 uint32_t reserved3;
448 uint32_t buffer_addr;
449 uint32_t reserved4;
450} IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
451
452typedef struct {
453 uint8_t op_code;
454 uint8_t command_id;
455 uint8_t channel;
456 uint8_t reserved3;
457 uint8_t reserved4;
458 uint8_t reserved5;
459 uint8_t reserved6;
460 uint8_t reserved7;
461 uint8_t reserved8;
462 uint8_t reserved9;
463 uint8_t reserved10;
464 uint8_t reserved11;
465 uint8_t reserved12;
466 uint8_t reserved13;
467 uint8_t reserved14;
468 uint8_t adapter_flag;
469} IPS_RESET_CMD, *PIPS_RESET_CMD;
470
471typedef struct {
472 uint8_t op_code;
473 uint8_t command_id;
474 uint16_t reserved;
475 uint32_t reserved2;
476 uint32_t dcdb_address;
477 uint16_t reserved3;
478 uint8_t segment_4G;
479 uint8_t enhanced_sg;
480 uint32_t ccsar;
481 uint32_t cccr;
482} IPS_DCDB_CMD, *PIPS_DCDB_CMD;
483
484typedef struct {
485 uint8_t op_code;
486 uint8_t command_id;
487 uint8_t channel;
488 uint8_t source_target;
489 uint32_t reserved;
490 uint32_t reserved2;
491 uint32_t reserved3;
492 uint32_t ccsar;
493 uint32_t cccr;
494} IPS_CS_CMD, *PIPS_CS_CMD;
495
496typedef struct {
497 uint8_t op_code;
498 uint8_t command_id;
499 uint8_t log_drv;
500 uint8_t control;
501 uint32_t reserved;
502 uint32_t reserved2;
503 uint32_t reserved3;
504 uint32_t ccsar;
505 uint32_t cccr;
506} IPS_US_CMD, *PIPS_US_CMD;
507
508typedef struct {
509 uint8_t op_code;
510 uint8_t command_id;
511 uint8_t reserved;
512 uint8_t state;
513 uint32_t reserved2;
514 uint32_t reserved3;
515 uint32_t reserved4;
516 uint32_t ccsar;
517 uint32_t cccr;
518} IPS_FC_CMD, *PIPS_FC_CMD;
519
520typedef struct {
521 uint8_t op_code;
522 uint8_t command_id;
523 uint8_t reserved;
524 uint8_t desc;
525 uint32_t reserved2;
526 uint32_t buffer_addr;
527 uint32_t reserved3;
528 uint32_t ccsar;
529 uint32_t cccr;
530} IPS_STATUS_CMD, *PIPS_STATUS_CMD;
531
532typedef struct {
533 uint8_t op_code;
534 uint8_t command_id;
535 uint8_t page;
536 uint8_t write;
537 uint32_t reserved;
538 uint32_t buffer_addr;
539 uint32_t reserved2;
540 uint32_t ccsar;
541 uint32_t cccr;
542} IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
543
544typedef struct
545{
546 uint8_t op_code;
547 uint8_t command_id;
548 uint16_t reserved;
549 uint32_t count;
550 uint32_t buffer_addr;
551 uint32_t reserved2;
552} IPS_VERSION_INFO, *PIPS_VERSION_INFO;
553
554typedef struct {
555 uint8_t op_code;
556 uint8_t command_id;
557 uint8_t reset_count;
558 uint8_t reset_type;
559 uint8_t second;
560 uint8_t minute;
561 uint8_t hour;
562 uint8_t day;
563 uint8_t reserved1[4];
564 uint8_t month;
565 uint8_t yearH;
566 uint8_t yearL;
567 uint8_t reserved2;
568} IPS_FFDC_CMD, *PIPS_FFDC_CMD;
569
570typedef struct {
571 uint8_t op_code;
572 uint8_t command_id;
573 uint8_t type;
574 uint8_t direction;
575 uint32_t count;
576 uint32_t buffer_addr;
577 uint8_t total_packets;
578 uint8_t packet_num;
579 uint16_t reserved;
580} IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
581
582typedef struct {
583 uint8_t op_code;
584 uint8_t command_id;
585 uint8_t type;
586 uint8_t direction;
587 uint32_t count;
588 uint32_t buffer_addr;
589 uint32_t offset;
590} IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
591
592typedef union {
593 IPS_IO_CMD basic_io;
594 IPS_LD_CMD logical_info;
595 IPS_IOCTL_CMD ioctl_info;
596 IPS_DCDB_CMD dcdb;
597 IPS_CS_CMD config_sync;
598 IPS_US_CMD unlock_stripe;
599 IPS_FC_CMD flush_cache;
600 IPS_STATUS_CMD status;
601 IPS_NVRAM_CMD nvram;
602 IPS_FFDC_CMD ffdc;
603 IPS_FLASHFW_CMD flashfw;
604 IPS_FLASHBIOS_CMD flashbios;
605 IPS_VERSION_INFO version_info;
606 IPS_RESET_CMD reset;
607} IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
608
609typedef struct {
610 uint8_t logical_id;
611 uint8_t reserved;
612 uint8_t raid_level;
613 uint8_t state;
614 uint32_t sector_count;
615} IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
616
617typedef struct {
618 uint8_t no_of_log_drive;
619 uint8_t reserved[3];
620 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
621} IPS_LD_INFO, *PIPS_LD_INFO;
622
623typedef struct {
624 uint8_t device_address;
625 uint8_t cmd_attribute;
626 uint16_t transfer_length;
627 uint32_t buffer_pointer;
628 uint8_t cdb_length;
629 uint8_t sense_length;
630 uint8_t sg_count;
631 uint8_t reserved;
632 uint8_t scsi_cdb[12];
633 uint8_t sense_info[64];
634 uint8_t scsi_status;
635 uint8_t reserved2[3];
636} IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
637
638typedef struct {
639 uint8_t device_address;
640 uint8_t cmd_attribute;
641 uint8_t cdb_length;
642 uint8_t reserved_for_LUN;
643 uint32_t transfer_length;
644 uint32_t buffer_pointer;
645 uint16_t sg_count;
646 uint8_t sense_length;
647 uint8_t scsi_status;
648 uint32_t reserved;
649 uint8_t scsi_cdb[16];
650 uint8_t sense_info[56];
651} IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
652
653typedef union {
654 struct {
655 volatile uint8_t reserved;
656 volatile uint8_t command_id;
657 volatile uint8_t basic_status;
658 volatile uint8_t extended_status;
659 } fields;
660
661 volatile uint32_t value;
662} IPS_STATUS, *PIPS_STATUS;
663
664typedef struct {
665 IPS_STATUS status[IPS_MAX_CMDS + 1];
666 volatile PIPS_STATUS p_status_start;
667 volatile PIPS_STATUS p_status_end;
668 volatile PIPS_STATUS p_status_tail;
669 volatile uint32_t hw_status_start;
670 volatile uint32_t hw_status_tail;
671} IPS_ADAPTER, *PIPS_ADAPTER;
672
673typedef struct {
674 uint8_t ucLogDriveCount;
675 uint8_t ucMiscFlag;
676 uint8_t ucSLTFlag;
677 uint8_t ucBSTFlag;
678 uint8_t ucPwrChgCnt;
679 uint8_t ucWrongAdrCnt;
680 uint8_t ucUnidentCnt;
681 uint8_t ucNVramDevChgCnt;
682 uint8_t CodeBlkVersion[8];
683 uint8_t BootBlkVersion[8];
684 uint32_t ulDriveSize[IPS_MAX_LD];
685 uint8_t ucConcurrentCmdCount;
686 uint8_t ucMaxPhysicalDevices;
687 uint16_t usFlashRepgmCount;
688 uint8_t ucDefunctDiskCount;
689 uint8_t ucRebuildFlag;
690 uint8_t ucOfflineLogDrvCount;
691 uint8_t ucCriticalDrvCount;
692 uint16_t usConfigUpdateCount;
693 uint8_t ucBlkFlag;
694 uint8_t reserved;
695 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
696} IPS_ENQ, *PIPS_ENQ;
697
698typedef struct {
699 uint8_t ucInitiator;
700 uint8_t ucParameters;
701 uint8_t ucMiscFlag;
702 uint8_t ucState;
703 uint32_t ulBlockCount;
704 uint8_t ucDeviceId[28];
705} IPS_DEVSTATE, *PIPS_DEVSTATE;
706
707typedef struct {
708 uint8_t ucChn;
709 uint8_t ucTgt;
710 uint16_t ucReserved;
711 uint32_t ulStartSect;
712 uint32_t ulNoOfSects;
713} IPS_CHUNK, *PIPS_CHUNK;
714
715typedef struct {
716 uint16_t ucUserField;
717 uint8_t ucState;
718 uint8_t ucRaidCacheParam;
719 uint8_t ucNoOfChunkUnits;
720 uint8_t ucStripeSize;
721 uint8_t ucParams;
722 uint8_t ucReserved;
723 uint32_t ulLogDrvSize;
724 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
725} IPS_LD, *PIPS_LD;
726
727typedef struct {
728 uint8_t board_disc[8];
729 uint8_t processor[8];
730 uint8_t ucNoChanType;
731 uint8_t ucNoHostIntType;
732 uint8_t ucCompression;
733 uint8_t ucNvramType;
734 uint32_t ulNvramSize;
735} IPS_HARDWARE, *PIPS_HARDWARE;
736
737typedef struct {
738 uint8_t ucLogDriveCount;
739 uint8_t ucDateD;
740 uint8_t ucDateM;
741 uint8_t ucDateY;
742 uint8_t init_id[4];
743 uint8_t host_id[12];
744 uint8_t time_sign[8];
745 uint32_t UserOpt;
746 uint16_t user_field;
747 uint8_t ucRebuildRate;
748 uint8_t ucReserve;
749 IPS_HARDWARE hardware_disc;
750 IPS_LD logical_drive[IPS_MAX_LD];
751 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
752 uint8_t reserved[512];
753} IPS_CONF, *PIPS_CONF;
754
755typedef struct {
756 uint32_t signature;
757 uint8_t reserved1;
758 uint8_t adapter_slot;
759 uint16_t adapter_type;
760 uint8_t ctrl_bios[8];
761 uint8_t versioning;
762 uint8_t version_mismatch;
763 uint8_t reserved2;
764 uint8_t operating_system;
765 uint8_t driver_high[4];
766 uint8_t driver_low[4];
767 uint8_t BiosCompatibilityID[8];
768 uint8_t ReservedForOS2[8];
769 uint8_t bios_high[4];
770 uint8_t bios_low[4];
771 uint8_t adapter_order[16];
772 uint8_t Filler[60];
773} IPS_NVRAM_P5, *PIPS_NVRAM_P5;
774
775
776
777
778
779
780#define IPS_GET_VERSION_SUPPORT 0x00018000
781
782typedef struct
783{
784 uint32_t revision;
785 uint8_t bootBlkVersion[32];
786 uint8_t bootBlkAttributes[4];
787 uint8_t codeBlkVersion[32];
788 uint8_t biosVersion[32];
789 uint8_t biosAttributes[4];
790 uint8_t compatibilityId[32];
791 uint8_t reserved[4];
792} IPS_VERSION_DATA;
793
794
795typedef struct _IPS_SUBSYS {
796 uint32_t param[128];
797} IPS_SUBSYS, *PIPS_SUBSYS;
798
799
800
801
802
803
804
805
806typedef struct {
807 uint8_t DeviceType;
808 uint8_t DeviceTypeQualifier;
809 uint8_t Version;
810 uint8_t ResponseDataFormat;
811 uint8_t AdditionalLength;
812 uint8_t Reserved;
813 uint8_t Flags[2];
814 uint8_t VendorId[8];
815 uint8_t ProductId[16];
816 uint8_t ProductRevisionLevel[4];
817 uint8_t Reserved2;
818} IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
819
820
821
822
823typedef struct {
824 uint32_t lba;
825 uint32_t len;
826} IPS_SCSI_CAPACITY;
827
828
829
830
831typedef struct {
832 uint8_t ResponseCode;
833 uint8_t SegmentNumber;
834 uint8_t Flags;
835 uint8_t Information[4];
836 uint8_t AdditionalLength;
837 uint8_t CommandSpecific[4];
838 uint8_t AdditionalSenseCode;
839 uint8_t AdditionalSenseCodeQual;
840 uint8_t FRUCode;
841 uint8_t SenseKeySpecific[3];
842} IPS_SCSI_REQSEN;
843
844
845
846
847typedef struct {
848 uint8_t PageCode;
849 uint8_t PageLength;
850 uint16_t TracksPerZone;
851 uint16_t AltSectorsPerZone;
852 uint16_t AltTracksPerZone;
853 uint16_t AltTracksPerVolume;
854 uint16_t SectorsPerTrack;
855 uint16_t BytesPerSector;
856 uint16_t Interleave;
857 uint16_t TrackSkew;
858 uint16_t CylinderSkew;
859 uint8_t flags;
860 uint8_t reserved[3];
861} IPS_SCSI_MODE_PAGE3;
862
863
864
865
866typedef struct {
867 uint8_t PageCode;
868 uint8_t PageLength;
869 uint16_t CylindersHigh;
870 uint8_t CylindersLow;
871 uint8_t Heads;
872 uint16_t WritePrecompHigh;
873 uint8_t WritePrecompLow;
874 uint16_t ReducedWriteCurrentHigh;
875 uint8_t ReducedWriteCurrentLow;
876 uint16_t StepRate;
877 uint16_t LandingZoneHigh;
878 uint8_t LandingZoneLow;
879 uint8_t flags;
880 uint8_t RotationalOffset;
881 uint8_t Reserved;
882 uint16_t MediumRotationRate;
883 uint8_t Reserved2[2];
884} IPS_SCSI_MODE_PAGE4;
885
886
887
888
889typedef struct {
890 uint8_t PageCode;
891 uint8_t PageLength;
892 uint8_t flags;
893 uint8_t RetentPrio;
894 uint16_t DisPrefetchLen;
895 uint16_t MinPrefetchLen;
896 uint16_t MaxPrefetchLen;
897 uint16_t MaxPrefetchCeiling;
898} IPS_SCSI_MODE_PAGE8;
899
900
901
902
903typedef struct {
904 uint32_t NumberOfBlocks;
905 uint8_t DensityCode;
906 uint16_t BlockLengthHigh;
907 uint8_t BlockLengthLow;
908} IPS_SCSI_MODE_PAGE_BLKDESC;
909
910
911
912
913typedef struct {
914 uint8_t DataLength;
915 uint8_t MediumType;
916 uint8_t Reserved;
917 uint8_t BlockDescLength;
918} IPS_SCSI_MODE_PAGE_HEADER;
919
920typedef struct {
921 IPS_SCSI_MODE_PAGE_HEADER hdr;
922 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
923
924 union {
925 IPS_SCSI_MODE_PAGE3 pg3;
926 IPS_SCSI_MODE_PAGE4 pg4;
927 IPS_SCSI_MODE_PAGE8 pg8;
928 } pdata;
929} IPS_SCSI_MODE_PAGE_DATA;
930
931
932
933
934typedef struct ips_sglist {
935 uint32_t address;
936 uint32_t length;
937} IPS_STD_SG_LIST;
938
939typedef struct ips_enh_sglist {
940 uint32_t address_lo;
941 uint32_t address_hi;
942 uint32_t length;
943 uint32_t reserved;
944} IPS_ENH_SG_LIST;
945
946typedef union {
947 void *list;
948 IPS_STD_SG_LIST *std_list;
949 IPS_ENH_SG_LIST *enh_list;
950} IPS_SG_LIST;
951
952typedef struct {
953 char *option_name;
954 int *option_flag;
955 int option_value;
956} IPS_OPTION;
957
958
959
960
961typedef struct ips_stat {
962 uint32_t residue_len;
963 void *scb_addr;
964 uint8_t padding[12 - sizeof(void *)];
965} ips_stat_t;
966
967
968
969
970typedef struct ips_scb_queue {
971 struct ips_scb *head;
972 struct ips_scb *tail;
973 int count;
974} ips_scb_queue_t;
975
976
977
978
979typedef struct ips_wait_queue {
980 struct scsi_cmnd *head;
981 struct scsi_cmnd *tail;
982 int count;
983} ips_wait_queue_entry_t;
984
985typedef struct ips_copp_wait_item {
986 struct scsi_cmnd *scsi_cmd;
987 struct ips_copp_wait_item *next;
988} ips_copp_wait_item_t;
989
990typedef struct ips_copp_queue {
991 struct ips_copp_wait_item *head;
992 struct ips_copp_wait_item *tail;
993 int count;
994} ips_copp_queue_t;
995
996
997struct ips_ha;
998
999typedef struct {
1000 int (*reset)(struct ips_ha *);
1001 int (*issue)(struct ips_ha *, struct ips_scb *);
1002 int (*isinit)(struct ips_ha *);
1003 int (*isintr)(struct ips_ha *);
1004 int (*init)(struct ips_ha *);
1005 int (*erasebios)(struct ips_ha *);
1006 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1007 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1008 void (*statinit)(struct ips_ha *);
1009 int (*intr)(struct ips_ha *);
1010 void (*enableint)(struct ips_ha *);
1011 uint32_t (*statupd)(struct ips_ha *);
1012} ips_hw_func_t;
1013
1014typedef struct ips_ha {
1015 uint8_t ha_id[IPS_MAX_CHANNELS+1];
1016 uint32_t dcdb_active[IPS_MAX_CHANNELS];
1017 uint32_t io_addr;
1018 uint8_t ntargets;
1019 uint8_t nbus;
1020 uint8_t nlun;
1021 uint16_t ad_type;
1022 uint16_t host_num;
1023 uint32_t max_xfer;
1024 uint32_t max_cmds;
1025 uint32_t num_ioctl;
1026 ips_stat_t sp;
1027 struct ips_scb *scbs;
1028 struct ips_scb *scb_freelist;
1029 ips_wait_queue_entry_t scb_waitlist;
1030 ips_copp_queue_t copp_waitlist;
1031 ips_scb_queue_t scb_activelist;
1032 IPS_IO_CMD *dummy;
1033 IPS_ADAPTER *adapt;
1034 IPS_LD_INFO *logical_drive_info;
1035 dma_addr_t logical_drive_info_dma_addr;
1036 IPS_ENQ *enq;
1037 IPS_CONF *conf;
1038 IPS_NVRAM_P5 *nvram;
1039 IPS_SUBSYS *subsys;
1040 char *ioctl_data;
1041 uint32_t ioctl_datasize;
1042 uint32_t cmd_in_progress;
1043 int flags;
1044 uint8_t waitflag;
1045 uint8_t active;
1046 int ioctl_reset;
1047 uint16_t reset_count;
1048 time64_t last_ffdc;
1049 uint8_t slot_num;
1050 int ioctl_len;
1051 dma_addr_t ioctl_busaddr;
1052 uint8_t bios_version[8];
1053 uint32_t mem_addr;
1054 uint32_t io_len;
1055 uint32_t mem_len;
1056 char __iomem *mem_ptr;
1057 char __iomem *ioremap_ptr;
1058 ips_hw_func_t func;
1059 struct pci_dev *pcidev;
1060 char *flash_data;
1061 int flash_len;
1062 u32 flash_datasize;
1063 dma_addr_t flash_busaddr;
1064 dma_addr_t enq_busaddr;
1065 uint8_t requires_esl;
1066} ips_ha_t;
1067
1068typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1069
1070
1071
1072
1073typedef struct ips_scb {
1074 IPS_HOST_COMMAND cmd;
1075 IPS_DCDB_TABLE dcdb;
1076 uint8_t target_id;
1077 uint8_t bus;
1078 uint8_t lun;
1079 uint8_t cdb[12];
1080 uint32_t scb_busaddr;
1081 uint32_t old_data_busaddr;
1082 uint32_t timeout;
1083 uint8_t basic_status;
1084 uint8_t extended_status;
1085 uint8_t breakup;
1086 uint8_t sg_break;
1087 uint32_t data_len;
1088 uint32_t sg_len;
1089 uint32_t flags;
1090 uint32_t op_code;
1091 IPS_SG_LIST sg_list;
1092 struct scsi_cmnd *scsi_cmd;
1093 struct ips_scb *q_next;
1094 ips_scb_callback callback;
1095 uint32_t sg_busaddr;
1096 int sg_count;
1097 dma_addr_t data_busaddr;
1098} ips_scb_t;
1099
1100typedef struct ips_scb_pt {
1101 IPS_HOST_COMMAND cmd;
1102 IPS_DCDB_TABLE dcdb;
1103 uint8_t target_id;
1104 uint8_t bus;
1105 uint8_t lun;
1106 uint8_t cdb[12];
1107 uint32_t scb_busaddr;
1108 uint32_t data_busaddr;
1109 uint32_t timeout;
1110 uint8_t basic_status;
1111 uint8_t extended_status;
1112 uint16_t breakup;
1113 uint32_t data_len;
1114 uint32_t sg_len;
1115 uint32_t flags;
1116 uint32_t op_code;
1117 IPS_SG_LIST *sg_list;
1118 struct scsi_cmnd *scsi_cmd;
1119 struct ips_scb *q_next;
1120 ips_scb_callback callback;
1121} ips_scb_pt_t;
1122
1123
1124
1125
1126typedef struct {
1127 uint8_t CoppID[4];
1128 uint32_t CoppCmd;
1129 uint32_t PtBuffer;
1130 uint8_t *CmdBuffer;
1131 uint32_t CmdBSize;
1132 ips_scb_pt_t CoppCP;
1133 uint32_t TimeOut;
1134 uint8_t BasicStatus;
1135 uint8_t ExtendedStatus;
1136 uint8_t AdapterType;
1137 uint8_t reserved;
1138} ips_passthru_t;
1139
1140#endif
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151#define IPS_VER_MAJOR 7
1152#define IPS_VER_MAJOR_STRING __stringify(IPS_VER_MAJOR)
1153#define IPS_VER_MINOR 12
1154#define IPS_VER_MINOR_STRING __stringify(IPS_VER_MINOR)
1155#define IPS_VER_BUILD 05
1156#define IPS_VER_BUILD_STRING __stringify(IPS_VER_BUILD)
1157#define IPS_VER_STRING IPS_VER_MAJOR_STRING "." \
1158 IPS_VER_MINOR_STRING "." IPS_VER_BUILD_STRING
1159#define IPS_RELEASE_ID 0x00020000
1160#define IPS_BUILD_IDENT 761
1161#define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1162#define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1163#define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1164#define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1165
1166
1167#define IPS_VER_SERVERAID1 "2.25.01"
1168#define IPS_VER_SERVERAID2 "2.88.13"
1169#define IPS_VER_NAVAJO "2.88.13"
1170#define IPS_VER_SERVERAID3 "6.10.24"
1171#define IPS_VER_SERVERAID4H "7.12.02"
1172#define IPS_VER_SERVERAID4MLx "7.12.02"
1173#define IPS_VER_SARASOTA "7.12.02"
1174#define IPS_VER_MARCO "7.12.02"
1175#define IPS_VER_SEBRING "7.12.02"
1176#define IPS_VER_KEYWEST "7.12.02"
1177
1178
1179#define IPS_COMPAT_UNKNOWN ""
1180#define IPS_COMPAT_CURRENT "KW710"
1181#define IPS_COMPAT_SERVERAID1 "2.25.01"
1182#define IPS_COMPAT_SERVERAID2 "2.88.13"
1183#define IPS_COMPAT_NAVAJO "2.88.13"
1184#define IPS_COMPAT_KIOWA "2.88.13"
1185#define IPS_COMPAT_SERVERAID3H "SB610"
1186#define IPS_COMPAT_SERVERAID3L "SB610"
1187#define IPS_COMPAT_SERVERAID4H "KW710"
1188#define IPS_COMPAT_SERVERAID4M "KW710"
1189#define IPS_COMPAT_SERVERAID4L "KW710"
1190#define IPS_COMPAT_SERVERAID4Mx "KW710"
1191#define IPS_COMPAT_SERVERAID4Lx "KW710"
1192#define IPS_COMPAT_SARASOTA "KW710"
1193#define IPS_COMPAT_MARCO "KW710"
1194#define IPS_COMPAT_SEBRING "KW710"
1195#define IPS_COMPAT_TAMPA "KW710"
1196#define IPS_COMPAT_KEYWEST "KW710"
1197#define IPS_COMPAT_BIOS "KW710"
1198
1199#define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1200#define IPS_COMPAT_ID_LENGTH 8
1201
1202#define IPS_DEFINE_COMPAT_TABLE(tablename) \
1203 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1204 IPS_COMPAT_UNKNOWN, \
1205 IPS_COMPAT_SERVERAID1, \
1206 IPS_COMPAT_SERVERAID2, \
1207 IPS_COMPAT_NAVAJO, \
1208 IPS_COMPAT_KIOWA, \
1209 IPS_COMPAT_SERVERAID3H, \
1210 IPS_COMPAT_SERVERAID3L, \
1211 IPS_COMPAT_SERVERAID4H, \
1212 IPS_COMPAT_SERVERAID4M, \
1213 IPS_COMPAT_SERVERAID4L, \
1214 IPS_COMPAT_SERVERAID4Mx, \
1215 IPS_COMPAT_SERVERAID4Lx, \
1216 IPS_COMPAT_SARASOTA, \
1217 IPS_COMPAT_SARASOTA, \
1218 IPS_COMPAT_MARCO, \
1219 IPS_COMPAT_SEBRING, \
1220 IPS_COMPAT_TAMPA, \
1221 IPS_COMPAT_KEYWEST \
1222 }
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
