linux/drivers/spi/spi-tegra20-sflash.c
<<
>>
Prefs
   1/*
   2 * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
   3 *
   4 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5 *
   6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
   7 *
   8 * This program is free software; you can redistribute it and/or modify it
   9 * under the terms and conditions of the GNU General Public License,
  10 * version 2, as published by the Free Software Foundation.
  11 *
  12 * This program is distributed in the hope it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15 * more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/completion.h>
  23#include <linux/delay.h>
  24#include <linux/err.h>
  25#include <linux/interrupt.h>
  26#include <linux/io.h>
  27#include <linux/kernel.h>
  28#include <linux/kthread.h>
  29#include <linux/module.h>
  30#include <linux/platform_device.h>
  31#include <linux/pm_runtime.h>
  32#include <linux/of.h>
  33#include <linux/of_device.h>
  34#include <linux/reset.h>
  35#include <linux/spi/spi.h>
  36
  37#define SPI_COMMAND                             0x000
  38#define SPI_GO                                  BIT(30)
  39#define SPI_M_S                                 BIT(28)
  40#define SPI_ACTIVE_SCLK_MASK                    (0x3 << 26)
  41#define SPI_ACTIVE_SCLK_DRIVE_LOW               (0 << 26)
  42#define SPI_ACTIVE_SCLK_DRIVE_HIGH              (1 << 26)
  43#define SPI_ACTIVE_SCLK_PULL_LOW                (2 << 26)
  44#define SPI_ACTIVE_SCLK_PULL_HIGH               (3 << 26)
  45
  46#define SPI_CK_SDA_FALLING                      (1 << 21)
  47#define SPI_CK_SDA_RISING                       (0 << 21)
  48#define SPI_CK_SDA_MASK                         (1 << 21)
  49#define SPI_ACTIVE_SDA                          (0x3 << 18)
  50#define SPI_ACTIVE_SDA_DRIVE_LOW                (0 << 18)
  51#define SPI_ACTIVE_SDA_DRIVE_HIGH               (1 << 18)
  52#define SPI_ACTIVE_SDA_PULL_LOW                 (2 << 18)
  53#define SPI_ACTIVE_SDA_PULL_HIGH                (3 << 18)
  54
  55#define SPI_CS_POL_INVERT                       BIT(16)
  56#define SPI_TX_EN                               BIT(15)
  57#define SPI_RX_EN                               BIT(14)
  58#define SPI_CS_VAL_HIGH                         BIT(13)
  59#define SPI_CS_VAL_LOW                          0x0
  60#define SPI_CS_SW                               BIT(12)
  61#define SPI_CS_HW                               0x0
  62#define SPI_CS_DELAY_MASK                       (7 << 9)
  63#define SPI_CS3_EN                              BIT(8)
  64#define SPI_CS2_EN                              BIT(7)
  65#define SPI_CS1_EN                              BIT(6)
  66#define SPI_CS0_EN                              BIT(5)
  67
  68#define SPI_CS_MASK                     (SPI_CS3_EN | SPI_CS2_EN |      \
  69                                        SPI_CS1_EN | SPI_CS0_EN)
  70#define SPI_BIT_LENGTH(x)               (((x) & 0x1f) << 0)
  71
  72#define SPI_MODES                       (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
  73
  74#define SPI_STATUS                      0x004
  75#define SPI_BSY                         BIT(31)
  76#define SPI_RDY                         BIT(30)
  77#define SPI_TXF_FLUSH                   BIT(29)
  78#define SPI_RXF_FLUSH                   BIT(28)
  79#define SPI_RX_UNF                      BIT(27)
  80#define SPI_TX_OVF                      BIT(26)
  81#define SPI_RXF_EMPTY                   BIT(25)
  82#define SPI_RXF_FULL                    BIT(24)
  83#define SPI_TXF_EMPTY                   BIT(23)
  84#define SPI_TXF_FULL                    BIT(22)
  85#define SPI_BLK_CNT(count)              (((count) & 0xffff) + 1)
  86
  87#define SPI_FIFO_ERROR                  (SPI_RX_UNF | SPI_TX_OVF)
  88#define SPI_FIFO_EMPTY                  (SPI_TX_EMPTY | SPI_RX_EMPTY)
  89
  90#define SPI_RX_CMP                      0x8
  91#define SPI_DMA_CTL                     0x0C
  92#define SPI_DMA_EN                      BIT(31)
  93#define SPI_IE_RXC                      BIT(27)
  94#define SPI_IE_TXC                      BIT(26)
  95#define SPI_PACKED                      BIT(20)
  96#define SPI_RX_TRIG_MASK                (0x3 << 18)
  97#define SPI_RX_TRIG_1W                  (0x0 << 18)
  98#define SPI_RX_TRIG_4W                  (0x1 << 18)
  99#define SPI_TX_TRIG_MASK                (0x3 << 16)
 100#define SPI_TX_TRIG_1W                  (0x0 << 16)
 101#define SPI_TX_TRIG_4W                  (0x1 << 16)
 102#define SPI_DMA_BLK_COUNT(count)        (((count) - 1) & 0xFFFF)
 103
 104#define SPI_TX_FIFO                     0x10
 105#define SPI_RX_FIFO                     0x20
 106
 107#define DATA_DIR_TX                     (1 << 0)
 108#define DATA_DIR_RX                     (1 << 1)
 109
 110#define MAX_CHIP_SELECT                 4
 111#define SPI_FIFO_DEPTH                  4
 112#define SPI_DMA_TIMEOUT               (msecs_to_jiffies(1000))
 113
 114struct tegra_sflash_data {
 115        struct device                           *dev;
 116        struct spi_master                       *master;
 117        spinlock_t                              lock;
 118
 119        struct clk                              *clk;
 120        struct reset_control                    *rst;
 121        void __iomem                            *base;
 122        unsigned                                irq;
 123        u32                                     cur_speed;
 124
 125        struct spi_device                       *cur_spi;
 126        unsigned                                cur_pos;
 127        unsigned                                cur_len;
 128        unsigned                                bytes_per_word;
 129        unsigned                                cur_direction;
 130        unsigned                                curr_xfer_words;
 131
 132        unsigned                                cur_rx_pos;
 133        unsigned                                cur_tx_pos;
 134
 135        u32                                     tx_status;
 136        u32                                     rx_status;
 137        u32                                     status_reg;
 138
 139        u32                                     def_command_reg;
 140        u32                                     command_reg;
 141        u32                                     dma_control_reg;
 142
 143        struct completion                       xfer_completion;
 144        struct spi_transfer                     *curr_xfer;
 145};
 146
 147static int tegra_sflash_runtime_suspend(struct device *dev);
 148static int tegra_sflash_runtime_resume(struct device *dev);
 149
 150static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
 151                unsigned long reg)
 152{
 153        return readl(tsd->base + reg);
 154}
 155
 156static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
 157                u32 val, unsigned long reg)
 158{
 159        writel(val, tsd->base + reg);
 160}
 161
 162static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
 163{
 164        /* Write 1 to clear status register */
 165        tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
 166}
 167
 168static unsigned tegra_sflash_calculate_curr_xfer_param(
 169        struct spi_device *spi, struct tegra_sflash_data *tsd,
 170        struct spi_transfer *t)
 171{
 172        unsigned remain_len = t->len - tsd->cur_pos;
 173        unsigned max_word;
 174
 175        tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
 176        max_word = remain_len / tsd->bytes_per_word;
 177        if (max_word > SPI_FIFO_DEPTH)
 178                max_word = SPI_FIFO_DEPTH;
 179        tsd->curr_xfer_words = max_word;
 180        return max_word;
 181}
 182
 183static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
 184        struct tegra_sflash_data *tsd, struct spi_transfer *t)
 185{
 186        unsigned nbytes;
 187        u32 status;
 188        unsigned max_n_32bit = tsd->curr_xfer_words;
 189        u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
 190
 191        if (max_n_32bit > SPI_FIFO_DEPTH)
 192                max_n_32bit = SPI_FIFO_DEPTH;
 193        nbytes = max_n_32bit * tsd->bytes_per_word;
 194
 195        status = tegra_sflash_readl(tsd, SPI_STATUS);
 196        while (!(status & SPI_TXF_FULL)) {
 197                int i;
 198                u32 x = 0;
 199
 200                for (i = 0; nbytes && (i < tsd->bytes_per_word);
 201                                                        i++, nbytes--)
 202                        x |= (u32)(*tx_buf++) << (i * 8);
 203                tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
 204                if (!nbytes)
 205                        break;
 206
 207                status = tegra_sflash_readl(tsd, SPI_STATUS);
 208        }
 209        tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
 210        return max_n_32bit;
 211}
 212
 213static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
 214                struct tegra_sflash_data *tsd, struct spi_transfer *t)
 215{
 216        u32 status;
 217        unsigned int read_words = 0;
 218        u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
 219
 220        status = tegra_sflash_readl(tsd, SPI_STATUS);
 221        while (!(status & SPI_RXF_EMPTY)) {
 222                int i;
 223                u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
 224
 225                for (i = 0; (i < tsd->bytes_per_word); i++)
 226                        *rx_buf++ = (x >> (i*8)) & 0xFF;
 227                read_words++;
 228                status = tegra_sflash_readl(tsd, SPI_STATUS);
 229        }
 230        tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
 231        return 0;
 232}
 233
 234static int tegra_sflash_start_cpu_based_transfer(
 235                struct tegra_sflash_data *tsd, struct spi_transfer *t)
 236{
 237        u32 val = 0;
 238        unsigned cur_words;
 239
 240        if (tsd->cur_direction & DATA_DIR_TX)
 241                val |= SPI_IE_TXC;
 242
 243        if (tsd->cur_direction & DATA_DIR_RX)
 244                val |= SPI_IE_RXC;
 245
 246        tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 247        tsd->dma_control_reg = val;
 248
 249        if (tsd->cur_direction & DATA_DIR_TX)
 250                cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
 251        else
 252                cur_words = tsd->curr_xfer_words;
 253        val |= SPI_DMA_BLK_COUNT(cur_words);
 254        tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 255        tsd->dma_control_reg = val;
 256        val |= SPI_DMA_EN;
 257        tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 258        return 0;
 259}
 260
 261static int tegra_sflash_start_transfer_one(struct spi_device *spi,
 262                struct spi_transfer *t, bool is_first_of_msg,
 263                bool is_single_xfer)
 264{
 265        struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
 266        u32 speed;
 267        u32 command;
 268
 269        speed = t->speed_hz;
 270        if (speed != tsd->cur_speed) {
 271                clk_set_rate(tsd->clk, speed);
 272                tsd->cur_speed = speed;
 273        }
 274
 275        tsd->cur_spi = spi;
 276        tsd->cur_pos = 0;
 277        tsd->cur_rx_pos = 0;
 278        tsd->cur_tx_pos = 0;
 279        tsd->curr_xfer = t;
 280        tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
 281        if (is_first_of_msg) {
 282                command = tsd->def_command_reg;
 283                command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
 284                command |= SPI_CS_VAL_HIGH;
 285
 286                command &= ~SPI_MODES;
 287                if (spi->mode & SPI_CPHA)
 288                        command |= SPI_CK_SDA_FALLING;
 289
 290                if (spi->mode & SPI_CPOL)
 291                        command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
 292                else
 293                        command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
 294                command |= SPI_CS0_EN << spi->chip_select;
 295        } else {
 296                command = tsd->command_reg;
 297                command &= ~SPI_BIT_LENGTH(~0);
 298                command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
 299                command &= ~(SPI_RX_EN | SPI_TX_EN);
 300        }
 301
 302        tsd->cur_direction = 0;
 303        if (t->rx_buf) {
 304                command |= SPI_RX_EN;
 305                tsd->cur_direction |= DATA_DIR_RX;
 306        }
 307        if (t->tx_buf) {
 308                command |= SPI_TX_EN;
 309                tsd->cur_direction |= DATA_DIR_TX;
 310        }
 311        tegra_sflash_writel(tsd, command, SPI_COMMAND);
 312        tsd->command_reg = command;
 313
 314        return tegra_sflash_start_cpu_based_transfer(tsd, t);
 315}
 316
 317static int tegra_sflash_transfer_one_message(struct spi_master *master,
 318                        struct spi_message *msg)
 319{
 320        bool is_first_msg = true;
 321        int single_xfer;
 322        struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 323        struct spi_transfer *xfer;
 324        struct spi_device *spi = msg->spi;
 325        int ret;
 326
 327        msg->status = 0;
 328        msg->actual_length = 0;
 329        single_xfer = list_is_singular(&msg->transfers);
 330        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 331                reinit_completion(&tsd->xfer_completion);
 332                ret = tegra_sflash_start_transfer_one(spi, xfer,
 333                                        is_first_msg, single_xfer);
 334                if (ret < 0) {
 335                        dev_err(tsd->dev,
 336                                "spi can not start transfer, err %d\n", ret);
 337                        goto exit;
 338                }
 339                is_first_msg = false;
 340                ret = wait_for_completion_timeout(&tsd->xfer_completion,
 341                                                SPI_DMA_TIMEOUT);
 342                if (WARN_ON(ret == 0)) {
 343                        dev_err(tsd->dev,
 344                                "spi transfer timeout, err %d\n", ret);
 345                        ret = -EIO;
 346                        goto exit;
 347                }
 348
 349                if (tsd->tx_status ||  tsd->rx_status) {
 350                        dev_err(tsd->dev, "Error in Transfer\n");
 351                        ret = -EIO;
 352                        goto exit;
 353                }
 354                msg->actual_length += xfer->len;
 355                if (xfer->cs_change && xfer->delay_usecs) {
 356                        tegra_sflash_writel(tsd, tsd->def_command_reg,
 357                                        SPI_COMMAND);
 358                        udelay(xfer->delay_usecs);
 359                }
 360        }
 361        ret = 0;
 362exit:
 363        tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
 364        msg->status = ret;
 365        spi_finalize_current_message(master);
 366        return ret;
 367}
 368
 369static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
 370{
 371        struct spi_transfer *t = tsd->curr_xfer;
 372        unsigned long flags;
 373
 374        spin_lock_irqsave(&tsd->lock, flags);
 375        if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
 376                dev_err(tsd->dev,
 377                        "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
 378                dev_err(tsd->dev,
 379                        "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
 380                                tsd->dma_control_reg);
 381                reset_control_assert(tsd->rst);
 382                udelay(2);
 383                reset_control_deassert(tsd->rst);
 384                complete(&tsd->xfer_completion);
 385                goto exit;
 386        }
 387
 388        if (tsd->cur_direction & DATA_DIR_RX)
 389                tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
 390
 391        if (tsd->cur_direction & DATA_DIR_TX)
 392                tsd->cur_pos = tsd->cur_tx_pos;
 393        else
 394                tsd->cur_pos = tsd->cur_rx_pos;
 395
 396        if (tsd->cur_pos == t->len) {
 397                complete(&tsd->xfer_completion);
 398                goto exit;
 399        }
 400
 401        tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
 402        tegra_sflash_start_cpu_based_transfer(tsd, t);
 403exit:
 404        spin_unlock_irqrestore(&tsd->lock, flags);
 405        return IRQ_HANDLED;
 406}
 407
 408static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
 409{
 410        struct tegra_sflash_data *tsd = context_data;
 411
 412        tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
 413        if (tsd->cur_direction & DATA_DIR_TX)
 414                tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
 415
 416        if (tsd->cur_direction & DATA_DIR_RX)
 417                tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
 418        tegra_sflash_clear_status(tsd);
 419
 420        return handle_cpu_based_xfer(tsd);
 421}
 422
 423static const struct of_device_id tegra_sflash_of_match[] = {
 424        { .compatible = "nvidia,tegra20-sflash", },
 425        {}
 426};
 427MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
 428
 429static int tegra_sflash_probe(struct platform_device *pdev)
 430{
 431        struct spi_master       *master;
 432        struct tegra_sflash_data        *tsd;
 433        struct resource         *r;
 434        int ret;
 435        const struct of_device_id *match;
 436
 437        match = of_match_device(tegra_sflash_of_match, &pdev->dev);
 438        if (!match) {
 439                dev_err(&pdev->dev, "Error: No device match found\n");
 440                return -ENODEV;
 441        }
 442
 443        master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
 444        if (!master) {
 445                dev_err(&pdev->dev, "master allocation failed\n");
 446                return -ENOMEM;
 447        }
 448
 449        /* the spi->mode bits understood by this driver: */
 450        master->mode_bits = SPI_CPOL | SPI_CPHA;
 451        master->transfer_one_message = tegra_sflash_transfer_one_message;
 452        master->auto_runtime_pm = true;
 453        master->num_chipselect = MAX_CHIP_SELECT;
 454
 455        platform_set_drvdata(pdev, master);
 456        tsd = spi_master_get_devdata(master);
 457        tsd->master = master;
 458        tsd->dev = &pdev->dev;
 459        spin_lock_init(&tsd->lock);
 460
 461        if (of_property_read_u32(tsd->dev->of_node, "spi-max-frequency",
 462                                 &master->max_speed_hz))
 463                master->max_speed_hz = 25000000; /* 25MHz */
 464
 465        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 466        tsd->base = devm_ioremap_resource(&pdev->dev, r);
 467        if (IS_ERR(tsd->base)) {
 468                ret = PTR_ERR(tsd->base);
 469                goto exit_free_master;
 470        }
 471
 472        tsd->irq = platform_get_irq(pdev, 0);
 473        ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
 474                        dev_name(&pdev->dev), tsd);
 475        if (ret < 0) {
 476                dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
 477                                        tsd->irq);
 478                goto exit_free_master;
 479        }
 480
 481        tsd->clk = devm_clk_get(&pdev->dev, NULL);
 482        if (IS_ERR(tsd->clk)) {
 483                dev_err(&pdev->dev, "can not get clock\n");
 484                ret = PTR_ERR(tsd->clk);
 485                goto exit_free_irq;
 486        }
 487
 488        tsd->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
 489        if (IS_ERR(tsd->rst)) {
 490                dev_err(&pdev->dev, "can not get reset\n");
 491                ret = PTR_ERR(tsd->rst);
 492                goto exit_free_irq;
 493        }
 494
 495        init_completion(&tsd->xfer_completion);
 496        pm_runtime_enable(&pdev->dev);
 497        if (!pm_runtime_enabled(&pdev->dev)) {
 498                ret = tegra_sflash_runtime_resume(&pdev->dev);
 499                if (ret)
 500                        goto exit_pm_disable;
 501        }
 502
 503        ret = pm_runtime_get_sync(&pdev->dev);
 504        if (ret < 0) {
 505                dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
 506                goto exit_pm_disable;
 507        }
 508
 509        /* Reset controller */
 510        reset_control_assert(tsd->rst);
 511        udelay(2);
 512        reset_control_deassert(tsd->rst);
 513
 514        tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;
 515        tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
 516        pm_runtime_put(&pdev->dev);
 517
 518        master->dev.of_node = pdev->dev.of_node;
 519        ret = devm_spi_register_master(&pdev->dev, master);
 520        if (ret < 0) {
 521                dev_err(&pdev->dev, "can not register to master err %d\n", ret);
 522                goto exit_pm_disable;
 523        }
 524        return ret;
 525
 526exit_pm_disable:
 527        pm_runtime_disable(&pdev->dev);
 528        if (!pm_runtime_status_suspended(&pdev->dev))
 529                tegra_sflash_runtime_suspend(&pdev->dev);
 530exit_free_irq:
 531        free_irq(tsd->irq, tsd);
 532exit_free_master:
 533        spi_master_put(master);
 534        return ret;
 535}
 536
 537static int tegra_sflash_remove(struct platform_device *pdev)
 538{
 539        struct spi_master *master = platform_get_drvdata(pdev);
 540        struct tegra_sflash_data        *tsd = spi_master_get_devdata(master);
 541
 542        free_irq(tsd->irq, tsd);
 543
 544        pm_runtime_disable(&pdev->dev);
 545        if (!pm_runtime_status_suspended(&pdev->dev))
 546                tegra_sflash_runtime_suspend(&pdev->dev);
 547
 548        return 0;
 549}
 550
 551#ifdef CONFIG_PM_SLEEP
 552static int tegra_sflash_suspend(struct device *dev)
 553{
 554        struct spi_master *master = dev_get_drvdata(dev);
 555
 556        return spi_master_suspend(master);
 557}
 558
 559static int tegra_sflash_resume(struct device *dev)
 560{
 561        struct spi_master *master = dev_get_drvdata(dev);
 562        struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 563        int ret;
 564
 565        ret = pm_runtime_get_sync(dev);
 566        if (ret < 0) {
 567                dev_err(dev, "pm runtime failed, e = %d\n", ret);
 568                return ret;
 569        }
 570        tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
 571        pm_runtime_put(dev);
 572
 573        return spi_master_resume(master);
 574}
 575#endif
 576
 577static int tegra_sflash_runtime_suspend(struct device *dev)
 578{
 579        struct spi_master *master = dev_get_drvdata(dev);
 580        struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 581
 582        /* Flush all write which are in PPSB queue by reading back */
 583        tegra_sflash_readl(tsd, SPI_COMMAND);
 584
 585        clk_disable_unprepare(tsd->clk);
 586        return 0;
 587}
 588
 589static int tegra_sflash_runtime_resume(struct device *dev)
 590{
 591        struct spi_master *master = dev_get_drvdata(dev);
 592        struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 593        int ret;
 594
 595        ret = clk_prepare_enable(tsd->clk);
 596        if (ret < 0) {
 597                dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
 598                return ret;
 599        }
 600        return 0;
 601}
 602
 603static const struct dev_pm_ops slink_pm_ops = {
 604        SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
 605                tegra_sflash_runtime_resume, NULL)
 606        SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
 607};
 608static struct platform_driver tegra_sflash_driver = {
 609        .driver = {
 610                .name           = "spi-tegra-sflash",
 611                .pm             = &slink_pm_ops,
 612                .of_match_table = tegra_sflash_of_match,
 613        },
 614        .probe =        tegra_sflash_probe,
 615        .remove =       tegra_sflash_remove,
 616};
 617module_platform_driver(tegra_sflash_driver);
 618
 619MODULE_ALIAS("platform:spi-tegra-sflash");
 620MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
 621MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
 622MODULE_LICENSE("GPL v2");
 623