LXR linux/drivers/staging/rtl8192u/r8192U.h

   1/*
   2 * This is part of rtl8187 OpenSource driver.
   3 * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   4 * Released under the terms of GPL (General Public Licence)
   5 *
   6 * Parts of this driver are based on the GPL part of the
   7 * official realtek driver
   8 *
   9 * Parts of this driver are based on the rtl8192 driver skeleton
  10 * from Patric Schenke & Andres Salomon
  11 *
  12 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13 *
  14 * We want to thank the Authors of those projects and the Ndiswrapper
  15 * project Authors.
  16 */
  17
  18#ifndef R8192U_H
  19#define R8192U_H
  20
  21#include <linux/compiler.h>
  22#include <linux/module.h>
  23#include <linux/kernel.h>
  24#include <linux/ioport.h>
  25#include <linux/sched.h>
  26#include <linux/types.h>
  27#include <linux/slab.h>
  28#include <linux/netdevice.h>
  29#include <linux/usb.h>
  30#include <linux/etherdevice.h>
  31#include <linux/delay.h>
  32#include <linux/rtnetlink.h>
  33#include <linux/wireless.h>
  34#include <linux/timer.h>
  35#include <linux/proc_fs.h>
  36#include <linux/if_arp.h>
  37#include <linux/random.h>
  38#include <linux/io.h>
  39#include "ieee80211/ieee80211.h"
  40
  41#define RTL8192U
  42#define RTL819xU_MODULE_NAME "rtl819xU"
  43/* HW security */
  44#define MAX_KEY_LEN     61
  45#define KEY_BUF_SIZE    5
  46
  47#define Rx_Smooth_Factor                20
  48#define DMESG(x, a...)
  49#define DMESGW(x, a...)
  50#define DMESGE(x, a...)
  51extern u32 rt_global_debug_component;
  52#define RT_TRACE(component, x, args...) \
  53        do {                                                    \
  54                if (rt_global_debug_component & component)      \
  55                        pr_debug("RTL8192U: " x "\n", ##args);  \
  56        } while (0)
  57
  58#define COMP_TRACE              BIT(0)  /* Function call tracing. */
  59#define COMP_DBG                BIT(1)
  60#define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */
  61
  62#define COMP_RECV               BIT(3)  /* Receive data path. */
  63#define COMP_SEND               BIT(4)  /* Send data path. */
  64#define COMP_IO                 BIT(5)
  65/* 802.11 Power Save mode or System/Device Power state. */
  66#define COMP_POWER              BIT(6)
  67/* 802.11 link related: join/start BSS, leave BSS. */
  68#define COMP_EPROM              BIT(7)
  69#define COMP_SWBW               BIT(8)  /* Bandwidth switch. */
  70#define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */
  71#define COMP_TURBO              BIT(10) /* Turbo Mode */
  72#define COMP_QOS                BIT(11)
  73#define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */
  74#define COMP_RM                 BIT(13) /* Radio Measurement */
  75#define COMP_DIG                BIT(14)
  76#define COMP_PHY                BIT(15)
  77#define COMP_CH                 BIT(16) /* Channel setting debug */
  78#define COMP_TXAGC              BIT(17) /* Tx power */
  79#define COMP_HIPWR              BIT(18) /* High Power Mechanism */
  80#define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */
  81#define COMP_SEC                BIT(20) /* Event handling */
  82#define COMP_LED                BIT(21)
  83#define COMP_RF                 BIT(22)
  84#define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */
  85
  86/* 11n or 8190 specific code */
  87
  88#define COMP_FIRMWARE           BIT(24) /* Firmware downloading */
  89#define COMP_HT                 BIT(25) /* 802.11n HT related information */
  90#define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */
  91#define COMP_SCAN               BIT(27)
  92#define COMP_DOWN               BIT(29) /* rm driver module */
  93#define COMP_RESET              BIT(30) /* Silent reset */
  94#define COMP_ERR                BIT(31) /* Error out, always on */
  95
  96#define RTL819x_DEBUG
  97#ifdef RTL819x_DEBUG
  98#define RTL8192U_ASSERT(expr) \
  99        do {                                                            \
 100                if (!(expr)) {                                          \
 101                        pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 102                                 #expr, __FILE__, __func__, __LINE__);  \
 103                }                                                       \
 104        } while (0)
 105/*
 106 * Debug out data buf.
 107 * If you want to print DATA buffer related BA,
 108 * please set ieee80211_debug_level to DATA|BA
 109 */
 110#define RT_DEBUG_DATA(level, data, datalen) \
 111        do {                                                            \
 112                if ((rt_global_debug_component & (level)) == (level)) { \
 113                        int i;                                          \
 114                        u8 *pdata = (u8 *) data;                        \
 115                        pr_debug("RTL8192U: %s()\n", __func__);         \
 116                        for (i = 0; i < (int)(datalen); i++) {          \
 117                                printk("%2x ", pdata[i]);               \
 118                                if ((i+1)%16 == 0)                      \
 119                                        printk("\n");                   \
 120                        }                                               \
 121                        printk("\n");                                   \
 122                }                                                       \
 123        } while (0)
 124#else
 125#define RTL8192U_ASSERT(expr) do {} while (0)
 126#define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 127#endif /* RTL8169_DEBUG */
 128
 129/* Queue Select Value in TxDesc */
 130#define QSLT_BK                                 0x1
 131#define QSLT_BE                                 0x0
 132#define QSLT_VI                                 0x4
 133#define QSLT_VO                                 0x6
 134#define QSLT_BEACON                             0x10
 135#define QSLT_HIGH                               0x11
 136#define QSLT_MGNT                               0x12
 137#define QSLT_CMD                                0x13
 138
 139#define DESC90_RATE1M                           0x00
 140#define DESC90_RATE2M                           0x01
 141#define DESC90_RATE5_5M                         0x02
 142#define DESC90_RATE11M                          0x03
 143#define DESC90_RATE6M                           0x04
 144#define DESC90_RATE9M                           0x05
 145#define DESC90_RATE12M                          0x06
 146#define DESC90_RATE18M                          0x07
 147#define DESC90_RATE24M                          0x08
 148#define DESC90_RATE36M                          0x09
 149#define DESC90_RATE48M                          0x0a
 150#define DESC90_RATE54M                          0x0b
 151#define DESC90_RATEMCS0                         0x00
 152#define DESC90_RATEMCS1                         0x01
 153#define DESC90_RATEMCS2                         0x02
 154#define DESC90_RATEMCS3                         0x03
 155#define DESC90_RATEMCS4                         0x04
 156#define DESC90_RATEMCS5                         0x05
 157#define DESC90_RATEMCS6                         0x06
 158#define DESC90_RATEMCS7                         0x07
 159#define DESC90_RATEMCS8                         0x08
 160#define DESC90_RATEMCS9                         0x09
 161#define DESC90_RATEMCS10                        0x0a
 162#define DESC90_RATEMCS11                        0x0b
 163#define DESC90_RATEMCS12                        0x0c
 164#define DESC90_RATEMCS13                        0x0d
 165#define DESC90_RATEMCS14                        0x0e
 166#define DESC90_RATEMCS15                        0x0f
 167#define DESC90_RATEMCS32                        0x20
 168
 169#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 170
 171#define IEEE80211_WATCH_DOG_TIME    2000
 172#define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 173/* For Tx Power Tracking */
 174#define         OFDM_Table_Length       19
 175#define CCK_Table_length        12
 176
 177/* For rtl819x */
 178struct tx_desc_819x_usb {
 179        /* DWORD 0 */
 180        u16     PktSize;
 181        u8      Offset;
 182        u8      Reserved0:3;
 183        u8      CmdInit:1;
 184        u8      LastSeg:1;
 185        u8      FirstSeg:1;
 186        u8      LINIP:1;
 187        u8      OWN:1;
 188
 189        /* DWORD 1 */
 190        u8      TxFWInfoSize;
 191        u8      RATid:3;
 192        u8      DISFB:1;
 193        u8      USERATE:1;
 194        u8      MOREFRAG:1;
 195        u8      NoEnc:1;
 196        u8      PIFS:1;
 197        u8      QueueSelect:5;
 198        u8      NoACM:1;
 199        u8      Reserved1:2;
 200        u8      SecCAMID:5;
 201        u8      SecDescAssign:1;
 202        u8      SecType:2;
 203
 204        /* DWORD 2 */
 205        u16     TxBufferSize;
 206        u8      ResvForPaddingLen:7;
 207        u8      Reserved3:1;
 208        u8      Reserved4;
 209
 210        /* DWORD 3, 4, 5 */
 211        u32     Reserved5;
 212        u32     Reserved6;
 213        u32     Reserved7;
 214};
 215
 216struct tx_desc_cmd_819x_usb {
 217        /* DWORD 0 */
 218        u16     Reserved0;
 219        u8      Reserved1;
 220        u8      Reserved2:3;
 221        u8      CmdInit:1;
 222        u8      LastSeg:1;
 223        u8      FirstSeg:1;
 224        u8      LINIP:1;
 225        u8      OWN:1;
 226
 227        /* DOWRD 1 */
 228        u8      TxFWInfoSize;
 229        u8      Reserved3;
 230        u8      QueueSelect;
 231        u8      Reserved4;
 232
 233        /* DOWRD 2 */
 234        u16     TxBufferSize;
 235        u16     Reserved5;
 236
 237        /* DWORD 3, 4, 5 */
 238        u32     Reserved6;
 239        u32     Reserved7;
 240        u32     Reserved8;
 241};
 242
 243struct tx_fwinfo_819x_usb {
 244        /* DOWRD 0 */
 245        u8      TxRate:7;
 246        u8      CtsEnable:1;
 247        u8      RtsRate:7;
 248        u8      RtsEnable:1;
 249        u8      TxHT:1;
 250        u8      Short:1;        /* Error out, always on */
 251        u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 252        u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 253        u8      STBC:2;
 254        u8      AllowAggregation:1;
 255        /* Interpret RtsRate field as high throughput data rate */
 256        u8      RtsHT:1;
 257        u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 258        u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 259        u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 260        u8      RtsSTBC:2;
 261        /* Enable firmware to recalculate and assign packet duration */
 262        u8      EnableCPUDur:1;
 263
 264        /* DWORD 1 */
 265        u32     RxMF:2;
 266        u32     RxAMD:3;
 267        /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 268        u32     TxPerPktInfoFeedback:1;
 269        u32     Reserved1:2;
 270        u32     TxAGCOffSet:4;
 271        u32     TxAGCSign:1;
 272        u32     Tx_INFO_RSVD:6;
 273        u32     PacketID:13;
 274};
 275
 276struct rtl8192_rx_info {
 277        struct urb *urb;
 278        struct net_device *dev;
 279        u8 out_pipe;
 280};
 281
 282struct rx_desc_819x_usb {
 283        /* DOWRD 0 */
 284        u16                 Length:14;
 285        u16                 CRC32:1;
 286        u16                 ICV:1;
 287        u8                  RxDrvInfoSize;
 288        u8                  Shift:2;
 289        u8                  PHYStatus:1;
 290        u8                  SWDec:1;
 291        u8                  Reserved1:4;
 292
 293        /* DWORD 1 */
 294        u32                 Reserved2;
 295};
 296
 297struct rx_drvinfo_819x_usb {
 298        /* DWORD 0 */
 299        u16                 Reserved1:12;
 300        u16                 PartAggr:1;
 301        u16                 FirstAGGR:1;
 302        u16                 Reserved2:2;
 303
 304        u8                  RxRate:7;
 305        u8                  RxHT:1;
 306
 307        u8                  BW:1;
 308        u8                  SPLCP:1;
 309        u8                  Reserved3:2;
 310        u8                  PAM:1;
 311        u8                  Mcast:1;
 312        u8                  Bcast:1;
 313        u8                  Reserved4:1;
 314
 315        /* DWORD 1 */
 316        u32                  TSFL;
 317
 318};
 319
 320/* Support till 64 bit bus width OS */
 321#define MAX_DEV_ADDR_SIZE               8
 322/* For RTL8190 */
 323#define MAX_FIRMWARE_INFORMATION_SIZE   32
 324#define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 325#define ENCRYPTION_MAX_OVERHEAD         128
 326#define USB_HWDESC_HEADER_LEN           sizeof(struct tx_desc_819x_usb)
 327#define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(struct tx_fwinfo_819x_usb))
 328#define MAX_FRAGMENT_COUNT              8
 329#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 330#define MAX_TRANSMIT_BUFFER_SIZE                        32000
 331#else
 332#define MAX_TRANSMIT_BUFFER_SIZE                        8000
 333#endif
 334/* Octets for crc32 (FCS, ICV) */
 335#define scrclng                                 4
 336
 337enum rf_op_type {
 338        RF_OP_By_SW_3wire = 0,
 339        RF_OP_By_FW,
 340        RF_OP_MAX
 341};
 342
 343/* 8190 Loopback Mode definition */
 344typedef enum _rtl819xUsb_loopback {
 345        RTL819xU_NO_LOOPBACK = 0,
 346        RTL819xU_MAC_LOOPBACK = 1,
 347        RTL819xU_DMA_LOOPBACK = 2,
 348        RTL819xU_CCK_LOOPBACK = 3,
 349} rtl819xUsb_loopback_e;
 350
 351/* due to rtl8192 firmware */
 352typedef enum _desc_packet_type_e {
 353        DESC_PACKET_TYPE_INIT = 0,
 354        DESC_PACKET_TYPE_NORMAL = 1,
 355} desc_packet_type_e;
 356
 357typedef enum _firmware_status {
 358        FW_STATUS_0_INIT = 0,
 359        FW_STATUS_1_MOVE_BOOT_CODE = 1,
 360        FW_STATUS_2_MOVE_MAIN_CODE = 2,
 361        FW_STATUS_3_TURNON_CPU = 3,
 362        FW_STATUS_4_MOVE_DATA_CODE = 4,
 363        FW_STATUS_5_READY = 5,
 364} firmware_status_e;
 365
 366typedef struct _rt_firmare_seg_container {
 367        u16     seg_size;
 368        u8      *seg_ptr;
 369} fw_seg_container, *pfw_seg_container;
 370typedef struct _rt_firmware {
 371        firmware_status_e firmware_status;
 372        u16               cmdpacket_frag_thresold;
 373#define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 374        u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 375        u16               firmware_buf_size;
 376} rt_firmware, *prt_firmware;
 377
 378/* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 379#define MAX_RECEIVE_BUFFER_SIZE 9100
 380
 381typedef struct _rt_firmware_info_819xUsb {
 382        u8              sz_info[16];
 383} rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 384
 385/* Firmware Queue Layout */
 386#define NUM_OF_FIRMWARE_QUEUE           10
 387#define NUM_OF_PAGES_IN_FW              0x100
 388
 389#ifdef USE_ONE_PIPE
 390#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 391#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 392#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 393#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 394#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 395#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 396#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 397#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 398#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 399#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 400#else
 401
 402#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 403#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 404#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 405#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 406#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 407#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 408#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 409#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 410#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 411#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 412
 413#endif
 414
 415#define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 416#define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 417#define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 418#define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 419#define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 420#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 421#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 422#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 423#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 424
 425/*
 426 * =================================================================
 427 * =================================================================
 428 */
 429
 430#define EPROM_93c46 0
 431#define EPROM_93c56 1
 432
 433#define DEFAULT_FRAG_THRESHOLD 2342U
 434#define MIN_FRAG_THRESHOLD     256U
 435#define DEFAULT_BEACONINTERVAL 0x64U
 436#define DEFAULT_BEACON_ESSID "Rtl819xU"
 437
 438#define DEFAULT_SSID ""
 439#define DEFAULT_RETRY_RTS 7
 440#define DEFAULT_RETRY_DATA 7
 441#define PRISM_HDR_SIZE 64
 442
 443#define         PHY_RSSI_SLID_WIN_MAX                           100
 444
 445typedef enum _WIRELESS_MODE {
 446        WIRELESS_MODE_UNKNOWN = 0x00,
 447        WIRELESS_MODE_A = 0x01,
 448        WIRELESS_MODE_B = 0x02,
 449        WIRELESS_MODE_G = 0x04,
 450        WIRELESS_MODE_AUTO = 0x08,
 451        WIRELESS_MODE_N_24G = 0x10,
 452        WIRELESS_MODE_N_5G = 0x20
 453} WIRELESS_MODE;
 454
 455#define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 456
 457typedef struct buffer {
 458        struct buffer *next;
 459        u32 *buf;
 460
 461} buffer;
 462
 463typedef struct rtl_reg_debug {
 464        unsigned int  cmd;
 465        struct {
 466                unsigned char type;
 467                unsigned char addr;
 468                unsigned char page;
 469                unsigned char length;
 470        } head;
 471        unsigned char buf[0xff];
 472} rtl_reg_debug;
 473
 474typedef struct _rt_9x_tx_rate_history {
 475        u32             cck[4];
 476        u32             ofdm[8];
 477        u32             ht_mcs[4][16];
 478} rt_tx_rahis_t, *prt_tx_rahis_t;
 479typedef struct _RT_SMOOTH_DATA_4RF {
 480        s8    elements[4][100]; /* array to store values */
 481        u32     index;            /* index to current array to store */
 482        u32     TotalNum;         /* num of valid elements */
 483        u32     TotalVal[4];      /* sum of valid elements */
 484} RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 485
 486/* This maybe changed for D-cut larger aggregation size */
 487#define MAX_8192U_RX_SIZE                       8192
 488/* Stats seems messed up, clean it ASAP */
 489typedef struct Stats {
 490        unsigned long txrdu;
 491        unsigned long rxok;
 492        unsigned long rxframgment;
 493        unsigned long rxurberr;
 494        unsigned long rxstaterr;
 495        /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 496        unsigned long received_rate_histogram[4][32];
 497        /* 0: Long preamble/GI, 1: Short preamble/GI */
 498        unsigned long received_preamble_GI[2][32];
 499        /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 500        unsigned long rx_AMPDUsize_histogram[5];
 501        /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 502        unsigned long rx_AMPDUnum_histogram[5];
 503        unsigned long numpacket_matchbssid;
 504        unsigned long numpacket_toself;
 505        unsigned long num_process_phyinfo;
 506        unsigned long numqry_phystatus;
 507        unsigned long numqry_phystatusCCK;
 508        unsigned long numqry_phystatusHT;
 509        /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 510        unsigned long received_bwtype[5];
 511        unsigned long txnperr;
 512        unsigned long txnpdrop;
 513        unsigned long txresumed;
 514        unsigned long txnpokint;
 515        unsigned long txoverflow;
 516        unsigned long txlpokint;
 517        unsigned long txlpdrop;
 518        unsigned long txlperr;
 519        unsigned long txbeokint;
 520        unsigned long txbedrop;
 521        unsigned long txbeerr;
 522        unsigned long txbkokint;
 523        unsigned long txbkdrop;
 524        unsigned long txbkerr;
 525        unsigned long txviokint;
 526        unsigned long txvidrop;
 527        unsigned long txvierr;
 528        unsigned long txvookint;
 529        unsigned long txvodrop;
 530        unsigned long txvoerr;
 531        unsigned long txbeaconokint;
 532        unsigned long txbeacondrop;
 533        unsigned long txbeaconerr;
 534        unsigned long txmanageokint;
 535        unsigned long txmanagedrop;
 536        unsigned long txmanageerr;
 537        unsigned long txdatapkt;
 538        unsigned long txfeedback;
 539        unsigned long txfeedbackok;
 540
 541        unsigned long txoktotal;
 542        unsigned long txokbytestotal;
 543        unsigned long txokinperiod;
 544        unsigned long txmulticast;
 545        unsigned long txbytesmulticast;
 546        unsigned long txbroadcast;
 547        unsigned long txbytesbroadcast;
 548        unsigned long txunicast;
 549        unsigned long txbytesunicast;
 550
 551        unsigned long rxoktotal;
 552        unsigned long rxbytesunicast;
 553        unsigned long txfeedbackfail;
 554        unsigned long txerrtotal;
 555        unsigned long txerrbytestotal;
 556        unsigned long txerrmulticast;
 557        unsigned long txerrbroadcast;
 558        unsigned long txerrunicast;
 559        unsigned long txretrycount;
 560        unsigned long txfeedbackretry;
 561        u8            last_packet_rate;
 562        unsigned long slide_signal_strength[100];
 563        unsigned long slide_evm[100];
 564        /* For recording sliding window's RSSI value */
 565        unsigned long slide_rssi_total;
 566        /* For recording sliding window's EVM value */
 567        unsigned long slide_evm_total;
 568        /* Transformed in dbm. Beautified signal strength for UI, not correct */
 569        long signal_strength;
 570        long signal_quality;
 571        long last_signal_strength_inpercent;
 572        /* Correct smoothed ss in dbm, only used in driver
 573         * to report real power now
 574         */
 575        long recv_signal_power;
 576        u8 rx_rssi_percentage[4];
 577        u8 rx_evm_percentage[2];
 578        long rxSNRdB[4];
 579        rt_tx_rahis_t txrate;
 580        /* For beacon RSSI */
 581        u32 Slide_Beacon_pwdb[100];
 582        u32 Slide_Beacon_Total;
 583        RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 584
 585        u32     CurrentShowTxate;
 586} Stats;
 587
 588/* Bandwidth Offset */
 589#define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 590#define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 591#define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 592
 593typedef struct  ChnlAccessSetting {
 594        u16 SIFS_Timer;
 595        u16 DIFS_Timer;
 596        u16 SlotTimeTimer;
 597        u16 EIFS_Timer;
 598        u16 CWminIndex;
 599        u16 CWmaxIndex;
 600} *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 601
 602typedef struct _BB_REGISTER_DEFINITION {
 603        /* set software control:        0x870~0x877 [8 bytes]  */
 604        u32 rfintfs;
 605        /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 606        u32 rfintfi;
 607        /* output data:                 0x860~0x86f [16 bytes] */
 608        u32 rfintfo;
 609        /* output enable:               0x860~0x86f [16 bytes] */
 610        u32 rfintfe;
 611        /* LSSI data:                   0x840~0x84f [16 bytes] */
 612        u32 rf3wireOffset;
 613        /* BB Band Select:              0x878~0x87f [8 bytes]  */
 614        u32 rfLSSI_Select;
 615        /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 616        u32 rfTxGainStage;
 617        /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 618         *                              0x830~0x833, 0x838~0x83b [16 bytes]
 619         */
 620        u32 rfHSSIPara1;
 621        /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 622         *                              0x834~0x837, 0x83c~0x83f [16 bytes]
 623         */
 624        u32 rfHSSIPara2;
 625        /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 626        u32 rfSwitchControl;
 627        /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 628         *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 629         */
 630        u32 rfAGCControl1;
 631        /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 632         *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 633         */
 634        u32 rfAGCControl2;
 635        /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 636         *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 637         */
 638        u32 rfRxIQImbalance;
 639        /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 640         *                              0xc10~0xc13, 0xc18~0xc1b,
 641         *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 642         */
 643        u32 rfRxAFE;
 644        /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 645         *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 646         */
 647        u32 rfTxIQImbalance;
 648        /* Tx IQ DC Offset and Tx DFIR type:
 649         *                              0xc84~0xc87, 0xc8c~0xc8f,
 650         *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 651         */
 652        u32 rfTxAFE;
 653        /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 654        u32 rfLSSIReadBack;
 655} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 656
 657typedef enum _RT_RF_TYPE_819xU {
 658        RF_TYPE_MIN = 0,
 659        RF_8225,
 660        RF_8256,
 661        RF_8258,
 662        RF_PSEUDO_11N = 4,
 663} RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 664
 665/* 2007/10/08 MH Define RATR state. */
 666enum dynamic_ratr_state {
 667        DM_RATR_STA_HIGH = 0,
 668        DM_RATR_STA_MIDDLE = 1,
 669        DM_RATR_STA_LOW = 2,
 670        DM_RATR_STA_MAX
 671};
 672
 673typedef struct _rate_adaptive {
 674        u8                              rate_adaptive_disabled;
 675        enum dynamic_ratr_state         ratr_state;
 676        u16                             reserve;
 677
 678        u32                             high_rssi_thresh_for_ra;
 679        u32                             high2low_rssi_thresh_for_ra;
 680        u8                              low2high_rssi_thresh_for_ra40M;
 681        u32                             low_rssi_thresh_for_ra40M;
 682        u8                              low2high_rssi_thresh_for_ra20M;
 683        u32                             low_rssi_thresh_for_ra20M;
 684        u32                             upper_rssi_threshold_ratr;
 685        u32                             middle_rssi_threshold_ratr;
 686        u32                             low_rssi_threshold_ratr;
 687        u32                             low_rssi_threshold_ratr_40M;
 688        u32                             low_rssi_threshold_ratr_20M;
 689        u8                              ping_rssi_enable;
 690        u32                             ping_rssi_ratr;
 691        u32                             ping_rssi_thresh_for_ra;
 692        u32                             last_ratr;
 693
 694} rate_adaptive, *prate_adaptive;
 695
 696#define TxBBGainTableLength 37
 697#define CCKTxBBGainTableLength 23
 698
 699typedef struct _txbbgain_struct {
 700        long    txbb_iq_amplifygain;
 701        u32     txbbgain_value;
 702} txbbgain_struct, *ptxbbgain_struct;
 703
 704typedef struct _ccktxbbgain_struct {
 705        /* The value is from a22 to a29, one byte one time is much safer */
 706        u8      ccktxbb_valuearray[8];
 707} ccktxbbgain_struct, *pccktxbbgain_struct;
 708
 709typedef struct _init_gain {
 710        u8                              xaagccore1;
 711        u8                              xbagccore1;
 712        u8                              xcagccore1;
 713        u8                              xdagccore1;
 714        u8                              cca;
 715
 716} init_gain, *pinit_gain;
 717
 718typedef struct _phy_ofdm_rx_status_report_819xusb {
 719        u8      trsw_gain_X[4];
 720        u8      pwdb_all;
 721        u8      cfosho_X[4];
 722        u8      cfotail_X[4];
 723        u8      rxevm_X[2];
 724        u8      rxsnr_X[4];
 725        u8      pdsnr_X[2];
 726        u8      csi_current_X[2];
 727        u8      csi_target_X[2];
 728        u8      sigevm;
 729        u8      max_ex_pwr;
 730        u8      sgi_en;
 731        u8  rxsc_sgien_exflg;
 732} phy_sts_ofdm_819xusb_t;
 733
 734typedef struct _phy_cck_rx_status_report_819xusb {
 735        /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 736         * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 737         * Range from -64~+63.5.
 738         */
 739        u8      adc_pwdb_X[4];
 740        u8      sq_rpt;
 741        u8      cck_agc_rpt;
 742} phy_sts_cck_819xusb_t;
 743
 744struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 745        u8                      reserved:4;
 746        u8                      rxsc:2;
 747        u8                      sgi_en:1;
 748        u8                      ex_intf_flag:1;
 749};
 750
 751typedef enum _RT_CUSTOMER_ID {
 752        RT_CID_DEFAULT = 0,
 753        RT_CID_8187_ALPHA0 = 1,
 754        RT_CID_8187_SERCOMM_PS = 2,
 755        RT_CID_8187_HW_LED = 3,
 756        RT_CID_8187_NETGEAR = 4,
 757        RT_CID_WHQL = 5,
 758        RT_CID_819x_CAMEO  = 6,
 759        RT_CID_819x_RUNTOP = 7,
 760        RT_CID_819x_Senao = 8,
 761        RT_CID_TOSHIBA = 9,
 762        RT_CID_819x_Netcore = 10,
 763        RT_CID_Nettronix = 11,
 764        RT_CID_DLINK = 12,
 765        RT_CID_PRONET = 13,
 766} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 767
 768/*
 769 * ==========================================================================
 770 * LED customization.
 771 * ==========================================================================
 772 */
 773
 774typedef enum _LED_STRATEGY_8190 {
 775        SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 776        SW_LED_MODE1, /* SW control for PCI Express */
 777        SW_LED_MODE2, /* SW control for Cameo. */
 778        SW_LED_MODE3, /* SW control for RunTop. */
 779        SW_LED_MODE4, /* SW control for Netcore. */
 780        /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 781        HW_LED,
 782} LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 783
 784typedef enum _RESET_TYPE {
 785        RESET_TYPE_NORESET = 0x00,
 786        RESET_TYPE_NORMAL = 0x01,
 787        RESET_TYPE_SILENT = 0x02
 788} RESET_TYPE;
 789
 790/* The simple tx command OP code. */
 791typedef enum _tag_TxCmd_Config_Index {
 792        TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 793        TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 794        TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 795        TXCMD_SET_TX_DURATION                           = 0xFF900003,
 796        TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 797        TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 798        TXCMD_XXXX_CTRL,
 799} DCMD_TXCMD_OP;
 800
 801typedef struct r8192_priv {
 802        struct usb_device *udev;
 803        /* For maintain info from eeprom */
 804        short epromtype;
 805        u16 eeprom_vid;
 806        u16 eeprom_pid;
 807        u8  eeprom_CustomerID;
 808        u8  eeprom_ChannelPlan;
 809        RT_CUSTOMER_ID CustomerID;
 810        LED_STRATEGY_8190       LedStrategy;
 811        u8  txqueue_to_outpipemap[9];
 812        int irq;
 813        struct ieee80211_device *ieee80211;
 814
 815        /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 816        short card_8192;
 817        /* If TCR reports card V B/C, this discriminates */
 818        u8 card_8192_version;
 819        short enable_gpio0;
 820        enum card_type {
 821                PCI, MINIPCI, CARDBUS, USB
 822        } card_type;
 823        short hw_plcp_len;
 824        short plcp_preamble_mode;
 825
 826        spinlock_t irq_lock;
 827        spinlock_t tx_lock;
 828        struct mutex mutex;
 829
 830        u16 irq_mask;
 831        short chan;
 832        short sens;
 833        short max_sens;
 834
 835        short up;
 836        /* If 1, allow bad crc frame, reception in monitor mode */
 837        short crcmon;
 838
 839        struct mutex wx_mutex;
 840
 841        u8 rf_type;                     /* 0: 1T2R, 1: 2T4R */
 842        RT_RF_TYPE_819xU rf_chip;
 843
 844        short (*rf_set_sens)(struct net_device *dev, short sens);
 845        u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 846        void (*rf_close)(struct net_device *dev);
 847        void (*rf_init)(struct net_device *dev);
 848        short promisc;
 849        /* Stats */
 850        struct Stats stats;
 851        struct iw_statistics wstats;
 852
 853        /* RX stuff */
 854        struct urb **rx_urb;
 855        struct urb **rx_cmd_urb;
 856#ifdef THOMAS_BEACON
 857        u32 *oldaddr;
 858#endif
 859#ifdef THOMAS_TASKLET
 860        atomic_t irt_counter; /* count for irq_rx_tasklet */
 861#endif
 862#ifdef JACKSON_NEW_RX
 863        struct sk_buff **pp_rxskb;
 864        int     rx_inx;
 865#endif
 866
 867       struct sk_buff_head rx_queue;
 868       struct sk_buff_head skb_queue;
 869       struct work_struct qos_activate;
 870        short  tx_urb_index;
 871        atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 872
 873        struct tasklet_struct irq_rx_tasklet;
 874        struct urb *rxurb_task;
 875
 876        /* Tx Related variables */
 877        u16     ShortRetryLimit;
 878        u16     LongRetryLimit;
 879        u32     TransmitConfig;
 880        u8      RegCWinMin;     /* For turbo mode CW adaptive */
 881
 882        u32     LastRxDescTSFHigh;
 883        u32     LastRxDescTSFLow;
 884
 885        /* Rx Related variables */
 886        u16     EarlyRxThreshold;
 887        u32     ReceiveConfig;
 888        u8      AcmControl;
 889
 890        u8      RFProgType;
 891
 892        u8 retry_data;
 893        u8 retry_rts;
 894        u16 rts;
 895
 896        struct  ChnlAccessSetting  ChannelAccessSetting;
 897        struct work_struct reset_wq;
 898
 899/**********************************************************/
 900        /* For rtl819xUsb */
 901        u16     basic_rate;
 902        u8      short_preamble;
 903        u8      slot_time;
 904        bool    bDcut;
 905        bool bCurrentRxAggrEnable;
 906        enum rf_op_type Rf_Mode;        /* For Firmware RF -R/W switch */
 907        prt_firmware            pFirmware;
 908        rtl819xUsb_loopback_e   LoopbackMode;
 909        u16 EEPROMTxPowerDiff;
 910        u8 EEPROMThermalMeter;
 911        u8 EEPROMPwDiff;
 912        u8 EEPROMCrystalCap;
 913        u8 EEPROM_Def_Ver;
 914        u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 915        u8 EEPROMTxPowerLevelCCK_V1[3];
 916        u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 917        u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
 918
 919        /* PHY related */
 920        BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
 921        /* Read/write are allow for following hardware information variables */
 922        u32     MCSTxPowerLevelOriginalOffset[6];
 923        u32     CCKTxPowerLevelOriginalOffset;
 924        u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
 925        u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
 926        u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
 927        u32     Pwr_Track;
 928        u8      TxPowerDiff;
 929        u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
 930        u8      CrystalCap;
 931        u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
 932
 933        u8      CckPwEnl;
 934        /* Use to calculate PWBD */
 935        u8      bCckHighPower;
 936        long    undecorated_smoothed_pwdb;
 937
 938        /* For set channel */
 939        u8      SwChnlInProgress;
 940        u8      SwChnlStage;
 941        u8      SwChnlStep;
 942        u8      SetBWModeInProgress;
 943        enum ht_channel_width   CurrentChannelBW;
 944        u8      ChannelPlan;
 945        /* 8190 40MHz mode */
 946        /* Control channel sub-carrier */
 947        u8      nCur40MhzPrimeSC;
 948        /* Test for shorten RF configuration time.
 949         * We save RF reg0 in this variable to reduce RF reading.
 950         */
 951        u32                                     RfReg0Value[4];
 952        u8                                      NumTotalRFPath;
 953        bool                            brfpath_rxenable[4];
 954        /* RF set related */
 955        bool                            SetRFPowerStateInProgress;
 956        struct timer_list watch_dog_timer;
 957
 958        /* For dynamic mechanism */
 959        /* Tx Power Control for Near/Far Range */
 960        bool    bdynamic_txpower;
 961        bool    bDynamicTxHighPower;
 962        bool    bDynamicTxLowPower;
 963        bool    bLastDTPFlag_High;
 964        bool    bLastDTPFlag_Low;
 965
 966        bool    bstore_last_dtpflag;
 967        /* Define to discriminate on High power State or
 968         * on sitesurvey to change Tx gain index
 969         */
 970        bool    bstart_txctrl_bydtp;
 971        rate_adaptive rate_adaptive;
 972        /* TX power tracking
 973         * OPEN/CLOSE TX POWER TRACKING
 974         */
 975        txbbgain_struct txbbgain_table[TxBBGainTableLength];
 976        u8              txpower_count; /* For 6 sec do tracking again */
 977        bool            btxpower_trackingInit;
 978        u8              OFDM_index;
 979        u8              CCK_index;
 980        /* CCK TX Power Tracking */
 981        ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
 982        ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
 983        u8 rfa_txpowertrackingindex;
 984        u8 rfa_txpowertrackingindex_real;
 985        u8 rfa_txpowertracking_default;
 986        u8 rfc_txpowertrackingindex;
 987        u8 rfc_txpowertrackingindex_real;
 988
 989        s8 cck_present_attenuation;
 990        u8 cck_present_attenuation_20Mdefault;
 991        u8 cck_present_attenuation_40Mdefault;
 992        s8 cck_present_attenuation_difference;
 993        bool btxpower_tracking;
 994        bool bcck_in_ch14;
 995        bool btxpowerdata_readfromEEPORM;
 996        u16     TSSI_13dBm;
 997        init_gain initgain_backup;
 998        u8 DefaultInitialGain[4];
 999        /* For EDCA Turbo mode */
1000        bool            bis_any_nonbepkts;

1001        bool            bcurrent_turbo_EDCA;
1002        bool            bis_cur_rdlstate;
1003        struct timer_list fsync_timer;
1004        bool bfsync_processing; /* 500ms Fsync timer is active or not */
1005        u32     rate_record;
1006        u32     rateCountDiffRecord;
1007        u32     ContinueDiffCount;
1008        bool bswitch_fsync;
1009
1010        u8      framesync;
1011        u32     framesyncC34;
1012        u8      framesyncMonitor;
1013        u16     nrxAMPDU_size;
1014        u8      nrxAMPDU_aggr_num;
1015
1016        /* For gpio */
1017         bool bHwRadioOff;
1018
1019        u32 reset_count;
1020        bool bpbc_pressed;
1021        u32 txpower_checkcnt;
1022        u32 txpower_tracking_callback_cnt;
1023        u8 thermal_read_val[40];
1024        u8 thermal_readback_index;
1025        u32 ccktxpower_adjustcnt_not_ch14;
1026        u32 ccktxpower_adjustcnt_ch14;
1027        u8 tx_fwinfo_force_subcarriermode;
1028        u8 tx_fwinfo_force_subcarrierval;
1029        /* For silent reset */
1030        RESET_TYPE      ResetProgress;
1031        bool            bForcedSilentReset;
1032        bool            bDisableNormalResetCheck;
1033        u16             TxCounter;
1034        u16             RxCounter;
1035        int             IrpPendingCount;
1036        bool            bResetInProgress;
1037        bool            force_reset;
1038        u8              InitialGainOperateType;
1039
1040        u16             SifsTime;
1041
1042        /* Define work item */
1043
1044        struct delayed_work update_beacon_wq;
1045        struct delayed_work watch_dog_wq;
1046        struct delayed_work txpower_tracking_wq;
1047        struct delayed_work rfpath_check_wq;
1048        struct delayed_work gpio_change_rf_wq;
1049        struct delayed_work initialgain_operate_wq;
1050        struct workqueue_struct *priv_wq;
1051} r8192_priv;
1052
1053/* For rtl8187B */
1054typedef enum{
1055        BULK_PRIORITY = 0x01,
1056        LOW_PRIORITY,
1057        NORM_PRIORITY,
1058        VO_PRIORITY,
1059        VI_PRIORITY,
1060        BE_PRIORITY,
1061        BK_PRIORITY,
1062        RSVD2,
1063        RSVD3,
1064        BEACON_PRIORITY,
1065        HIGH_PRIORITY,
1066        MANAGE_PRIORITY,
1067        RSVD4,
1068        RSVD5,
1069        UART_PRIORITY
1070} priority_t;
1071
1072typedef enum {
1073        NIC_8192U = 1,
1074        NIC_8190P = 2,
1075        NIC_8192E = 3,
1076} nic_t;
1077
1078bool init_firmware(struct net_device *dev);
1079short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1080short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1081
1082u32 read_cam(struct net_device *dev, u8 addr);
1083void write_cam(struct net_device *dev, u8 addr, u32 data);
1084
1085int read_nic_byte(struct net_device *dev, int x, u8 *data);
1086int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1087int read_nic_dword(struct net_device *dev, int x, u32 *data);
1088int read_nic_word(struct net_device *dev, int x, u16 *data);
1089int write_nic_byte(struct net_device *dev, int x, u8 y);
1090int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1091int write_nic_word(struct net_device *dev, int x, u16 y);
1092int write_nic_dword(struct net_device *dev, int x, u32 y);
1093void force_pci_posting(struct net_device *dev);
1094
1095void rtl8192_rtx_disable(struct net_device *dev);
1096void rtl8192_rx_enable(struct net_device *dev);
1097void rtl8192_tx_enable(struct net_device *dev);
1098
1099void rtl8192_disassociate(struct net_device *dev);
1100void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1101
1102void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1103void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1104void rtl8192_update_msr(struct net_device *dev);
1105int rtl8192_down(struct net_device *dev);
1106int rtl8192_up(struct net_device *dev);
1107void rtl8192_commit(struct net_device *dev);
1108void rtl8192_set_chan(struct net_device *dev, short ch);
1109void write_phy(struct net_device *dev, u8 adr, u8 data);
1110void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1111void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1112void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1113void rtl8192_set_rxconf(struct net_device *dev);
1114void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1115
1116void EnableHWSecurityConfig8192(struct net_device *dev);
1117void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1118
1119#endif
1120