1
2#ifndef __PMAC_ZILOG_H__
3#define __PMAC_ZILOG_H__
4
5
6
7
8#define MAX_ZS_PORTS 4
9
10
11
12
13#define NUM_ZSREGS 17
14
15struct uart_pmac_port {
16 struct uart_port port;
17 struct uart_pmac_port *mate;
18
19#ifdef CONFIG_PPC_PMAC
20
21
22
23 struct macio_dev *dev;
24
25
26
27 struct device_node *node;
28#else
29 struct platform_device *pdev;
30#endif
31
32
33 int port_type;
34 u8 curregs[NUM_ZSREGS];
35
36 unsigned int flags;
37#define PMACZILOG_FLAG_IS_CONS 0x00000001
38#define PMACZILOG_FLAG_IS_KGDB 0x00000002
39#define PMACZILOG_FLAG_MODEM_STATUS 0x00000004
40#define PMACZILOG_FLAG_IS_CHANNEL_A 0x00000008
41#define PMACZILOG_FLAG_REGS_HELD 0x00000010
42#define PMACZILOG_FLAG_TX_STOPPED 0x00000020
43#define PMACZILOG_FLAG_TX_ACTIVE 0x00000040
44#define PMACZILOG_FLAG_IS_IRDA 0x00000100
45#define PMACZILOG_FLAG_IS_INTMODEM 0x00000200
46#define PMACZILOG_FLAG_HAS_DMA 0x00000400
47#define PMACZILOG_FLAG_RSRC_REQUESTED 0x00000800
48#define PMACZILOG_FLAG_IS_OPEN 0x00002000
49#define PMACZILOG_FLAG_IS_EXTCLK 0x00008000
50#define PMACZILOG_FLAG_BREAK 0x00010000
51
52 unsigned char parity_mask;
53 unsigned char prev_status;
54
55 volatile u8 __iomem *control_reg;
56 volatile u8 __iomem *data_reg;
57
58#ifdef CONFIG_PPC_PMAC
59 unsigned int tx_dma_irq;
60 unsigned int rx_dma_irq;
61 volatile struct dbdma_regs __iomem *tx_dma_regs;
62 volatile struct dbdma_regs __iomem *rx_dma_regs;
63#endif
64
65 unsigned char irq_name[8];
66
67 struct ktermios termios_cache;
68};
69
70#define to_pmz(p) ((struct uart_pmac_port *)(p))
71
72static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
73{
74 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
75 return uap;
76 return uap->mate;
77}
78
79
80
81
82
83
84
85static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
86{
87 if (reg != 0)
88 writeb(reg, port->control_reg);
89 return readb(port->control_reg);
90}
91
92static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
93{
94 if (reg != 0)
95 writeb(reg, port->control_reg);
96 writeb(value, port->control_reg);
97}
98
99static inline u8 read_zsdata(struct uart_pmac_port *port)
100{
101 return readb(port->data_reg);
102}
103
104static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
105{
106 writeb(data, port->data_reg);
107}
108
109static inline void zssync(struct uart_pmac_port *port)
110{
111 (void)readb(port->control_reg);
112}
113
114
115
116
117#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
118#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
119
120#define ZS_CLOCK 3686400
121
122
123
124#define FLAG 0x7e
125
126
127#define R0 0
128#define R1 1
129#define R2 2
130#define R3 3
131#define R4 4
132#define R5 5
133#define R6 6
134#define R7 7
135#define R8 8
136#define R9 9
137#define R10 10
138#define R11 11
139#define R12 12
140#define R13 13
141#define R14 14
142#define R15 15
143#define R7P 16
144
145#define NULLCODE 0
146#define POINT_HIGH 0x8
147#define RES_EXT_INT 0x10
148#define SEND_ABORT 0x18
149#define RES_RxINT_FC 0x20
150#define RES_Tx_P 0x28
151#define ERR_RES 0x30
152#define RES_H_IUS 0x38
153
154#define RES_Rx_CRC 0x40
155#define RES_Tx_CRC 0x80
156#define RES_EOM_L 0xC0
157
158
159
160#define EXT_INT_ENAB 0x1
161#define TxINT_ENAB 0x2
162#define PAR_SPEC 0x4
163
164#define RxINT_DISAB 0
165#define RxINT_FCERR 0x8
166#define INT_ALL_Rx 0x10
167#define INT_ERR_Rx 0x18
168#define RxINT_MASK 0x18
169
170#define WT_RDY_RT 0x20
171#define WT_FN_RDYFN 0x40
172#define WT_RDY_ENAB 0x80
173
174
175
176
177
178#define RxENABLE 0x1
179#define SYNC_L_INH 0x2
180#define ADD_SM 0x4
181#define RxCRC_ENAB 0x8
182#define ENT_HM 0x10
183#define AUTO_ENAB 0x20
184#define Rx5 0x0
185#define Rx7 0x40
186#define Rx6 0x80
187#define Rx8 0xc0
188#define RxN_MASK 0xc0
189
190
191
192#define PAR_ENAB 0x1
193#define PAR_EVEN 0x2
194
195#define SYNC_ENAB 0
196#define SB1 0x4
197#define SB15 0x8
198#define SB2 0xc
199#define SB_MASK 0xc
200
201#define MONSYNC 0
202#define BISYNC 0x10
203#define SDLC 0x20
204#define EXTSYNC 0x30
205
206#define X1CLK 0x0
207#define X16CLK 0x40
208#define X32CLK 0x80
209#define X64CLK 0xC0
210#define XCLK_MASK 0xC0
211
212
213
214#define TxCRC_ENAB 0x1
215#define RTS 0x2
216#define SDLC_CRC 0x4
217#define TxENABLE 0x8
218#define SND_BRK 0x10
219#define Tx5 0x0
220#define Tx7 0x20
221#define Tx6 0x40
222#define Tx8 0x60
223#define TxN_MASK 0x60
224#define DTR 0x80
225
226
227
228
229
230
231#define ENEXREAD 0x40
232
233
234
235
236#define VIS 1
237#define NV 2
238#define DLC 4
239#define MIE 8
240#define STATHI 0x10
241#define NORESET 0
242#define CHRB 0x40
243#define CHRA 0x80
244#define FHWRES 0xc0
245
246
247#define BIT6 1
248#define LOOPMODE 2
249#define ABUNDER 4
250#define MARKIDLE 8
251#define GAOP 0x10
252#define NRZ 0
253#define NRZI 0x20
254#define FM1 0x40
255#define FM0 0x60
256#define CRCPS 0x80
257
258
259#define TRxCXT 0
260#define TRxCTC 1
261#define TRxCBR 2
262#define TRxCDP 3
263#define TRxCOI 4
264#define TCRTxCP 0
265#define TCTRxCP 8
266#define TCBR 0x10
267#define TCDPLL 0x18
268#define RCRTxCP 0
269#define RCTRxCP 0x20
270#define RCBR 0x40
271#define RCDPLL 0x60
272#define RTxCX 0x80
273
274
275
276
277
278
279#define BRENAB 1
280#define BRSRC 2
281#define DTRREQ 4
282#define AUTOECHO 8
283#define LOOPBAK 0x10
284#define SEARCH 0x20
285#define RMC 0x40
286#define DISDPLL 0x60
287#define SSBR 0x80
288#define SSRTxC 0xa0
289#define SFMM 0xc0
290#define SNRZI 0xe0
291
292
293#define EN85C30 1
294#define ZCIE 2
295#define ENSTFIFO 4
296#define DCDIE 8
297#define SYNCIE 0x10
298#define CTSIE 0x20
299#define TxUIE 0x40
300#define BRKIE 0x80
301
302
303
304#define Rx_CH_AV 0x1
305#define ZCOUNT 0x2
306#define Tx_BUF_EMP 0x4
307#define DCD 0x8
308#define SYNC_HUNT 0x10
309#define CTS 0x20
310#define TxEOM 0x40
311#define BRK_ABRT 0x80
312
313
314#define ALL_SNT 0x1
315
316#define RES3 0x8
317#define RES4 0x4
318#define RES5 0xc
319#define RES6 0x2
320#define RES7 0xa
321#define RES8 0x6
322#define RES18 0xe
323#define RES28 0x0
324
325#define PAR_ERR 0x10
326#define Rx_OVR 0x20
327#define CRC_ERR 0x40
328#define END_FR 0x80
329
330
331#define CHB_Tx_EMPTY 0x00
332#define CHB_EXT_STAT 0x02
333#define CHB_Rx_AVAIL 0x04
334#define CHB_SPECIAL 0x06
335#define CHA_Tx_EMPTY 0x08
336#define CHA_EXT_STAT 0x0a
337#define CHA_Rx_AVAIL 0x0c
338#define CHA_SPECIAL 0x0e
339#define STATUS_MASK 0x06
340
341
342#define CHBEXT 0x1
343#define CHBTxIP 0x2
344#define CHBRxIP 0x4
345#define CHAEXT 0x8
346#define CHATxIP 0x10
347#define CHARxIP 0x20
348
349
350
351
352#define ONLOOP 2
353#define LOOPSEND 0x10
354#define CLK2MIS 0x40
355#define CLK1MIS 0x80
356
357
358
359
360
361
362
363
364#define ZS_CLEARERR(port) (write_zsreg(port, 0, ERR_RES))
365#define ZS_CLEARFIFO(port) do { volatile unsigned char garbage; \
366 garbage = read_zsdata(port); \
367 garbage = read_zsdata(port); \
368 garbage = read_zsdata(port); \
369 } while(0)
370
371#define ZS_IS_CONS(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
372#define ZS_IS_KGDB(UP) ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
373#define ZS_IS_CHANNEL_A(UP) ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
374#define ZS_REGS_HELD(UP) ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
375#define ZS_TX_STOPPED(UP) ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
376#define ZS_TX_ACTIVE(UP) ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
377#define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
378#define ZS_IS_IRDA(UP) ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
379#define ZS_IS_INTMODEM(UP) ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
380#define ZS_HAS_DMA(UP) ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
381#define ZS_IS_OPEN(UP) ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
382#define ZS_IS_EXTCLK(UP) ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
383
384#endif
385