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11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/list.h>
19#include <linux/dma-mapping.h>
20
21#include <linux/usb/ch9.h>
22#include <linux/usb/gadget.h>
23#include <linux/usb/composite.h>
24
25#include "core.h"
26#include "debug.h"
27#include "gadget.h"
28#include "io.h"
29
30static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
32 struct dwc3_ep *dep, struct dwc3_request *req);
33
34static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
35 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
36{
37 struct dwc3_trb *trb;
38 struct dwc3 *dwc;
39
40 dwc = dep->dwc;
41 trb = &dwc->ep0_trb[dep->trb_enqueue];
42
43 if (chain)
44 dep->trb_enqueue++;
45
46 trb->bpl = lower_32_bits(buf_dma);
47 trb->bph = upper_32_bits(buf_dma);
48 trb->size = len;
49 trb->ctrl = type;
50
51 trb->ctrl |= (DWC3_TRB_CTRL_HWO
52 | DWC3_TRB_CTRL_ISP_IMI);
53
54 if (chain)
55 trb->ctrl |= DWC3_TRB_CTRL_CHN;
56 else
57 trb->ctrl |= (DWC3_TRB_CTRL_IOC
58 | DWC3_TRB_CTRL_LST);
59
60 trace_dwc3_prepare_trb(dep, trb);
61}
62
63static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
64{
65 struct dwc3_gadget_ep_cmd_params params;
66 struct dwc3 *dwc;
67 int ret;
68
69 if (dep->flags & DWC3_EP_TRANSFER_STARTED)
70 return 0;
71
72 dwc = dep->dwc;
73
74 memset(¶ms, 0, sizeof(params));
75 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
76 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
77
78 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, ¶ms);
79 if (ret < 0)
80 return ret;
81
82 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
83
84 return 0;
85}
86
87static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
88 struct dwc3_request *req)
89{
90 struct dwc3 *dwc = dep->dwc;
91
92 req->request.actual = 0;
93 req->request.status = -EINPROGRESS;
94 req->epnum = dep->number;
95
96 list_add_tail(&req->list, &dep->pending_list);
97
98
99
100
101
102
103
104
105
106
107 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
108 unsigned direction;
109
110 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
111
112 if (dwc->ep0state != EP0_DATA_PHASE) {
113 dev_WARN(dwc->dev, "Unexpected pending request\n");
114 return 0;
115 }
116
117 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
118
119 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
120 DWC3_EP0_DIR_IN);
121
122 return 0;
123 }
124
125
126
127
128
129 if (dwc->delayed_status) {
130 unsigned direction;
131
132 direction = !dwc->ep0_expect_in;
133 dwc->delayed_status = false;
134 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
135
136 if (dwc->ep0state == EP0_STATUS_PHASE)
137 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
138
139 return 0;
140 }
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172
173
174 if (dwc->three_stage_setup) {
175 unsigned direction;
176
177 direction = dwc->ep0_expect_in;
178 dwc->ep0state = EP0_DATA_PHASE;
179
180 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
181
182 dep->flags &= ~DWC3_EP0_DIR_IN;
183 }
184
185 return 0;
186}
187
188int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
189 gfp_t gfp_flags)
190{
191 struct dwc3_request *req = to_dwc3_request(request);
192 struct dwc3_ep *dep = to_dwc3_ep(ep);
193 struct dwc3 *dwc = dep->dwc;
194
195 unsigned long flags;
196
197 int ret;
198
199 spin_lock_irqsave(&dwc->lock, flags);
200 if (!dep->endpoint.desc) {
201 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
202 dep->name);
203 ret = -ESHUTDOWN;
204 goto out;
205 }
206
207
208 if (!list_empty(&dep->pending_list)) {
209 ret = -EBUSY;
210 goto out;
211 }
212
213 ret = __dwc3_gadget_ep0_queue(dep, req);
214
215out:
216 spin_unlock_irqrestore(&dwc->lock, flags);
217
218 return ret;
219}
220
221static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
222{
223 struct dwc3_ep *dep;
224
225
226 dep = dwc->eps[1];
227 dep->flags = DWC3_EP_ENABLED;
228
229
230 dep = dwc->eps[0];
231 __dwc3_gadget_ep_set_halt(dep, 1, false);
232 dep->flags = DWC3_EP_ENABLED;
233 dwc->delayed_status = false;
234
235 if (!list_empty(&dep->pending_list)) {
236 struct dwc3_request *req;
237
238 req = next_request(&dep->pending_list);
239 dwc3_gadget_giveback(dep, req, -ECONNRESET);
240 }
241
242 dwc->ep0state = EP0_SETUP_PHASE;
243 dwc3_ep0_out_start(dwc);
244}
245
246int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
247{
248 struct dwc3_ep *dep = to_dwc3_ep(ep);
249 struct dwc3 *dwc = dep->dwc;
250
251 dwc3_ep0_stall_and_restart(dwc);
252
253 return 0;
254}
255
256int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
257{
258 struct dwc3_ep *dep = to_dwc3_ep(ep);
259 struct dwc3 *dwc = dep->dwc;
260 unsigned long flags;
261 int ret;
262
263 spin_lock_irqsave(&dwc->lock, flags);
264 ret = __dwc3_gadget_ep0_set_halt(ep, value);
265 spin_unlock_irqrestore(&dwc->lock, flags);
266
267 return ret;
268}
269
270void dwc3_ep0_out_start(struct dwc3 *dwc)
271{
272 struct dwc3_ep *dep;
273 int ret;
274
275 complete(&dwc->ep0_in_setup);
276
277 dep = dwc->eps[0];
278 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
279 DWC3_TRBCTL_CONTROL_SETUP, false);
280 ret = dwc3_ep0_start_trans(dep);
281 WARN_ON(ret < 0);
282}
283
284static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
285{
286 struct dwc3_ep *dep;
287 u32 windex = le16_to_cpu(wIndex_le);
288 u32 epnum;
289
290 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
291 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
292 epnum |= 1;
293
294 dep = dwc->eps[epnum];
295 if (dep->flags & DWC3_EP_ENABLED)
296 return dep;
297
298 return NULL;
299}
300
301static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
302{
303}
304
305
306
307static int dwc3_ep0_handle_status(struct dwc3 *dwc,
308 struct usb_ctrlrequest *ctrl)
309{
310 struct dwc3_ep *dep;
311 u32 recip;
312 u32 value;
313 u32 reg;
314 u16 usb_status = 0;
315 __le16 *response_pkt;
316
317
318 value = le16_to_cpu(ctrl->wValue);
319 if (value != 0)
320 return -EINVAL;
321
322 recip = ctrl->bRequestType & USB_RECIP_MASK;
323 switch (recip) {
324 case USB_RECIP_DEVICE:
325
326
327
328 usb_status |= dwc->gadget.is_selfpowered;
329
330 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
331 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
332 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
333 if (reg & DWC3_DCTL_INITU1ENA)
334 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
335 if (reg & DWC3_DCTL_INITU2ENA)
336 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
337 }
338
339 break;
340
341 case USB_RECIP_INTERFACE:
342
343
344
345
346 break;
347
348 case USB_RECIP_ENDPOINT:
349 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
350 if (!dep)
351 return -EINVAL;
352
353 if (dep->flags & DWC3_EP_STALL)
354 usb_status = 1 << USB_ENDPOINT_HALT;
355 break;
356 default:
357 return -EINVAL;
358 }
359
360 response_pkt = (__le16 *) dwc->setup_buf;
361 *response_pkt = cpu_to_le16(usb_status);
362
363 dep = dwc->eps[0];
364 dwc->ep0_usb_req.dep = dep;
365 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
366 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
367 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
368
369 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
370}
371
372static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
373 int set)
374{
375 u32 reg;
376
377 if (state != USB_STATE_CONFIGURED)
378 return -EINVAL;
379 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
380 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
381 return -EINVAL;
382
383 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
384 if (set)
385 reg |= DWC3_DCTL_INITU1ENA;
386 else
387 reg &= ~DWC3_DCTL_INITU1ENA;
388 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
389
390 return 0;
391}
392
393static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
394 int set)
395{
396 u32 reg;
397
398
399 if (state != USB_STATE_CONFIGURED)
400 return -EINVAL;
401 if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
402 (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
403 return -EINVAL;
404
405 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
406 if (set)
407 reg |= DWC3_DCTL_INITU2ENA;
408 else
409 reg &= ~DWC3_DCTL_INITU2ENA;
410 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
411
412 return 0;
413}
414
415static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
416 u32 wIndex, int set)
417{
418 if ((wIndex & 0xff) != 0)
419 return -EINVAL;
420 if (!set)
421 return -EINVAL;
422
423 switch (wIndex >> 8) {
424 case TEST_J:
425 case TEST_K:
426 case TEST_SE0_NAK:
427 case TEST_PACKET:
428 case TEST_FORCE_EN:
429 dwc->test_mode_nr = wIndex >> 8;
430 dwc->test_mode = true;
431 break;
432 default:
433 return -EINVAL;
434 }
435
436 return 0;
437}
438
439static int dwc3_ep0_handle_device(struct dwc3 *dwc,
440 struct usb_ctrlrequest *ctrl, int set)
441{
442 enum usb_device_state state;
443 u32 wValue;
444 u32 wIndex;
445 int ret = 0;
446
447 wValue = le16_to_cpu(ctrl->wValue);
448 wIndex = le16_to_cpu(ctrl->wIndex);
449 state = dwc->gadget.state;
450
451 switch (wValue) {
452 case USB_DEVICE_REMOTE_WAKEUP:
453 break;
454
455
456
457
458 case USB_DEVICE_U1_ENABLE:
459 ret = dwc3_ep0_handle_u1(dwc, state, set);
460 break;
461 case USB_DEVICE_U2_ENABLE:
462 ret = dwc3_ep0_handle_u2(dwc, state, set);
463 break;
464 case USB_DEVICE_LTM_ENABLE:
465 ret = -EINVAL;
466 break;
467 case USB_DEVICE_TEST_MODE:
468 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
469 break;
470 default:
471 ret = -EINVAL;
472 }
473
474 return ret;
475}
476
477static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
478 struct usb_ctrlrequest *ctrl, int set)
479{
480 u32 wValue;
481 int ret = 0;
482
483 wValue = le16_to_cpu(ctrl->wValue);
484
485 switch (wValue) {
486 case USB_INTRF_FUNC_SUSPEND:
487
488
489
490
491
492
493
494 break;
495 default:
496 ret = -EINVAL;
497 }
498
499 return ret;
500}
501
502static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
503 struct usb_ctrlrequest *ctrl, int set)
504{
505 struct dwc3_ep *dep;
506 u32 wValue;
507 int ret;
508
509 wValue = le16_to_cpu(ctrl->wValue);
510
511 switch (wValue) {
512 case USB_ENDPOINT_HALT:
513 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
514 if (!dep)
515 return -EINVAL;
516
517 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
518 break;
519
520 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
521 if (ret)
522 return -EINVAL;
523 break;
524 default:
525 return -EINVAL;
526 }
527
528 return 0;
529}
530
531static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
532 struct usb_ctrlrequest *ctrl, int set)
533{
534 u32 recip;
535 int ret;
536
537 recip = ctrl->bRequestType & USB_RECIP_MASK;
538
539 switch (recip) {
540 case USB_RECIP_DEVICE:
541 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
542 break;
543 case USB_RECIP_INTERFACE:
544 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
545 break;
546 case USB_RECIP_ENDPOINT:
547 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
548 break;
549 default:
550 ret = -EINVAL;
551 }
552
553 return ret;
554}
555
556static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
557{
558 enum usb_device_state state = dwc->gadget.state;
559 u32 addr;
560 u32 reg;
561
562 addr = le16_to_cpu(ctrl->wValue);
563 if (addr > 127) {
564 dev_err(dwc->dev, "invalid device address %d\n", addr);
565 return -EINVAL;
566 }
567
568 if (state == USB_STATE_CONFIGURED) {
569 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
570 return -EINVAL;
571 }
572
573 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
574 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
575 reg |= DWC3_DCFG_DEVADDR(addr);
576 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
577
578 if (addr)
579 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
580 else
581 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
582
583 return 0;
584}
585
586static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
587{
588 int ret;
589
590 spin_unlock(&dwc->lock);
591 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
592 spin_lock(&dwc->lock);
593 return ret;
594}
595
596static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
597{
598 enum usb_device_state state = dwc->gadget.state;
599 u32 cfg;
600 int ret;
601 u32 reg;
602
603 cfg = le16_to_cpu(ctrl->wValue);
604
605 switch (state) {
606 case USB_STATE_DEFAULT:
607 return -EINVAL;
608
609 case USB_STATE_ADDRESS:
610 ret = dwc3_ep0_delegate_req(dwc, ctrl);
611
612 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
613
614
615
616
617
618
619
620 if (ret == 0)
621 usb_gadget_set_state(&dwc->gadget,
622 USB_STATE_CONFIGURED);
623
624
625
626
627
628 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
629 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
630 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
631 }
632 break;
633
634 case USB_STATE_CONFIGURED:
635 ret = dwc3_ep0_delegate_req(dwc, ctrl);
636 if (!cfg && !ret)
637 usb_gadget_set_state(&dwc->gadget,
638 USB_STATE_ADDRESS);
639 break;
640 default:
641 ret = -EINVAL;
642 }
643 return ret;
644}
645
646static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
647{
648 struct dwc3_ep *dep = to_dwc3_ep(ep);
649 struct dwc3 *dwc = dep->dwc;
650
651 u32 param = 0;
652 u32 reg;
653
654 struct timing {
655 u8 u1sel;
656 u8 u1pel;
657 __le16 u2sel;
658 __le16 u2pel;
659 } __packed timing;
660
661 int ret;
662
663 memcpy(&timing, req->buf, sizeof(timing));
664
665 dwc->u1sel = timing.u1sel;
666 dwc->u1pel = timing.u1pel;
667 dwc->u2sel = le16_to_cpu(timing.u2sel);
668 dwc->u2pel = le16_to_cpu(timing.u2pel);
669
670 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
671 if (reg & DWC3_DCTL_INITU2ENA)
672 param = dwc->u2pel;
673 if (reg & DWC3_DCTL_INITU1ENA)
674 param = dwc->u1pel;
675
676
677
678
679
680
681 if (param > 125)
682 param = 0;
683
684
685 ret = dwc3_send_gadget_generic_command(dwc,
686 DWC3_DGCMD_SET_PERIODIC_PAR, param);
687 WARN_ON(ret < 0);
688}
689
690static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
691{
692 struct dwc3_ep *dep;
693 enum usb_device_state state = dwc->gadget.state;
694 u16 wLength;
695
696 if (state == USB_STATE_DEFAULT)
697 return -EINVAL;
698
699 wLength = le16_to_cpu(ctrl->wLength);
700
701 if (wLength != 6) {
702 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
703 wLength);
704 return -EINVAL;
705 }
706
707
708
709
710
711
712
713
714
715 dep = dwc->eps[0];
716 dwc->ep0_usb_req.dep = dep;
717 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
718 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
719 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
720
721 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
722}
723
724static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
725{
726 u16 wLength;
727 u16 wValue;
728 u16 wIndex;
729
730 wValue = le16_to_cpu(ctrl->wValue);
731 wLength = le16_to_cpu(ctrl->wLength);
732 wIndex = le16_to_cpu(ctrl->wIndex);
733
734 if (wIndex || wLength)
735 return -EINVAL;
736
737 dwc->gadget.isoch_delay = wValue;
738
739 return 0;
740}
741
742static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
743{
744 int ret;
745
746 switch (ctrl->bRequest) {
747 case USB_REQ_GET_STATUS:
748 ret = dwc3_ep0_handle_status(dwc, ctrl);
749 break;
750 case USB_REQ_CLEAR_FEATURE:
751 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
752 break;
753 case USB_REQ_SET_FEATURE:
754 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
755 break;
756 case USB_REQ_SET_ADDRESS:
757 ret = dwc3_ep0_set_address(dwc, ctrl);
758 break;
759 case USB_REQ_SET_CONFIGURATION:
760 ret = dwc3_ep0_set_config(dwc, ctrl);
761 break;
762 case USB_REQ_SET_SEL:
763 ret = dwc3_ep0_set_sel(dwc, ctrl);
764 break;
765 case USB_REQ_SET_ISOCH_DELAY:
766 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
767 break;
768 default:
769 ret = dwc3_ep0_delegate_req(dwc, ctrl);
770 break;
771 }
772
773 return ret;
774}
775
776static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
777 const struct dwc3_event_depevt *event)
778{
779 struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
780 int ret = -EINVAL;
781 u32 len;
782
783 if (!dwc->gadget_driver)
784 goto out;
785
786 trace_dwc3_ctrl_req(ctrl);
787
788 len = le16_to_cpu(ctrl->wLength);
789 if (!len) {
790 dwc->three_stage_setup = false;
791 dwc->ep0_expect_in = false;
792 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
793 } else {
794 dwc->three_stage_setup = true;
795 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
796 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
797 }
798
799 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
800 ret = dwc3_ep0_std_request(dwc, ctrl);
801 else
802 ret = dwc3_ep0_delegate_req(dwc, ctrl);
803
804 if (ret == USB_GADGET_DELAYED_STATUS)
805 dwc->delayed_status = true;
806
807out:
808 if (ret < 0)
809 dwc3_ep0_stall_and_restart(dwc);
810}
811
812static void dwc3_ep0_complete_data(struct dwc3 *dwc,
813 const struct dwc3_event_depevt *event)
814{
815 struct dwc3_request *r;
816 struct usb_request *ur;
817 struct dwc3_trb *trb;
818 struct dwc3_ep *ep0;
819 u32 transferred = 0;
820 u32 status;
821 u32 length;
822 u8 epnum;
823
824 epnum = event->endpoint_number;
825 ep0 = dwc->eps[0];
826
827 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
828 trb = dwc->ep0_trb;
829 trace_dwc3_complete_trb(ep0, trb);
830
831 r = next_request(&ep0->pending_list);
832 if (!r)
833 return;
834
835 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
836 if (status == DWC3_TRBSTS_SETUP_PENDING) {
837 dwc->setup_packet_pending = true;
838 if (r)
839 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
840
841 return;
842 }
843
844 ur = &r->request;
845
846 length = trb->size & DWC3_TRB_SIZE_MASK;
847 transferred = ur->length - length;
848 ur->actual += transferred;
849
850 if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
851 ur->length && ur->zero) || dwc->ep0_bounced) {
852 trb++;
853 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
854 trace_dwc3_complete_trb(ep0, trb);
855
856 if (r->direction)
857 dwc->eps[1]->trb_enqueue = 0;
858 else
859 dwc->eps[0]->trb_enqueue = 0;
860
861 dwc->ep0_bounced = false;
862 }
863
864 if ((epnum & 1) && ur->actual < ur->length)
865 dwc3_ep0_stall_and_restart(dwc);
866 else
867 dwc3_gadget_giveback(ep0, r, 0);
868}
869
870static void dwc3_ep0_complete_status(struct dwc3 *dwc,
871 const struct dwc3_event_depevt *event)
872{
873 struct dwc3_request *r;
874 struct dwc3_ep *dep;
875 struct dwc3_trb *trb;
876 u32 status;
877
878 dep = dwc->eps[0];
879 trb = dwc->ep0_trb;
880
881 trace_dwc3_complete_trb(dep, trb);
882
883 if (!list_empty(&dep->pending_list)) {
884 r = next_request(&dep->pending_list);
885
886 dwc3_gadget_giveback(dep, r, 0);
887 }
888
889 if (dwc->test_mode) {
890 int ret;
891
892 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
893 if (ret < 0) {
894 dev_err(dwc->dev, "invalid test #%d\n",
895 dwc->test_mode_nr);
896 dwc3_ep0_stall_and_restart(dwc);
897 return;
898 }
899 }
900
901 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
902 if (status == DWC3_TRBSTS_SETUP_PENDING)
903 dwc->setup_packet_pending = true;
904
905 dwc->ep0state = EP0_SETUP_PHASE;
906 dwc3_ep0_out_start(dwc);
907}
908
909static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
910 const struct dwc3_event_depevt *event)
911{
912 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
913
914 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
915 dep->resource_index = 0;
916 dwc->setup_packet_pending = false;
917
918 switch (dwc->ep0state) {
919 case EP0_SETUP_PHASE:
920 dwc3_ep0_inspect_setup(dwc, event);
921 break;
922
923 case EP0_DATA_PHASE:
924 dwc3_ep0_complete_data(dwc, event);
925 break;
926
927 case EP0_STATUS_PHASE:
928 dwc3_ep0_complete_status(dwc, event);
929 break;
930 default:
931 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
932 }
933}
934
935static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
936 struct dwc3_ep *dep, struct dwc3_request *req)
937{
938 int ret;
939
940 req->direction = !!dep->number;
941
942 if (req->request.length == 0) {
943 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0,
944 DWC3_TRBCTL_CONTROL_DATA, false);
945 ret = dwc3_ep0_start_trans(dep);
946 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
947 && (dep->number == 0)) {
948 u32 maxpacket;
949 u32 rem;
950
951 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
952 &req->request, dep->number);
953 if (ret)
954 return;
955
956 maxpacket = dep->endpoint.maxpacket;
957 rem = req->request.length % maxpacket;
958 dwc->ep0_bounced = true;
959
960
961 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
962 req->request.length,
963 DWC3_TRBCTL_CONTROL_DATA,
964 true);
965
966 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
967
968
969 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
970 maxpacket - rem,
971 DWC3_TRBCTL_CONTROL_DATA,
972 false);
973 ret = dwc3_ep0_start_trans(dep);
974 } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
975 req->request.length && req->request.zero) {
976
977 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
978 &req->request, dep->number);
979 if (ret)
980 return;
981
982
983 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
984 req->request.length,
985 DWC3_TRBCTL_CONTROL_DATA,
986 true);
987
988 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
989
990
991 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
992 0, DWC3_TRBCTL_CONTROL_DATA,
993 false);
994 ret = dwc3_ep0_start_trans(dep);
995 } else {
996 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
997 &req->request, dep->number);
998 if (ret)
999 return;
1000
1001 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1002 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1003 false);
1004
1005 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1006
1007 ret = dwc3_ep0_start_trans(dep);
1008 }
1009
1010 WARN_ON(ret < 0);
1011}
1012
1013static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1014{
1015 struct dwc3 *dwc = dep->dwc;
1016 u32 type;
1017
1018 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1019 : DWC3_TRBCTL_CONTROL_STATUS2;
1020
1021 dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1022 return dwc3_ep0_start_trans(dep);
1023}
1024
1025static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1026{
1027 WARN_ON(dwc3_ep0_start_control_status(dep));
1028}
1029
1030static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1031 const struct dwc3_event_depevt *event)
1032{
1033 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
1034
1035 __dwc3_ep0_do_control_status(dwc, dep);
1036}
1037
1038static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1039{
1040 struct dwc3_gadget_ep_cmd_params params;
1041 u32 cmd;
1042 int ret;
1043
1044 if (!dep->resource_index)
1045 return;
1046
1047 cmd = DWC3_DEPCMD_ENDTRANSFER;
1048 cmd |= DWC3_DEPCMD_CMDIOC;
1049 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1050 memset(¶ms, 0, sizeof(params));
1051 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1052 WARN_ON_ONCE(ret);
1053 dep->resource_index = 0;
1054}
1055
1056static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1057 const struct dwc3_event_depevt *event)
1058{
1059 switch (event->status) {
1060 case DEPEVT_STATUS_CONTROL_DATA:
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070 if (dwc->ep0_expect_in != event->endpoint_number) {
1071 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1072
1073 dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1074 dwc3_ep0_end_control_data(dwc, dep);
1075 dwc3_ep0_stall_and_restart(dwc);
1076 return;
1077 }
1078
1079 break;
1080
1081 case DEPEVT_STATUS_CONTROL_STATUS:
1082 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1083 return;
1084
1085 dwc->ep0state = EP0_STATUS_PHASE;
1086
1087 if (dwc->delayed_status) {
1088 struct dwc3_ep *dep = dwc->eps[0];
1089
1090 WARN_ON_ONCE(event->endpoint_number != 1);
1091
1092
1093
1094
1095
1096 if (!list_empty(&dep->pending_list)) {
1097 dwc->delayed_status = false;
1098 usb_gadget_set_state(&dwc->gadget,
1099 USB_STATE_CONFIGURED);
1100 dwc3_ep0_do_control_status(dwc, event);
1101 }
1102
1103 return;
1104 }
1105
1106 dwc3_ep0_do_control_status(dwc, event);
1107 }
1108}
1109
1110void dwc3_ep0_interrupt(struct dwc3 *dwc,
1111 const struct dwc3_event_depevt *event)
1112{
1113 switch (event->endpoint_event) {
1114 case DWC3_DEPEVT_XFERCOMPLETE:
1115 dwc3_ep0_xfer_complete(dwc, event);
1116 break;
1117
1118 case DWC3_DEPEVT_XFERNOTREADY:
1119 dwc3_ep0_xfernotready(dwc, event);
1120 break;
1121
1122 case DWC3_DEPEVT_XFERINPROGRESS:
1123 case DWC3_DEPEVT_RXTXFIFOEVT:
1124 case DWC3_DEPEVT_STREAMEVT:
1125 case DWC3_DEPEVT_EPCMDCMPLT:
1126 break;
1127 }
1128}
1129