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14#ifndef _LINUX_MFD_SYSCON_ATMEL_SMC_H_
15#define _LINUX_MFD_SYSCON_ATMEL_SMC_H_
16
17#include <linux/kernel.h>
18#include <linux/of.h>
19#include <linux/regmap.h>
20
21#define ATMEL_SMC_SETUP(cs) (((cs) * 0x10))
22#define ATMEL_HSMC_SETUP(layout, cs) \
23 ((layout)->timing_regs_offset + ((cs) * 0x14))
24#define ATMEL_SMC_PULSE(cs) (((cs) * 0x10) + 0x4)
25#define ATMEL_HSMC_PULSE(layout, cs) \
26 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x4)
27#define ATMEL_SMC_CYCLE(cs) (((cs) * 0x10) + 0x8)
28#define ATMEL_HSMC_CYCLE(layout, cs) \
29 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x8)
30#define ATMEL_SMC_NWE_SHIFT 0
31#define ATMEL_SMC_NCS_WR_SHIFT 8
32#define ATMEL_SMC_NRD_SHIFT 16
33#define ATMEL_SMC_NCS_RD_SHIFT 24
34
35#define ATMEL_SMC_MODE(cs) (((cs) * 0x10) + 0xc)
36#define ATMEL_HSMC_MODE(layout, cs) \
37 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0x10)
38#define ATMEL_SMC_MODE_READMODE_MASK BIT(0)
39#define ATMEL_SMC_MODE_READMODE_NCS (0 << 0)
40#define ATMEL_SMC_MODE_READMODE_NRD (1 << 0)
41#define ATMEL_SMC_MODE_WRITEMODE_MASK BIT(1)
42#define ATMEL_SMC_MODE_WRITEMODE_NCS (0 << 1)
43#define ATMEL_SMC_MODE_WRITEMODE_NWE (1 << 1)
44#define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)
45#define ATMEL_SMC_MODE_EXNWMODE_DISABLE (0 << 4)
46#define ATMEL_SMC_MODE_EXNWMODE_FROZEN (2 << 4)
47#define ATMEL_SMC_MODE_EXNWMODE_READY (3 << 4)
48#define ATMEL_SMC_MODE_BAT_MASK BIT(8)
49#define ATMEL_SMC_MODE_BAT_SELECT (0 << 8)
50#define ATMEL_SMC_MODE_BAT_WRITE (1 << 8)
51#define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)
52#define ATMEL_SMC_MODE_DBW_8 (0 << 12)
53#define ATMEL_SMC_MODE_DBW_16 (1 << 12)
54#define ATMEL_SMC_MODE_DBW_32 (2 << 12)
55#define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)
56#define ATMEL_SMC_MODE_TDF(x) (((x) - 1) << 16)
57#define ATMEL_SMC_MODE_TDF_MAX 16
58#define ATMEL_SMC_MODE_TDF_MIN 1
59#define ATMEL_SMC_MODE_TDFMODE_OPTIMIZED BIT(20)
60#define ATMEL_SMC_MODE_PMEN BIT(24)
61#define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
62#define ATMEL_SMC_MODE_PS_4 (0 << 28)
63#define ATMEL_SMC_MODE_PS_8 (1 << 28)
64#define ATMEL_SMC_MODE_PS_16 (2 << 28)
65#define ATMEL_SMC_MODE_PS_32 (3 << 28)
66
67#define ATMEL_HSMC_TIMINGS(layout, cs) \
68 ((layout)->timing_regs_offset + ((cs) * 0x14) + 0xc)
69#define ATMEL_HSMC_TIMINGS_OCMS BIT(12)
70#define ATMEL_HSMC_TIMINGS_RBNSEL(x) ((x) << 28)
71#define ATMEL_HSMC_TIMINGS_NFSEL BIT(31)
72#define ATMEL_HSMC_TIMINGS_TCLR_SHIFT 0
73#define ATMEL_HSMC_TIMINGS_TADL_SHIFT 4
74#define ATMEL_HSMC_TIMINGS_TAR_SHIFT 8
75#define ATMEL_HSMC_TIMINGS_TRR_SHIFT 16
76#define ATMEL_HSMC_TIMINGS_TWB_SHIFT 24
77
78struct atmel_hsmc_reg_layout {
79 unsigned int timing_regs_offset;
80};
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91struct atmel_smc_cs_conf {
92 u32 setup;
93 u32 pulse;
94 u32 cycle;
95 u32 timings;
96 u32 mode;
97};
98
99void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf);
100int atmel_smc_cs_conf_set_timing(struct atmel_smc_cs_conf *conf,
101 unsigned int shift,
102 unsigned int ncycles);
103int atmel_smc_cs_conf_set_setup(struct atmel_smc_cs_conf *conf,
104 unsigned int shift, unsigned int ncycles);
105int atmel_smc_cs_conf_set_pulse(struct atmel_smc_cs_conf *conf,
106 unsigned int shift, unsigned int ncycles);
107int atmel_smc_cs_conf_set_cycle(struct atmel_smc_cs_conf *conf,
108 unsigned int shift, unsigned int ncycles);
109void atmel_smc_cs_conf_apply(struct regmap *regmap, int cs,
110 const struct atmel_smc_cs_conf *conf);
111void atmel_hsmc_cs_conf_apply(struct regmap *regmap,
112 const struct atmel_hsmc_reg_layout *reglayout,
113 int cs, const struct atmel_smc_cs_conf *conf);
114void atmel_smc_cs_conf_get(struct regmap *regmap, int cs,
115 struct atmel_smc_cs_conf *conf);
116void atmel_hsmc_cs_conf_get(struct regmap *regmap,
117 const struct atmel_hsmc_reg_layout *reglayout,
118 int cs, struct atmel_smc_cs_conf *conf);
119const struct atmel_hsmc_reg_layout *
120atmel_hsmc_get_reg_layout(struct device_node *np);
121
122#endif
123
