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33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
48
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
52#define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55#define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59#define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60#define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
62
63#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
71
72
73#define MLX5_SET(typ, p, fld, v) do { \
74 u32 _v = v; \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((_v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
82#define MLX5_ARRAY_SET(typ, p, fld, idx, v) do { \
83 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 32); \
84 MLX5_SET(typ, p, fld[idx], v); \
85} while (0)
86
87#define MLX5_SET_TO_ONES(typ, p, fld) do { \
88 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
89 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
90 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
91 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
92 << __mlx5_dw_bit_off(typ, fld))); \
93} while (0)
94
95#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
96__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
97__mlx5_mask(typ, fld))
98
99#define MLX5_GET_PR(typ, p, fld) ({ \
100 u32 ___t = MLX5_GET(typ, p, fld); \
101 pr_debug(#fld " = 0x%x\n", ___t); \
102 ___t; \
103})
104
105#define __MLX5_SET64(typ, p, fld, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
107 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
108} while (0)
109
110#define MLX5_SET64(typ, p, fld, v) do { \
111 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
112 __MLX5_SET64(typ, p, fld, v); \
113} while (0)
114
115#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
116 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
117 __MLX5_SET64(typ, p, fld[idx], v); \
118} while (0)
119
120#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET64_PR(typ, p, fld) ({ \
123 u64 ___t = MLX5_GET64(typ, p, fld); \
124 pr_debug(#fld " = 0x%llx\n", ___t); \
125 ___t; \
126})
127
128#define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
129__mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
130__mlx5_mask16(typ, fld))
131
132#define MLX5_SET16(typ, p, fld, v) do { \
133 u16 _v = v; \
134 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
135 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
136 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
137 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
138 << __mlx5_16_bit_off(typ, fld))); \
139} while (0)
140
141
142#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
143 __mlx5_64_off(typ, fld)))
144
145#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
146 type_t tmp; \
147 switch (sizeof(tmp)) { \
148 case sizeof(u8): \
149 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
150 break; \
151 case sizeof(u16): \
152 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
153 break; \
154 case sizeof(u32): \
155 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
156 break; \
157 case sizeof(u64): \
158 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
159 break; \
160 } \
161 tmp; \
162 })
163
164enum mlx5_inline_modes {
165 MLX5_INLINE_MODE_NONE,
166 MLX5_INLINE_MODE_L2,
167 MLX5_INLINE_MODE_IP,
168 MLX5_INLINE_MODE_TCP_UDP,
169};
170
171enum {
172 MLX5_MAX_COMMANDS = 32,
173 MLX5_CMD_DATA_BLOCK_SIZE = 512,
174 MLX5_PCI_CMD_XPORT = 7,
175 MLX5_MKEY_BSF_OCTO_SIZE = 4,
176 MLX5_MAX_PSVS = 4,
177};
178
179enum {
180 MLX5_EXTENDED_UD_AV = 0x80000000,
181};
182
183enum {
184 MLX5_CQ_STATE_ARMED = 9,
185 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
186 MLX5_CQ_STATE_FIRED = 0xa,
187};
188
189enum {
190 MLX5_STAT_RATE_OFFSET = 5,
191};
192
193enum {
194 MLX5_INLINE_SEG = 0x80000000,
195};
196
197enum {
198 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
199};
200
201enum {
202 MLX5_MIN_PKEY_TABLE_SIZE = 128,
203 MLX5_MAX_LOG_PKEY_TABLE = 5,
204};
205
206enum {
207 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
208};
209
210enum {
211 MLX5_PFAULT_SUBTYPE_WQE = 0,
212 MLX5_PFAULT_SUBTYPE_RDMA = 1,
213};
214
215enum {
216 MLX5_PERM_LOCAL_READ = 1 << 2,
217 MLX5_PERM_LOCAL_WRITE = 1 << 3,
218 MLX5_PERM_REMOTE_READ = 1 << 4,
219 MLX5_PERM_REMOTE_WRITE = 1 << 5,
220 MLX5_PERM_ATOMIC = 1 << 6,
221 MLX5_PERM_UMR_EN = 1 << 7,
222};
223
224enum {
225 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
226 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
227 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
228 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
229 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
230};
231
232enum {
233 MLX5_EN_RD = (u64)1,
234 MLX5_EN_WR = (u64)2
235};
236
237enum {
238 MLX5_ADAPTER_PAGE_SHIFT = 12,
239 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
240};
241
242enum {
243 MLX5_BFREGS_PER_UAR = 4,
244 MLX5_MAX_UARS = 1 << 8,
245 MLX5_NON_FP_BFREGS_PER_UAR = 2,
246 MLX5_FP_BFREGS_PER_UAR = MLX5_BFREGS_PER_UAR -
247 MLX5_NON_FP_BFREGS_PER_UAR,
248 MLX5_MAX_BFREGS = MLX5_MAX_UARS *
249 MLX5_NON_FP_BFREGS_PER_UAR,
250 MLX5_UARS_IN_PAGE = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
251 MLX5_NON_FP_BFREGS_IN_PAGE = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
252 MLX5_MIN_DYN_BFREGS = 512,
253 MLX5_MAX_DYN_BFREGS = 1024,
254};
255
256enum {
257 MLX5_MKEY_MASK_LEN = 1ull << 0,
258 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
259 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
260 MLX5_MKEY_MASK_PD = 1ull << 7,
261 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
262 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
263 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
264 MLX5_MKEY_MASK_KEY = 1ull << 13,
265 MLX5_MKEY_MASK_QPN = 1ull << 14,
266 MLX5_MKEY_MASK_LR = 1ull << 17,
267 MLX5_MKEY_MASK_LW = 1ull << 18,
268 MLX5_MKEY_MASK_RR = 1ull << 19,
269 MLX5_MKEY_MASK_RW = 1ull << 20,
270 MLX5_MKEY_MASK_A = 1ull << 21,
271 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
272 MLX5_MKEY_MASK_FREE = 1ull << 29,
273};
274
275enum {
276 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
277
278 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
279 MLX5_UMR_CHECK_FREE = (2 << 5),
280
281 MLX5_UMR_INLINE = (1 << 7),
282};
283
284#define MLX5_UMR_MTT_ALIGNMENT 0x40
285#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
286#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
287
288#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
289
290enum {
291 MLX5_EVENT_QUEUE_TYPE_QP = 0,
292 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
293 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
294 MLX5_EVENT_QUEUE_TYPE_DCT = 6,
295};
296
297enum mlx5_event {
298 MLX5_EVENT_TYPE_COMP = 0x0,
299
300 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
301 MLX5_EVENT_TYPE_COMM_EST = 0x02,
302 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
303 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
304 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
305
306 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
307 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
308 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
309 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
310 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
311 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
312
313 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
314 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
315 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
316 MLX5_EVENT_TYPE_PORT_MODULE_EVENT = 0x16,
317 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
318 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
319 MLX5_EVENT_TYPE_GENERAL_EVENT = 0x22,
320 MLX5_EVENT_TYPE_PPS_EVENT = 0x25,
321
322 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
323 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
324
325 MLX5_EVENT_TYPE_CMD = 0x0a,
326 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
327
328 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
329 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
330
331 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
332
333 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
334 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
335
336 MLX5_EVENT_TYPE_DEVICE_TRACER = 0x26,
337};
338
339enum {
340 MLX5_TRACER_SUBTYPE_OWNERSHIP_CHANGE = 0x0,
341 MLX5_TRACER_SUBTYPE_TRACES_AVAILABLE = 0x1,
342};
343
344enum {
345 MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
346};
347
348enum {
349 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
350 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
351 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
352 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
353 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
354 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
355 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
356};
357
358enum {
359 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
360 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
361 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
362 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
363 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
364 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
365 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
366 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
367 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
368 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
369 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
370 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
371};
372
373enum {
374 MLX5_ROCE_VERSION_1 = 0,
375 MLX5_ROCE_VERSION_2 = 2,
376};
377
378enum {
379 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
380 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
381};
382
383enum {
384 MLX5_ROCE_L3_TYPE_IPV4 = 0,
385 MLX5_ROCE_L3_TYPE_IPV6 = 1,
386};
387
388enum {
389 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
390 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
391};
392
393enum {
394 MLX5_OPCODE_NOP = 0x00,
395 MLX5_OPCODE_SEND_INVAL = 0x01,
396 MLX5_OPCODE_RDMA_WRITE = 0x08,
397 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
398 MLX5_OPCODE_SEND = 0x0a,
399 MLX5_OPCODE_SEND_IMM = 0x0b,
400 MLX5_OPCODE_LSO = 0x0e,
401 MLX5_OPCODE_RDMA_READ = 0x10,
402 MLX5_OPCODE_ATOMIC_CS = 0x11,
403 MLX5_OPCODE_ATOMIC_FA = 0x12,
404 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
405 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
406 MLX5_OPCODE_BIND_MW = 0x18,
407 MLX5_OPCODE_CONFIG_CMD = 0x1f,
408
409 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
410 MLX5_RECV_OPCODE_SEND = 0x01,
411 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
412 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
413
414 MLX5_CQE_OPCODE_ERROR = 0x1e,
415 MLX5_CQE_OPCODE_RESIZE = 0x16,
416
417 MLX5_OPCODE_SET_PSV = 0x20,
418 MLX5_OPCODE_GET_PSV = 0x21,
419 MLX5_OPCODE_CHECK_PSV = 0x22,
420 MLX5_OPCODE_RGET_PSV = 0x26,
421 MLX5_OPCODE_RCHECK_PSV = 0x27,
422
423 MLX5_OPCODE_UMR = 0x25,
424
425};
426
427enum {
428 MLX5_SET_PORT_RESET_QKEY = 0,
429 MLX5_SET_PORT_GUID0 = 16,
430 MLX5_SET_PORT_NODE_GUID = 17,
431 MLX5_SET_PORT_SYS_GUID = 18,
432 MLX5_SET_PORT_GID_TABLE = 19,
433 MLX5_SET_PORT_PKEY_TABLE = 20,
434};
435
436enum {
437 MLX5_BW_NO_LIMIT = 0,
438 MLX5_100_MBPS_UNIT = 3,
439 MLX5_GBPS_UNIT = 4,
440};
441
442enum {
443 MLX5_MAX_PAGE_SHIFT = 31
444};
445
446enum {
447 MLX5_CAP_OFF_CMDIF_CSUM = 46,
448};
449
450enum {
451
452
453
454
455
456
457
458 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
459};
460
461enum mlx5_odp_transport_cap_bits {
462 MLX5_ODP_SUPPORT_SEND = 1 << 31,
463 MLX5_ODP_SUPPORT_RECV = 1 << 30,
464 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
465 MLX5_ODP_SUPPORT_READ = 1 << 28,
466};
467
468struct mlx5_odp_caps {
469 char reserved[0x10];
470 struct {
471 __be32 rc_odp_caps;
472 __be32 uc_odp_caps;
473 __be32 ud_odp_caps;
474 } per_transport_caps;
475 char reserved2[0xe4];
476};
477
478struct mlx5_cmd_layout {
479 u8 type;
480 u8 rsvd0[3];
481 __be32 inlen;
482 __be64 in_ptr;
483 __be32 in[4];
484 __be32 out[4];
485 __be64 out_ptr;
486 __be32 outlen;
487 u8 token;
488 u8 sig;
489 u8 rsvd1;
490 u8 status_own;
491};
492
493struct health_buffer {
494 __be32 assert_var[5];
495 __be32 rsvd0[3];
496 __be32 assert_exit_ptr;
497 __be32 assert_callra;
498 __be32 rsvd1[2];
499 __be32 fw_ver;
500 __be32 hw_id;
501 __be32 rsvd2;
502 u8 irisc_index;
503 u8 synd;
504 __be16 ext_synd;
505};
506
507struct mlx5_init_seg {
508 __be32 fw_rev;
509 __be32 cmdif_rev_fw_sub;
510 __be32 rsvd0[2];
511 __be32 cmdq_addr_h;
512 __be32 cmdq_addr_l_sz;
513 __be32 cmd_dbell;
514 __be32 rsvd1[120];
515 __be32 initializing;
516 struct health_buffer health;
517 __be32 rsvd2[880];
518 __be32 internal_timer_h;
519 __be32 internal_timer_l;
520 __be32 rsvd3[2];
521 __be32 health_counter;
522 __be32 rsvd4[1019];
523 __be64 ieee1588_clk;
524 __be32 ieee1588_clk_type;
525 __be32 clr_intx;
526};
527
528struct mlx5_eqe_comp {
529 __be32 reserved[6];
530 __be32 cqn;
531};
532
533struct mlx5_eqe_qp_srq {
534 __be32 reserved1[5];
535 u8 type;
536 u8 reserved2[3];
537 __be32 qp_srq_n;
538};
539
540struct mlx5_eqe_cq_err {
541 __be32 cqn;
542 u8 reserved1[7];
543 u8 syndrome;
544};
545
546struct mlx5_eqe_port_state {
547 u8 reserved0[8];
548 u8 port;
549};
550
551struct mlx5_eqe_gpio {
552 __be32 reserved0[2];
553 __be64 gpio_event;
554};
555
556struct mlx5_eqe_congestion {
557 u8 type;
558 u8 rsvd0;
559 u8 congestion_level;
560};
561
562struct mlx5_eqe_stall_vl {
563 u8 rsvd0[3];
564 u8 port_vl;
565};
566
567struct mlx5_eqe_cmd {
568 __be32 vector;
569 __be32 rsvd[6];
570};
571
572struct mlx5_eqe_page_req {
573 u8 rsvd0[2];
574 __be16 func_id;
575 __be32 num_pages;
576 __be32 rsvd1[5];
577};
578
579struct mlx5_eqe_page_fault {
580 __be32 bytes_committed;
581 union {
582 struct {
583 u16 reserved1;
584 __be16 wqe_index;
585 u16 reserved2;
586 __be16 packet_length;
587 __be32 token;
588 u8 reserved4[8];
589 __be32 pftype_wq;
590 } __packed wqe;
591 struct {
592 __be32 r_key;
593 u16 reserved1;
594 __be16 packet_length;
595 __be32 rdma_op_len;
596 __be64 rdma_va;
597 __be32 pftype_token;
598 } __packed rdma;
599 } __packed;
600} __packed;
601
602struct mlx5_eqe_vport_change {
603 u8 rsvd0[2];
604 __be16 vport_num;
605 __be32 rsvd1[6];
606} __packed;
607
608struct mlx5_eqe_port_module {
609 u8 reserved_at_0[1];
610 u8 module;
611 u8 reserved_at_2[1];
612 u8 module_status;
613 u8 reserved_at_4[2];
614 u8 error_type;
615} __packed;
616
617struct mlx5_eqe_pps {
618 u8 rsvd0[3];
619 u8 pin;
620 u8 rsvd1[4];
621 union {
622 struct {
623 __be32 time_sec;
624 __be32 time_nsec;
625 };
626 struct {
627 __be64 time_stamp;
628 };
629 };
630 u8 rsvd2[12];
631} __packed;
632
633struct mlx5_eqe_dct {
634 __be32 reserved[6];
635 __be32 dctn;
636};
637
638struct mlx5_eqe_temp_warning {
639 __be64 sensor_warning_msb;
640 __be64 sensor_warning_lsb;
641} __packed;
642
643union ev_data {
644 __be32 raw[7];
645 struct mlx5_eqe_cmd cmd;
646 struct mlx5_eqe_comp comp;
647 struct mlx5_eqe_qp_srq qp_srq;
648 struct mlx5_eqe_cq_err cq_err;
649 struct mlx5_eqe_port_state port;
650 struct mlx5_eqe_gpio gpio;
651 struct mlx5_eqe_congestion cong;
652 struct mlx5_eqe_stall_vl stall_vl;
653 struct mlx5_eqe_page_req req_pages;
654 struct mlx5_eqe_page_fault page_fault;
655 struct mlx5_eqe_vport_change vport_change;
656 struct mlx5_eqe_port_module port_module;
657 struct mlx5_eqe_pps pps;
658 struct mlx5_eqe_dct dct;
659 struct mlx5_eqe_temp_warning temp_warning;
660} __packed;
661
662struct mlx5_eqe {
663 u8 rsvd0;
664 u8 type;
665 u8 rsvd1;
666 u8 sub_type;
667 __be32 rsvd2[7];
668 union ev_data data;
669 __be16 rsvd3;
670 u8 signature;
671 u8 owner;
672} __packed;
673
674struct mlx5_cmd_prot_block {
675 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
676 u8 rsvd0[48];
677 __be64 next;
678 __be32 block_num;
679 u8 rsvd1;
680 u8 token;
681 u8 ctrl_sig;
682 u8 sig;
683};
684
685enum {
686 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
687};
688
689struct mlx5_err_cqe {
690 u8 rsvd0[32];
691 __be32 srqn;
692 u8 rsvd1[18];
693 u8 vendor_err_synd;
694 u8 syndrome;
695 __be32 s_wqe_opcode_qpn;
696 __be16 wqe_counter;
697 u8 signature;
698 u8 op_own;
699};
700
701struct mlx5_cqe64 {
702 u8 outer_l3_tunneled;
703 u8 rsvd0;
704 __be16 wqe_id;
705 u8 lro_tcppsh_abort_dupack;
706 u8 lro_min_ttl;
707 __be16 lro_tcp_win;
708 __be32 lro_ack_seq_num;
709 __be32 rss_hash_result;
710 u8 rss_hash_type;
711 u8 ml_path;
712 u8 rsvd20[2];
713 __be16 check_sum;
714 __be16 slid;
715 __be32 flags_rqpn;
716 u8 hds_ip_ext;
717 u8 l4_l3_hdr_type;
718 __be16 vlan_info;
719 __be32 srqn;
720 __be32 imm_inval_pkey;
721 u8 rsvd40[4];
722 __be32 byte_cnt;
723 __be32 timestamp_h;
724 __be32 timestamp_l;
725 __be32 sop_drop_qpn;
726 __be16 wqe_counter;
727 u8 signature;
728 u8 op_own;
729};
730
731struct mlx5_mini_cqe8 {
732 union {
733 __be32 rx_hash_result;
734 struct {
735 __be16 checksum;
736 __be16 rsvd;
737 };
738 struct {
739 __be16 wqe_counter;
740 u8 s_wqe_opcode;
741 u8 reserved;
742 } s_wqe_info;
743 };
744 __be32 byte_cnt;
745};
746
747enum {
748 MLX5_NO_INLINE_DATA,
749 MLX5_INLINE_DATA32_SEG,
750 MLX5_INLINE_DATA64_SEG,
751 MLX5_COMPRESSED,
752};
753
754enum {
755 MLX5_CQE_FORMAT_CSUM = 0x1,
756};
757
758#define MLX5_MINI_CQE_ARRAY_SIZE 8
759
760static inline u8 mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
761{
762 return (cqe->op_own >> 2) & 0x3;
763}
764
765static inline u8 get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
766{
767 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
768}
769
770static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
771{
772 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
773}
774
775static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
776{
777 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
778}
779
780static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
781{
782 return cqe->outer_l3_tunneled & 0x1;
783}
784
785static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
786{
787 return cqe->l4_l3_hdr_type & 0x1;
788}
789
790static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
791{
792 u32 hi, lo;
793
794 hi = be32_to_cpu(cqe->timestamp_h);
795 lo = be32_to_cpu(cqe->timestamp_l);
796
797 return (u64)lo | ((u64)hi << 32);
798}
799
800#define MLX5_MPWQE_LOG_NUM_STRIDES_BASE (9)
801#define MLX5_MPWQE_LOG_STRIDE_SZ_BASE (6)
802
803struct mpwrq_cqe_bc {
804 __be16 filler_consumed_strides;
805 __be16 byte_cnt;
806};
807
808static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
809{
810 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
811
812 return be16_to_cpu(bc->byte_cnt);
813}
814
815static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
816{
817 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
818}
819
820static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
821{
822 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
823
824 return mpwrq_get_cqe_bc_consumed_strides(bc);
825}
826
827static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
828{
829 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
830
831 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
832}
833
834static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
835{
836 return be16_to_cpu(cqe->wqe_counter);
837}
838
839enum {
840 CQE_L4_HDR_TYPE_NONE = 0x0,
841 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
842 CQE_L4_HDR_TYPE_UDP = 0x2,
843 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
844 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
845};
846
847enum {
848 CQE_RSS_HTYPE_IP = 0x3 << 2,
849
850
851
852 CQE_RSS_HTYPE_L4 = 0x3 << 6,
853
854
855
856};
857
858enum {
859 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
860 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
861 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
862};
863
864enum {
865 CQE_L2_OK = 1 << 0,
866 CQE_L3_OK = 1 << 1,
867 CQE_L4_OK = 1 << 2,
868};
869
870struct mlx5_sig_err_cqe {
871 u8 rsvd0[16];
872 __be32 expected_trans_sig;
873 __be32 actual_trans_sig;
874 __be32 expected_reftag;
875 __be32 actual_reftag;
876 __be16 syndrome;
877 u8 rsvd22[2];
878 __be32 mkey;
879 __be64 err_offset;
880 u8 rsvd30[8];
881 __be32 qpn;
882 u8 rsvd38[2];
883 u8 signature;
884 u8 op_own;
885};
886
887struct mlx5_wqe_srq_next_seg {
888 u8 rsvd0[2];
889 __be16 next_wqe_index;
890 u8 signature;
891 u8 rsvd1[11];
892};
893
894union mlx5_ext_cqe {
895 struct ib_grh grh;
896 u8 inl[64];
897};
898
899struct mlx5_cqe128 {
900 union mlx5_ext_cqe inl_grh;
901 struct mlx5_cqe64 cqe64;
902};
903
904enum {
905 MLX5_MKEY_STATUS_FREE = 1 << 6,
906};
907
908enum {
909 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
910 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
911 MLX5_MKEY_BSF_EN = 1 << 30,
912 MLX5_MKEY_LEN64 = 1 << 31,
913};
914
915struct mlx5_mkey_seg {
916
917
918
919
920 u8 status;
921 u8 pcie_control;
922 u8 flags;
923 u8 version;
924 __be32 qpn_mkey7_0;
925 u8 rsvd1[4];
926 __be32 flags_pd;
927 __be64 start_addr;
928 __be64 len;
929 __be32 bsfs_octo_size;
930 u8 rsvd2[16];
931 __be32 xlt_oct_size;
932 u8 rsvd3[3];
933 u8 log2_page_size;
934 u8 rsvd4[4];
935};
936
937#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
938
939enum {
940 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
941};
942
943enum {
944 VPORT_STATE_DOWN = 0x0,
945 VPORT_STATE_UP = 0x1,
946};
947
948enum {
949 MLX5_VPORT_ADMIN_STATE_DOWN = 0x0,
950 MLX5_VPORT_ADMIN_STATE_UP = 0x1,
951 MLX5_VPORT_ADMIN_STATE_AUTO = 0x2,
952};
953
954enum {
955 MLX5_L3_PROT_TYPE_IPV4 = 0,
956 MLX5_L3_PROT_TYPE_IPV6 = 1,
957};
958
959enum {
960 MLX5_L4_PROT_TYPE_TCP = 0,
961 MLX5_L4_PROT_TYPE_UDP = 1,
962};
963
964enum {
965 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
966 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
967 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
968 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
969 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
970};
971
972enum {
973 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
974 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
975 MLX5_MATCH_INNER_HEADERS = 1 << 2,
976
977};
978
979enum {
980 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
981 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
982};
983
984enum {
985 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
986 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
987 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
988};
989
990enum mlx5_list_type {
991 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
992 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
993 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
994};
995
996enum {
997 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
998 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
999};
1000
1001enum mlx5_wol_mode {
1002 MLX5_WOL_DISABLE = 0,
1003 MLX5_WOL_SECURED_MAGIC = 1 << 1,
1004 MLX5_WOL_MAGIC = 1 << 2,
1005 MLX5_WOL_ARP = 1 << 3,
1006 MLX5_WOL_BROADCAST = 1 << 4,
1007 MLX5_WOL_MULTICAST = 1 << 5,
1008 MLX5_WOL_UNICAST = 1 << 6,
1009 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
1010};
1011
1012enum mlx5_mpls_supported_fields {
1013 MLX5_FIELD_SUPPORT_MPLS_LABEL = 1 << 0,
1014 MLX5_FIELD_SUPPORT_MPLS_EXP = 1 << 1,
1015 MLX5_FIELD_SUPPORT_MPLS_S_BOS = 1 << 2,
1016 MLX5_FIELD_SUPPORT_MPLS_TTL = 1 << 3
1017};
1018
1019enum mlx5_flex_parser_protos {
1020 MLX5_FLEX_PROTO_CW_MPLS_GRE = 1 << 4,
1021 MLX5_FLEX_PROTO_CW_MPLS_UDP = 1 << 5,
1022};
1023
1024
1025
1026
1027enum mlx5_cap_mode {
1028 HCA_CAP_OPMOD_GET_MAX = 0,
1029 HCA_CAP_OPMOD_GET_CUR = 1,
1030};
1031
1032enum mlx5_cap_type {
1033 MLX5_CAP_GENERAL = 0,
1034 MLX5_CAP_ETHERNET_OFFLOADS,
1035 MLX5_CAP_ODP,
1036 MLX5_CAP_ATOMIC,
1037 MLX5_CAP_ROCE,
1038 MLX5_CAP_IPOIB_OFFLOADS,
1039 MLX5_CAP_IPOIB_ENHANCED_OFFLOADS,
1040 MLX5_CAP_FLOW_TABLE,
1041 MLX5_CAP_ESWITCH_FLOW_TABLE,
1042 MLX5_CAP_ESWITCH,
1043 MLX5_CAP_RESERVED,
1044 MLX5_CAP_VECTOR_CALC,
1045 MLX5_CAP_QOS,
1046 MLX5_CAP_DEBUG,
1047 MLX5_CAP_RESERVED_14,
1048 MLX5_CAP_DEV_MEM,
1049
1050 MLX5_CAP_NUM
1051};
1052
1053enum mlx5_pcam_reg_groups {
1054 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1055};
1056
1057enum mlx5_pcam_feature_groups {
1058 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1059};
1060
1061enum mlx5_mcam_reg_groups {
1062 MLX5_MCAM_REGS_FIRST_128 = 0x0,
1063};
1064
1065enum mlx5_mcam_feature_groups {
1066 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1067};
1068
1069enum mlx5_qcam_reg_groups {
1070 MLX5_QCAM_REGS_FIRST_128 = 0x0,
1071};
1072
1073enum mlx5_qcam_feature_groups {
1074 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1075};
1076
1077
1078#define MLX5_CAP_GEN(mdev, cap) \
1079 MLX5_GET(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1080
1081#define MLX5_CAP_GEN_64(mdev, cap) \
1082 MLX5_GET64(cmd_hca_cap, mdev->caps.hca_cur[MLX5_CAP_GENERAL], cap)
1083
1084#define MLX5_CAP_GEN_MAX(mdev, cap) \
1085 MLX5_GET(cmd_hca_cap, mdev->caps.hca_max[MLX5_CAP_GENERAL], cap)
1086
1087#define MLX5_CAP_ETH(mdev, cap) \
1088 MLX5_GET(per_protocol_networking_offload_caps,\
1089 mdev->caps.hca_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1090
1091#define MLX5_CAP_ETH_MAX(mdev, cap) \
1092 MLX5_GET(per_protocol_networking_offload_caps,\
1093 mdev->caps.hca_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1094
1095#define MLX5_CAP_IPOIB_ENHANCED(mdev, cap) \
1096 MLX5_GET(per_protocol_networking_offload_caps,\
1097 mdev->caps.hca_cur[MLX5_CAP_IPOIB_ENHANCED_OFFLOADS], cap)
1098
1099#define MLX5_CAP_ROCE(mdev, cap) \
1100 MLX5_GET(roce_cap, mdev->caps.hca_cur[MLX5_CAP_ROCE], cap)
1101
1102#define MLX5_CAP_ROCE_MAX(mdev, cap) \
1103 MLX5_GET(roce_cap, mdev->caps.hca_max[MLX5_CAP_ROCE], cap)
1104
1105#define MLX5_CAP_ATOMIC(mdev, cap) \
1106 MLX5_GET(atomic_caps, mdev->caps.hca_cur[MLX5_CAP_ATOMIC], cap)
1107
1108#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1109 MLX5_GET(atomic_caps, mdev->caps.hca_max[MLX5_CAP_ATOMIC], cap)
1110
1111#define MLX5_CAP_FLOWTABLE(mdev, cap) \
1112 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_cur[MLX5_CAP_FLOW_TABLE], cap)
1113
1114#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1115 MLX5_GET(flow_table_nic_cap, mdev->caps.hca_max[MLX5_CAP_FLOW_TABLE], cap)
1116
1117#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1118 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1119
1120#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1121 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1122
1123#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
1124 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
1125
1126#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
1127 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
1128
1129#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
1130 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1131
1132#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
1133 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
1134
1135#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1136 MLX5_GET(flow_table_eswitch_cap, \
1137 mdev->caps.hca_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1138
1139#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1140 MLX5_GET(flow_table_eswitch_cap, \
1141 mdev->caps.hca_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1142
1143#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1144 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1145
1146#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1147 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1148
1149#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1150 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1151
1152#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1153 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1154
1155#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1156 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1157
1158#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1159 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1160
1161#define MLX5_CAP_ESW(mdev, cap) \
1162 MLX5_GET(e_switch_cap, \
1163 mdev->caps.hca_cur[MLX5_CAP_ESWITCH], cap)
1164
1165#define MLX5_CAP_ESW_MAX(mdev, cap) \
1166 MLX5_GET(e_switch_cap, \
1167 mdev->caps.hca_max[MLX5_CAP_ESWITCH], cap)
1168
1169#define MLX5_CAP_ODP(mdev, cap)\
1170 MLX5_GET(odp_cap, mdev->caps.hca_cur[MLX5_CAP_ODP], cap)
1171
1172#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1173 MLX5_GET(vector_calc_cap, \
1174 mdev->caps.hca_cur[MLX5_CAP_VECTOR_CALC], cap)
1175
1176#define MLX5_CAP_QOS(mdev, cap)\
1177 MLX5_GET(qos_cap, mdev->caps.hca_cur[MLX5_CAP_QOS], cap)
1178
1179#define MLX5_CAP_DEBUG(mdev, cap)\
1180 MLX5_GET(debug_cap, mdev->caps.hca_cur[MLX5_CAP_DEBUG], cap)
1181
1182#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1183 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1184
1185#define MLX5_CAP_PCAM_REG(mdev, reg) \
1186 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1187
1188#define MLX5_CAP_MCAM_REG(mdev, reg) \
1189 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1190
1191#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1192 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1193
1194#define MLX5_CAP_QCAM_REG(mdev, fld) \
1195 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1196
1197#define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1198 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1199
1200#define MLX5_CAP_FPGA(mdev, cap) \
1201 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1202
1203#define MLX5_CAP64_FPGA(mdev, cap) \
1204 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1205
1206#define MLX5_CAP_DEV_MEM(mdev, cap)\
1207 MLX5_GET(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1208
1209#define MLX5_CAP64_DEV_MEM(mdev, cap)\
1210 MLX5_GET64(device_mem_cap, mdev->caps.hca_cur[MLX5_CAP_DEV_MEM], cap)
1211
1212enum {
1213 MLX5_CMD_STAT_OK = 0x0,
1214 MLX5_CMD_STAT_INT_ERR = 0x1,
1215 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1216 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1217 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1218 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1219 MLX5_CMD_STAT_RES_BUSY = 0x6,
1220 MLX5_CMD_STAT_LIM_ERR = 0x8,
1221 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1222 MLX5_CMD_STAT_IX_ERR = 0xa,
1223 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1224 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1225 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1226 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1227 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1228 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1229};
1230
1231enum {
1232 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1233 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1234 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1235 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1236 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1237 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1238 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1239 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1240 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1241 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1242};
1243
1244enum {
1245 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1246};
1247
1248static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1249{
1250 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1251 return 0;
1252 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1253}
1254
1255#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 16
1256#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 16
1257#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1258#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1259 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1260 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
1261
1262#endif
1263
