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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39
40
41
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43
44
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46
47
48
49
50
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55
56struct pci_slot {
57 struct pci_bus *bus;
58 struct list_head list;
59 struct hotplug_slot *hotplug;
60 unsigned char number;
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75
76enum {
77
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81
82 PCI_ROM_RESOURCE,
83
84
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97
98 PCI_NUM_RESOURCES,
99
100
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104
105
106
107
108
109
110
111
112
113
114
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123
124#define PCI_NUM_INTX 4
125
126
127
128
129
130typedef int __bitwise pci_power_t;
131
132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
137#define PCI_UNKNOWN ((pci_power_t __force) 5)
138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
145 return pci_power_names[1 + (__force int) state];
146}
147
148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
152
153
154
155
156
157
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
177
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
180
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
186
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208};
209
210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
221};
222
223
224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
230 PCIE_LNK_X12 = 0x0c,
231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
234};
235
236
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
264enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
265enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
266
267struct pci_cap_saved_data {
268 u16 cap_nr;
269 bool cap_extended;
270 unsigned int size;
271 u32 data[0];
272};
273
274struct pci_cap_saved_state {
275 struct hlist_node next;
276 struct pci_cap_saved_data cap;
277};
278
279struct irq_affinity;
280struct pcie_link_state;
281struct pci_vpd;
282struct pci_sriov;
283struct pci_ats;
284
285
286struct pci_dev {
287 struct list_head bus_list;
288 struct pci_bus *bus;
289 struct pci_bus *subordinate;
290
291 void *sysdata;
292 struct proc_dir_entry *procent;
293 struct pci_slot *slot;
294
295 unsigned int devfn;
296 unsigned short vendor;
297 unsigned short device;
298 unsigned short subsystem_vendor;
299 unsigned short subsystem_device;
300 unsigned int class;
301 u8 revision;
302 u8 hdr_type;
303#ifdef CONFIG_PCIEAER
304 u16 aer_cap;
305 struct aer_stats *aer_stats;
306#endif
307 u8 pcie_cap;
308 u8 msi_cap;
309 u8 msix_cap;
310 u8 pcie_mpss:3;
311 u8 rom_base_reg;
312 u8 pin;
313 u16 pcie_flags_reg;
314 unsigned long *dma_alias_mask;
315
316 struct pci_driver *driver;
317 u64 dma_mask;
318
319
320
321
322
323 struct device_dma_parameters dma_parms;
324
325 pci_power_t current_state;
326
327
328 u8 pm_cap;
329 unsigned int pme_support:5;
330
331 unsigned int pme_poll:1;
332 unsigned int d1_support:1;
333 unsigned int d2_support:1;
334 unsigned int no_d1d2:1;
335 unsigned int no_d3cold:1;
336 unsigned int bridge_d3:1;
337 unsigned int d3cold_allowed:1;
338 unsigned int mmio_always_on:1;
339
340 unsigned int wakeup_prepared:1;
341 unsigned int runtime_d3cold:1;
342
343
344
345 unsigned int ignore_hotplug:1;
346 unsigned int hotplug_user_indicators:1;
347
348
349 unsigned int d3_delay;
350 unsigned int d3cold_delay;
351
352#ifdef CONFIG_PCIEASPM
353 struct pcie_link_state *link_state;
354 unsigned int ltr_path:1;
355
356#endif
357 unsigned int eetlp_prefix_path:1;
358
359 pci_channel_state_t error_state;
360 struct device dev;
361
362 int cfg_size;
363
364
365
366
367
368 unsigned int irq;
369 struct resource resource[DEVICE_COUNT_RESOURCE];
370
371 bool match_driver;
372
373 unsigned int transparent:1;
374 unsigned int multifunction:1;
375
376 unsigned int is_busmaster:1;
377 unsigned int no_msi:1;
378 unsigned int no_64bit_msi:1;
379 unsigned int block_cfg_access:1;
380 unsigned int broken_parity_status:1;
381 unsigned int irq_reroute_variant:2;
382 unsigned int msi_enabled:1;
383 unsigned int msix_enabled:1;
384 unsigned int ari_enabled:1;
385 unsigned int ats_enabled:1;
386 unsigned int pasid_enabled:1;
387 unsigned int pri_enabled:1;
388 unsigned int is_managed:1;
389 unsigned int needs_freset:1;
390 unsigned int state_saved:1;
391 unsigned int is_physfn:1;
392 unsigned int is_virtfn:1;
393 unsigned int reset_fn:1;
394 unsigned int is_hotplug_bridge:1;
395 unsigned int shpc_managed:1;
396 unsigned int is_thunderbolt:1;
397 unsigned int __aer_firmware_first_valid:1;
398 unsigned int __aer_firmware_first:1;
399 unsigned int broken_intx_masking:1;
400 unsigned int io_window_1k:1;
401 unsigned int irq_managed:1;
402 unsigned int has_secondary_link:1;
403 unsigned int non_compliant_bars:1;
404 unsigned int is_probed:1;
405 pci_dev_flags_t dev_flags;
406 atomic_t enable_cnt;
407
408 u32 saved_config_space[16];
409 struct hlist_head saved_cap_space;
410 struct bin_attribute *rom_attr;
411 int rom_attr_enabled;
412 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
413 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
414
415#ifdef CONFIG_HOTPLUG_PCI_PCIE
416 unsigned int broken_cmd_compl:1;
417#endif
418#ifdef CONFIG_PCIE_PTM
419 unsigned int ptm_root:1;
420 unsigned int ptm_enabled:1;
421 u8 ptm_granularity;
422#endif
423#ifdef CONFIG_PCI_MSI
424 const struct attribute_group **msi_irq_groups;
425#endif
426 struct pci_vpd *vpd;
427#ifdef CONFIG_PCI_ATS
428 union {
429 struct pci_sriov *sriov;
430 struct pci_dev *physfn;
431 };
432 u16 ats_cap;
433 u8 ats_stu;
434 atomic_t ats_ref_cnt;
435#endif
436#ifdef CONFIG_PCI_PRI
437 u32 pri_reqs_alloc;
438#endif
439#ifdef CONFIG_PCI_PASID
440 u16 pasid_features;
441#endif
442 phys_addr_t rom;
443 size_t romlen;
444 char *driver_override;
445
446 unsigned long priv_flags;
447};
448
449static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
450{
451#ifdef CONFIG_PCI_IOV
452 if (dev->is_virtfn)
453 dev = dev->physfn;
454#endif
455 return dev;
456}
457
458struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
459
460#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
461#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
462
463static inline int pci_channel_offline(struct pci_dev *pdev)
464{
465 return (pdev->error_state != pci_channel_io_normal);
466}
467
468struct pci_host_bridge {
469 struct device dev;
470 struct pci_bus *bus;
471 struct pci_ops *ops;
472 void *sysdata;
473 int busnr;
474 struct list_head windows;
475 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
476 int (*map_irq)(const struct pci_dev *, u8, u8);
477 void (*release_fn)(struct pci_host_bridge *);
478 void *release_data;
479 struct msi_controller *msi;
480 unsigned int ignore_reset_delay:1;
481 unsigned int no_ext_tags:1;
482 unsigned int native_aer:1;
483 unsigned int native_pcie_hotplug:1;
484 unsigned int native_shpc_hotplug:1;
485 unsigned int native_pme:1;
486 unsigned int native_ltr:1;
487
488 resource_size_t (*align_resource)(struct pci_dev *dev,
489 const struct resource *res,
490 resource_size_t start,
491 resource_size_t size,
492 resource_size_t align);
493 unsigned long private[0] ____cacheline_aligned;
494};
495
496#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
497
498static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
499{
500 return (void *)bridge->private;
501}
502
503static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
504{
505 return container_of(priv, struct pci_host_bridge, private);
506}
507
508struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
509struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
510 size_t priv);
511void pci_free_host_bridge(struct pci_host_bridge *bridge);
512struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
513
514void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
515 void (*release_fn)(struct pci_host_bridge *),
516 void *release_data);
517
518int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
519
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531
532
533#define PCI_SUBTRACTIVE_DECODE 0x1
534
535struct pci_bus_resource {
536 struct list_head list;
537 struct resource *res;
538 unsigned int flags;
539};
540
541#define PCI_REGION_FLAG_MASK 0x0fU
542
543struct pci_bus {
544 struct list_head node;
545 struct pci_bus *parent;
546 struct list_head children;
547 struct list_head devices;
548 struct pci_dev *self;
549 struct list_head slots;
550
551 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
552 struct list_head resources;
553 struct resource busn_res;
554
555 struct pci_ops *ops;
556 struct msi_controller *msi;
557 void *sysdata;
558 struct proc_dir_entry *procdir;
559
560 unsigned char number;
561 unsigned char primary;
562 unsigned char max_bus_speed;
563 unsigned char cur_bus_speed;
564#ifdef CONFIG_PCI_DOMAINS_GENERIC
565 int domain_nr;
566#endif
567
568 char name[48];
569
570 unsigned short bridge_ctl;
571 pci_bus_flags_t bus_flags;
572 struct device *bridge;
573 struct device dev;
574 struct bin_attribute *legacy_io;
575 struct bin_attribute *legacy_mem;
576 unsigned int is_added:1;
577};
578
579#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
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588
589static inline bool pci_is_root_bus(struct pci_bus *pbus)
590{
591 return !(pbus->parent);
592}
593
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600
601static inline bool pci_is_bridge(struct pci_dev *dev)
602{
603 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
604 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
605}
606
607#define for_each_pci_bridge(dev, bus) \
608 list_for_each_entry(dev, &bus->devices, bus_list) \
609 if (!pci_is_bridge(dev)) {} else
610
611static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
612{
613 dev = pci_physfn(dev);
614 if (pci_is_root_bus(dev->bus))
615 return NULL;
616
617 return dev->bus->self;
618}
619
620struct device *pci_get_host_bridge_device(struct pci_dev *dev);
621void pci_put_host_bridge_device(struct device *dev);
622
623#ifdef CONFIG_PCI_MSI
624static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
625{
626 return pci_dev->msi_enabled || pci_dev->msix_enabled;
627}
628#else
629static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
630#endif
631
632
633#define PCIBIOS_SUCCESSFUL 0x00
634#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
635#define PCIBIOS_BAD_VENDOR_ID 0x83
636#define PCIBIOS_DEVICE_NOT_FOUND 0x86
637#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
638#define PCIBIOS_SET_FAILED 0x88
639#define PCIBIOS_BUFFER_TOO_SMALL 0x89
640
641
642static inline int pcibios_err_to_errno(int err)
643{
644 if (err <= PCIBIOS_SUCCESSFUL)
645 return err;
646
647 switch (err) {
648 case PCIBIOS_FUNC_NOT_SUPPORTED:
649 return -ENOENT;
650 case PCIBIOS_BAD_VENDOR_ID:
651 return -ENOTTY;
652 case PCIBIOS_DEVICE_NOT_FOUND:
653 return -ENODEV;
654 case PCIBIOS_BAD_REGISTER_NUMBER:
655 return -EFAULT;
656 case PCIBIOS_SET_FAILED:
657 return -EIO;
658 case PCIBIOS_BUFFER_TOO_SMALL:
659 return -ENOSPC;
660 }
661
662 return -ERANGE;
663}
664
665
666
667struct pci_ops {
668 int (*add_bus)(struct pci_bus *bus);
669 void (*remove_bus)(struct pci_bus *bus);
670 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
671 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
672 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
673};
674
675
676
677
678
679int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
680 int reg, int len, u32 *val);
681int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
682 int reg, int len, u32 val);
683
684#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
685typedef u64 pci_bus_addr_t;
686#else
687typedef u32 pci_bus_addr_t;
688#endif
689
690struct pci_bus_region {
691 pci_bus_addr_t start;
692 pci_bus_addr_t end;
693};
694
695struct pci_dynids {
696 spinlock_t lock;
697 struct list_head list;
698};
699
700
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706
707
708typedef unsigned int __bitwise pci_ers_result_t;
709
710enum pci_ers_result {
711
712 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
713
714
715 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
716
717
718 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
719
720
721 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
722
723
724 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
725
726
727 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
728};
729
730
731struct pci_error_handlers {
732
733 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
734 enum pci_channel_state error);
735
736
737 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
738
739
740 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
741
742
743 void (*reset_prepare)(struct pci_dev *dev);
744 void (*reset_done)(struct pci_dev *dev);
745
746
747 void (*resume)(struct pci_dev *dev);
748};
749
750
751struct module;
752struct pci_driver {
753 struct list_head node;
754 const char *name;
755 const struct pci_device_id *id_table;
756 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
757 void (*remove)(struct pci_dev *dev);
758 int (*suspend)(struct pci_dev *dev, pm_message_t state);
759 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
760 int (*resume_early)(struct pci_dev *dev);
761 int (*resume) (struct pci_dev *dev);
762 void (*shutdown) (struct pci_dev *dev);
763 int (*sriov_configure) (struct pci_dev *dev, int num_vfs);
764 const struct pci_error_handlers *err_handler;
765 const struct attribute_group **groups;
766 struct device_driver driver;
767 struct pci_dynids dynids;
768};
769
770#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
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780
781#define PCI_DEVICE(vend,dev) \
782 .vendor = (vend), .device = (dev), \
783 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
784
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794
795#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
796 .vendor = (vend), .device = (dev), \
797 .subvendor = (subvend), .subdevice = (subdev)
798
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807
808#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
809 .class = (dev_class), .class_mask = (dev_class_mask), \
810 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
811 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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822
823#define PCI_VDEVICE(vend, dev) \
824 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
825 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
826
827
828
829
830
831
832
833
834
835
836
837#define PCI_DEVICE_DATA(vend, dev, data) \
838 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
839 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
840 .driver_data = (kernel_ulong_t)(data)
841
842enum {
843 PCI_REASSIGN_ALL_RSRC = 0x00000001,
844 PCI_REASSIGN_ALL_BUS = 0x00000002,
845 PCI_PROBE_ONLY = 0x00000004,
846 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
847 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
848 PCI_COMPAT_DOMAIN_0 = 0x00000020,
849 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
850};
851
852
853#ifdef CONFIG_PCI
854
855extern unsigned int pci_flags;
856
857static inline void pci_set_flags(int flags) { pci_flags = flags; }
858static inline void pci_add_flags(int flags) { pci_flags |= flags; }
859static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
860static inline int pci_has_flag(int flag) { return pci_flags & flag; }
861
862void pcie_bus_configure_settings(struct pci_bus *bus);
863
864enum pcie_bus_config_types {
865 PCIE_BUS_TUNE_OFF,
866 PCIE_BUS_DEFAULT,
867 PCIE_BUS_SAFE,
868 PCIE_BUS_PERFORMANCE,
869 PCIE_BUS_PEER2PEER,
870};
871
872extern enum pcie_bus_config_types pcie_bus_config;
873
874extern struct bus_type pci_bus_type;
875
876
877
878extern struct list_head pci_root_buses;
879
880int no_pci_devices(void);
881
882void pcibios_resource_survey_bus(struct pci_bus *bus);
883void pcibios_bus_add_device(struct pci_dev *pdev);
884void pcibios_add_bus(struct pci_bus *bus);
885void pcibios_remove_bus(struct pci_bus *bus);
886void pcibios_fixup_bus(struct pci_bus *);
887int __must_check pcibios_enable_device(struct pci_dev *, int mask);
888
889char *pcibios_setup(char *str);
890
891
892resource_size_t pcibios_align_resource(void *, const struct resource *,
893 resource_size_t,
894 resource_size_t);
895
896
897void pci_fixup_cardbus(struct pci_bus *);
898
899
900
901void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
902 struct resource *res);
903void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
904 struct pci_bus_region *region);
905void pcibios_scan_specific_bus(int busn);
906struct pci_bus *pci_find_bus(int domain, int busnr);
907void pci_bus_add_devices(const struct pci_bus *bus);
908struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
909struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
910 struct pci_ops *ops, void *sysdata,
911 struct list_head *resources);
912int pci_host_probe(struct pci_host_bridge *bridge);
913int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
914int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
915void pci_bus_release_busn_res(struct pci_bus *b);
916struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
917 struct pci_ops *ops, void *sysdata,
918 struct list_head *resources);
919int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
920struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
921 int busnr);
922void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
923struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
924 const char *name,
925 struct hotplug_slot *hotplug);
926void pci_destroy_slot(struct pci_slot *slot);
927#ifdef CONFIG_SYSFS
928void pci_dev_assign_slot(struct pci_dev *dev);
929#else
930static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
931#endif
932int pci_scan_slot(struct pci_bus *bus, int devfn);
933struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
934void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
935unsigned int pci_scan_child_bus(struct pci_bus *bus);
936void pci_bus_add_device(struct pci_dev *dev);
937void pci_read_bridge_bases(struct pci_bus *child);
938struct resource *pci_find_parent_resource(const struct pci_dev *dev,
939 struct resource *res);
940struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
941u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
942int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
943u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
944struct pci_dev *pci_dev_get(struct pci_dev *dev);
945void pci_dev_put(struct pci_dev *dev);
946void pci_remove_bus(struct pci_bus *b);
947void pci_stop_and_remove_bus_device(struct pci_dev *dev);
948void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
949void pci_stop_root_bus(struct pci_bus *bus);
950void pci_remove_root_bus(struct pci_bus *bus);
951void pci_setup_cardbus(struct pci_bus *bus);
952void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
953void pci_sort_breadthfirst(void);
954#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
955#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
956
957
958
959enum pci_lost_interrupt_reason {
960 PCI_LOST_IRQ_NO_INFORMATION = 0,
961 PCI_LOST_IRQ_DISABLE_MSI,
962 PCI_LOST_IRQ_DISABLE_MSIX,
963 PCI_LOST_IRQ_DISABLE_ACPI,
964};
965enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
966int pci_find_capability(struct pci_dev *dev, int cap);
967int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
968int pci_find_ext_capability(struct pci_dev *dev, int cap);
969int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
970int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
971int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
972struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
973
974struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
975 struct pci_dev *from);
976struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
977 unsigned int ss_vendor, unsigned int ss_device,
978 struct pci_dev *from);
979struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
980struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
981 unsigned int devfn);
982struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
983int pci_dev_present(const struct pci_device_id *ids);
984
985int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
986 int where, u8 *val);
987int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
988 int where, u16 *val);
989int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
990 int where, u32 *val);
991int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
992 int where, u8 val);
993int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
994 int where, u16 val);
995int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
996 int where, u32 val);
997
998int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
999 int where, int size, u32 *val);
1000int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1001 int where, int size, u32 val);
1002int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1003 int where, int size, u32 *val);
1004int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1005 int where, int size, u32 val);
1006
1007struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1008
1009int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1010int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1011int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1012int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1013int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1014int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1015
1016int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1017int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1018int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1019int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1020int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1021 u16 clear, u16 set);
1022int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1023 u32 clear, u32 set);
1024
1025static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1026 u16 set)
1027{
1028 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1029}
1030
1031static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1032 u32 set)
1033{
1034 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1035}
1036
1037static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1038 u16 clear)
1039{
1040 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1041}
1042
1043static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1044 u32 clear)
1045{
1046 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1047}
1048
1049
1050int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1051int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1052int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1053int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1054int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1055int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1056
1057int __must_check pci_enable_device(struct pci_dev *dev);
1058int __must_check pci_enable_device_io(struct pci_dev *dev);
1059int __must_check pci_enable_device_mem(struct pci_dev *dev);
1060int __must_check pci_reenable_device(struct pci_dev *);
1061int __must_check pcim_enable_device(struct pci_dev *pdev);
1062void pcim_pin_device(struct pci_dev *pdev);
1063
1064static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1065{
1066
1067
1068
1069
1070 return !pdev->broken_intx_masking;
1071}
1072
1073static inline int pci_is_enabled(struct pci_dev *pdev)
1074{
1075 return (atomic_read(&pdev->enable_cnt) > 0);
1076}
1077
1078static inline int pci_is_managed(struct pci_dev *pdev)
1079{
1080 return pdev->is_managed;
1081}
1082
1083void pci_disable_device(struct pci_dev *dev);
1084
1085extern unsigned int pcibios_max_latency;
1086void pci_set_master(struct pci_dev *dev);
1087void pci_clear_master(struct pci_dev *dev);
1088
1089int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1090int pci_set_cacheline_size(struct pci_dev *dev);
1091#define HAVE_PCI_SET_MWI
1092int __must_check pci_set_mwi(struct pci_dev *dev);
1093int __must_check pcim_set_mwi(struct pci_dev *dev);
1094int pci_try_set_mwi(struct pci_dev *dev);
1095void pci_clear_mwi(struct pci_dev *dev);
1096void pci_intx(struct pci_dev *dev, int enable);
1097bool pci_check_and_mask_intx(struct pci_dev *dev);
1098bool pci_check_and_unmask_intx(struct pci_dev *dev);
1099int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1100int pci_wait_for_pending_transaction(struct pci_dev *dev);
1101int pcix_get_max_mmrbc(struct pci_dev *dev);
1102int pcix_get_mmrbc(struct pci_dev *dev);
1103int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1104int pcie_get_readrq(struct pci_dev *dev);
1105int pcie_set_readrq(struct pci_dev *dev, int rq);
1106int pcie_get_mps(struct pci_dev *dev);
1107int pcie_set_mps(struct pci_dev *dev, int mps);
1108u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1109 enum pci_bus_speed *speed,
1110 enum pcie_link_width *width);
1111void pcie_print_link_status(struct pci_dev *dev);
1112bool pcie_has_flr(struct pci_dev *dev);
1113int pcie_flr(struct pci_dev *dev);
1114int __pci_reset_function_locked(struct pci_dev *dev);
1115int pci_reset_function(struct pci_dev *dev);
1116int pci_reset_function_locked(struct pci_dev *dev);
1117int pci_try_reset_function(struct pci_dev *dev);
1118int pci_probe_reset_slot(struct pci_slot *slot);
1119int pci_probe_reset_bus(struct pci_bus *bus);
1120int pci_reset_bus(struct pci_dev *dev);
1121void pci_reset_secondary_bus(struct pci_dev *dev);
1122void pcibios_reset_secondary_bus(struct pci_dev *dev);
1123void pci_update_resource(struct pci_dev *dev, int resno);
1124int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1125int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1126void pci_release_resource(struct pci_dev *dev, int resno);
1127int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1128int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1129bool pci_device_is_present(struct pci_dev *pdev);
1130void pci_ignore_hotplug(struct pci_dev *dev);
1131
1132int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1133 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1134 const char *fmt, ...);
1135void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1136
1137
1138int pci_enable_rom(struct pci_dev *pdev);
1139void pci_disable_rom(struct pci_dev *pdev);
1140void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1141void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1142void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1143
1144
1145int pci_save_state(struct pci_dev *dev);
1146void pci_restore_state(struct pci_dev *dev);
1147struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1148int pci_load_saved_state(struct pci_dev *dev,
1149 struct pci_saved_state *state);
1150int pci_load_and_free_saved_state(struct pci_dev *dev,
1151 struct pci_saved_state **state);
1152struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1153struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1154 u16 cap);
1155int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1156int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1157 u16 cap, unsigned int size);
1158int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1159int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1160pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1161bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1162void pci_pme_active(struct pci_dev *dev, bool enable);
1163int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1164int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1165int pci_prepare_to_sleep(struct pci_dev *dev);
1166int pci_back_from_sleep(struct pci_dev *dev);
1167bool pci_dev_run_wake(struct pci_dev *dev);
1168bool pci_check_pme_status(struct pci_dev *dev);
1169void pci_pme_wakeup_bus(struct pci_bus *bus);
1170void pci_d3cold_enable(struct pci_dev *dev);
1171void pci_d3cold_disable(struct pci_dev *dev);
1172bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1173void pci_wakeup_bus(struct pci_bus *bus);
1174void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1175
1176
1177int pci_save_vc_state(struct pci_dev *dev);
1178void pci_restore_vc_state(struct pci_dev *dev);
1179void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1180
1181
1182void set_pcie_port_type(struct pci_dev *pdev);
1183void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1184
1185
1186int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1187unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1188unsigned int pci_rescan_bus(struct pci_bus *bus);
1189void pci_lock_rescan_remove(void);
1190void pci_unlock_rescan_remove(void);
1191
1192
1193ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1194ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1195int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1196
1197
1198resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1199void pci_bus_assign_resources(const struct pci_bus *bus);
1200void pci_bus_claim_resources(struct pci_bus *bus);
1201void pci_bus_size_bridges(struct pci_bus *bus);
1202int pci_claim_resource(struct pci_dev *, int);
1203int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1204void pci_assign_unassigned_resources(void);
1205void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1206void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1207void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1208int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1209void pdev_enable_device(struct pci_dev *);
1210int pci_enable_resources(struct pci_dev *, int mask);
1211void pci_assign_irq(struct pci_dev *dev);
1212struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1213#define HAVE_PCI_REQ_REGIONS 2
1214int __must_check pci_request_regions(struct pci_dev *, const char *);
1215int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1216void pci_release_regions(struct pci_dev *);
1217int __must_check pci_request_region(struct pci_dev *, int, const char *);
1218int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1219void pci_release_region(struct pci_dev *, int);
1220int pci_request_selected_regions(struct pci_dev *, int, const char *);
1221int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1222void pci_release_selected_regions(struct pci_dev *, int);
1223
1224
1225struct pci_bus *pci_bus_get(struct pci_bus *bus);
1226void pci_bus_put(struct pci_bus *bus);
1227void pci_add_resource(struct list_head *resources, struct resource *res);
1228void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1229 resource_size_t offset);
1230void pci_free_resource_list(struct list_head *resources);
1231void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1232 unsigned int flags);
1233struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1234void pci_bus_remove_resources(struct pci_bus *bus);
1235int devm_request_pci_bus_resources(struct device *dev,
1236 struct list_head *resources);
1237
1238
1239int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1240
1241#define pci_bus_for_each_resource(bus, res, i) \
1242 for (i = 0; \
1243 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1244 i++)
1245
1246int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1247 struct resource *res, resource_size_t size,
1248 resource_size_t align, resource_size_t min,
1249 unsigned long type_mask,
1250 resource_size_t (*alignf)(void *,
1251 const struct resource *,
1252 resource_size_t,
1253 resource_size_t),
1254 void *alignf_data);
1255
1256
1257int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1258 resource_size_t size);
1259unsigned long pci_address_to_pio(phys_addr_t addr);
1260phys_addr_t pci_pio_to_address(unsigned long pio);
1261int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1262int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1263 phys_addr_t phys_addr);
1264void pci_unmap_iospace(struct resource *res);
1265void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1266 resource_size_t offset,
1267 resource_size_t size);
1268void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1269 struct resource *res);
1270
1271static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1272{
1273 struct pci_bus_region region;
1274
1275 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1276 return region.start;
1277}
1278
1279
1280int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1281 const char *mod_name);
1282
1283
1284#define pci_register_driver(driver) \
1285 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1286
1287void pci_unregister_driver(struct pci_driver *dev);
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297#define module_pci_driver(__pci_driver) \
1298 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308#define builtin_pci_driver(__pci_driver) \
1309 builtin_driver(__pci_driver, pci_register_driver)
1310
1311struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1312int pci_add_dynid(struct pci_driver *drv,
1313 unsigned int vendor, unsigned int device,
1314 unsigned int subvendor, unsigned int subdevice,
1315 unsigned int class, unsigned int class_mask,
1316 unsigned long driver_data);
1317const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1318 struct pci_dev *dev);
1319int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1320 int pass);
1321
1322void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1323 void *userdata);
1324int pci_cfg_space_size(struct pci_dev *dev);
1325unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1326void pci_setup_bridge(struct pci_bus *bus);
1327resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1328 unsigned long type);
1329
1330#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1331#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1332
1333int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1334 unsigned int command_bits, u32 flags);
1335
1336#define PCI_IRQ_LEGACY (1 << 0)
1337#define PCI_IRQ_MSI (1 << 1)
1338#define PCI_IRQ_MSIX (1 << 2)
1339#define PCI_IRQ_AFFINITY (1 << 3)
1340#define PCI_IRQ_ALL_TYPES \
1341 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1342
1343
1344
1345#include <linux/pci-dma.h>
1346#include <linux/dmapool.h>
1347
1348#define pci_pool dma_pool
1349#define pci_pool_create(name, pdev, size, align, allocation) \
1350 dma_pool_create(name, &pdev->dev, size, align, allocation)
1351#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1352#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1353#define pci_pool_zalloc(pool, flags, handle) \
1354 dma_pool_zalloc(pool, flags, handle)
1355#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1356
1357struct msix_entry {
1358 u32 vector;
1359 u16 entry;
1360};
1361
1362#ifdef CONFIG_PCI_MSI
1363int pci_msi_vec_count(struct pci_dev *dev);
1364void pci_disable_msi(struct pci_dev *dev);
1365int pci_msix_vec_count(struct pci_dev *dev);
1366void pci_disable_msix(struct pci_dev *dev);
1367void pci_restore_msi_state(struct pci_dev *dev);
1368int pci_msi_enabled(void);
1369int pci_enable_msi(struct pci_dev *dev);
1370int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1371 int minvec, int maxvec);
1372static inline int pci_enable_msix_exact(struct pci_dev *dev,
1373 struct msix_entry *entries, int nvec)
1374{
1375 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1376 if (rc < 0)
1377 return rc;
1378 return 0;
1379}
1380int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1381 unsigned int max_vecs, unsigned int flags,
1382 const struct irq_affinity *affd);
1383
1384void pci_free_irq_vectors(struct pci_dev *dev);
1385int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1386const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1387int pci_irq_get_node(struct pci_dev *pdev, int vec);
1388
1389#else
1390static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1391static inline void pci_disable_msi(struct pci_dev *dev) { }
1392static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1393static inline void pci_disable_msix(struct pci_dev *dev) { }
1394static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1395static inline int pci_msi_enabled(void) { return 0; }
1396static inline int pci_enable_msi(struct pci_dev *dev)
1397{ return -ENOSYS; }
1398static inline int pci_enable_msix_range(struct pci_dev *dev,
1399 struct msix_entry *entries, int minvec, int maxvec)
1400{ return -ENOSYS; }
1401static inline int pci_enable_msix_exact(struct pci_dev *dev,
1402 struct msix_entry *entries, int nvec)
1403{ return -ENOSYS; }
1404
1405static inline int
1406pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1407 unsigned int max_vecs, unsigned int flags,
1408 const struct irq_affinity *aff_desc)
1409{
1410 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1411 return 1;
1412 return -ENOSPC;
1413}
1414
1415static inline void pci_free_irq_vectors(struct pci_dev *dev)
1416{
1417}
1418
1419static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1420{
1421 if (WARN_ON_ONCE(nr > 0))
1422 return -EINVAL;
1423 return dev->irq;
1424}
1425static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1426 int vec)
1427{
1428 return cpu_possible_mask;
1429}
1430
1431static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1432{
1433 return first_online_node;
1434}
1435#endif
1436
1437static inline int
1438pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1439 unsigned int max_vecs, unsigned int flags)
1440{
1441 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1442 NULL);
1443}
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1462 struct device_node *node,
1463 const u32 *intspec,
1464 unsigned int intsize,
1465 unsigned long *out_hwirq,
1466 unsigned int *out_type)
1467{
1468 const u32 intx = intspec[0];
1469
1470 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1471 return -EINVAL;
1472
1473 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1474 return 0;
1475}
1476
1477#ifdef CONFIG_PCIEPORTBUS
1478extern bool pcie_ports_disabled;
1479extern bool pcie_ports_native;
1480#else
1481#define pcie_ports_disabled true
1482#define pcie_ports_native false
1483#endif
1484
1485#ifdef CONFIG_PCIEASPM
1486bool pcie_aspm_support_enabled(void);
1487#else
1488static inline bool pcie_aspm_support_enabled(void) { return false; }
1489#endif
1490
1491#ifdef CONFIG_PCIEAER
1492bool pci_aer_available(void);
1493#else
1494static inline bool pci_aer_available(void) { return false; }
1495#endif
1496
1497#ifdef CONFIG_PCIE_ECRC
1498void pcie_set_ecrc_checking(struct pci_dev *dev);
1499void pcie_ecrc_get_policy(char *str);
1500#else
1501static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1502static inline void pcie_ecrc_get_policy(char *str) { }
1503#endif
1504
1505bool pci_ats_disabled(void);
1506
1507#ifdef CONFIG_PCI_ATS
1508
1509void pci_ats_init(struct pci_dev *dev);
1510int pci_enable_ats(struct pci_dev *dev, int ps);
1511void pci_disable_ats(struct pci_dev *dev);
1512int pci_ats_queue_depth(struct pci_dev *dev);
1513#else
1514static inline void pci_ats_init(struct pci_dev *d) { }
1515static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1516static inline void pci_disable_ats(struct pci_dev *d) { }
1517static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1518#endif
1519
1520#ifdef CONFIG_PCIE_PTM
1521int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1522#else
1523static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1524{ return -EINVAL; }
1525#endif
1526
1527void pci_cfg_access_lock(struct pci_dev *dev);
1528bool pci_cfg_access_trylock(struct pci_dev *dev);
1529void pci_cfg_access_unlock(struct pci_dev *dev);
1530
1531
1532
1533
1534
1535
1536#ifdef CONFIG_PCI_DOMAINS
1537extern int pci_domains_supported;
1538#else
1539enum { pci_domains_supported = 0 };
1540static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1541static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1542#endif
1543
1544
1545
1546
1547
1548
1549#ifdef CONFIG_PCI_DOMAINS_GENERIC
1550static inline int pci_domain_nr(struct pci_bus *bus)
1551{
1552 return bus->domain_nr;
1553}
1554#ifdef CONFIG_ACPI
1555int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1556#else
1557static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1558{ return 0; }
1559#endif
1560int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1561#endif
1562
1563
1564typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1565 unsigned int command_bits, u32 flags);
1566void pci_register_set_vga_state(arch_set_vga_state_t func);
1567
1568static inline int
1569pci_request_io_regions(struct pci_dev *pdev, const char *name)
1570{
1571 return pci_request_selected_regions(pdev,
1572 pci_select_bars(pdev, IORESOURCE_IO), name);
1573}
1574
1575static inline void
1576pci_release_io_regions(struct pci_dev *pdev)
1577{
1578 return pci_release_selected_regions(pdev,
1579 pci_select_bars(pdev, IORESOURCE_IO));
1580}
1581
1582static inline int
1583pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1584{
1585 return pci_request_selected_regions(pdev,
1586 pci_select_bars(pdev, IORESOURCE_MEM), name);
1587}
1588
1589static inline void
1590pci_release_mem_regions(struct pci_dev *pdev)
1591{
1592 return pci_release_selected_regions(pdev,
1593 pci_select_bars(pdev, IORESOURCE_MEM));
1594}
1595
1596#else
1597
1598static inline void pci_set_flags(int flags) { }
1599static inline void pci_add_flags(int flags) { }
1600static inline void pci_clear_flags(int flags) { }
1601static inline int pci_has_flag(int flag) { return 0; }
1602
1603
1604
1605
1606
1607#define _PCI_NOP(o, s, t) \
1608 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1609 int where, t val) \
1610 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1611
1612#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1613 _PCI_NOP(o, word, u16 x) \
1614 _PCI_NOP(o, dword, u32 x)
1615_PCI_NOP_ALL(read, *)
1616_PCI_NOP_ALL(write,)
1617
1618static inline struct pci_dev *pci_get_device(unsigned int vendor,
1619 unsigned int device,
1620 struct pci_dev *from)
1621{ return NULL; }
1622
1623static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1624 unsigned int device,
1625 unsigned int ss_vendor,
1626 unsigned int ss_device,
1627 struct pci_dev *from)
1628{ return NULL; }
1629
1630static inline struct pci_dev *pci_get_class(unsigned int class,
1631 struct pci_dev *from)
1632{ return NULL; }
1633
1634#define pci_dev_present(ids) (0)
1635#define no_pci_devices() (1)
1636#define pci_dev_put(dev) do { } while (0)
1637
1638static inline void pci_set_master(struct pci_dev *dev) { }
1639static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1640static inline void pci_disable_device(struct pci_dev *dev) { }
1641static inline int pci_assign_resource(struct pci_dev *dev, int i)
1642{ return -EBUSY; }
1643static inline int __pci_register_driver(struct pci_driver *drv,
1644 struct module *owner)
1645{ return 0; }
1646static inline int pci_register_driver(struct pci_driver *drv)
1647{ return 0; }
1648static inline void pci_unregister_driver(struct pci_driver *drv) { }
1649static inline int pci_find_capability(struct pci_dev *dev, int cap)
1650{ return 0; }
1651static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1652 int cap)
1653{ return 0; }
1654static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1655{ return 0; }
1656
1657
1658static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1659static inline void pci_restore_state(struct pci_dev *dev) { }
1660static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1661{ return 0; }
1662static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1663{ return 0; }
1664static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1665 pm_message_t state)
1666{ return PCI_D0; }
1667static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1668 int enable)
1669{ return 0; }
1670
1671static inline struct resource *pci_find_resource(struct pci_dev *dev,
1672 struct resource *res)
1673{ return NULL; }
1674static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1675{ return -EIO; }
1676static inline void pci_release_regions(struct pci_dev *dev) { }
1677
1678static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1679
1680static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1681static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1682{ return 0; }
1683static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1684
1685static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1686{ return NULL; }
1687static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1688 unsigned int devfn)
1689{ return NULL; }
1690static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1691 unsigned int bus, unsigned int devfn)
1692{ return NULL; }
1693
1694static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1695static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1696
1697#define dev_is_pci(d) (false)
1698#define dev_is_pf(d) (false)
1699static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1700{ return false; }
1701static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1702 struct device_node *node,
1703 const u32 *intspec,
1704 unsigned int intsize,
1705 unsigned long *out_hwirq,
1706 unsigned int *out_type)
1707{ return -EINVAL; }
1708#endif
1709
1710
1711
1712#include <asm/pci.h>
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1727 struct vm_area_struct *vma,
1728 enum pci_mmap_state mmap_state, int write_combine);
1729int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1730 struct vm_area_struct *vma,
1731 enum pci_mmap_state mmap_state, int write_combine);
1732
1733#ifndef arch_can_pci_mmap_wc
1734#define arch_can_pci_mmap_wc() 0
1735#endif
1736
1737#ifndef arch_can_pci_mmap_io
1738#define arch_can_pci_mmap_io() 0
1739#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1740#else
1741int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1742#endif
1743
1744#ifndef pci_root_bus_fwnode
1745#define pci_root_bus_fwnode(bus) NULL
1746#endif
1747
1748
1749
1750
1751
1752#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1753#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1754#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1755#define pci_resource_len(dev,bar) \
1756 ((pci_resource_start((dev), (bar)) == 0 && \
1757 pci_resource_end((dev), (bar)) == \
1758 pci_resource_start((dev), (bar))) ? 0 : \
1759 \
1760 (pci_resource_end((dev), (bar)) - \
1761 pci_resource_start((dev), (bar)) + 1))
1762
1763
1764
1765
1766
1767
1768static inline void *pci_get_drvdata(struct pci_dev *pdev)
1769{
1770 return dev_get_drvdata(&pdev->dev);
1771}
1772
1773static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1774{
1775 dev_set_drvdata(&pdev->dev, data);
1776}
1777
1778static inline const char *pci_name(const struct pci_dev *pdev)
1779{
1780 return dev_name(&pdev->dev);
1781}
1782
1783
1784
1785
1786
1787
1788#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1789void pci_resource_to_user(const struct pci_dev *dev, int bar,
1790 const struct resource *rsrc,
1791 resource_size_t *start, resource_size_t *end);
1792#else
1793static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1794 const struct resource *rsrc, resource_size_t *start,
1795 resource_size_t *end)
1796{
1797 *start = rsrc->start;
1798 *end = rsrc->end;
1799}
1800#endif
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810struct pci_fixup {
1811 u16 vendor;
1812 u16 device;
1813 u32 class;
1814 unsigned int class_shift;
1815#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1816 int hook_offset;
1817#else
1818 void (*hook)(struct pci_dev *dev);
1819#endif
1820};
1821
1822enum pci_fixup_pass {
1823 pci_fixup_early,
1824 pci_fixup_header,
1825 pci_fixup_final,
1826 pci_fixup_enable,
1827 pci_fixup_resume,
1828 pci_fixup_suspend,
1829 pci_fixup_resume_early,
1830 pci_fixup_suspend_late,
1831};
1832
1833#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1834#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1835 class_shift, hook) \
1836 __ADDRESSABLE(hook) \
1837 asm(".section " #sec ", \"a\" \n" \
1838 ".balign 16 \n" \
1839 ".short " #vendor ", " #device " \n" \
1840 ".long " #class ", " #class_shift " \n" \
1841 ".long " #hook " - . \n" \
1842 ".previous \n");
1843#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1844 class_shift, hook) \
1845 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1846 class_shift, hook)
1847#else
1848
1849#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1850 class_shift, hook) \
1851 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1852 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1853 = { vendor, device, class, class_shift, hook };
1854#endif
1855
1856#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1857 class_shift, hook) \
1858 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1859 hook, vendor, device, class, class_shift, hook)
1860#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1861 class_shift, hook) \
1862 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1863 hook, vendor, device, class, class_shift, hook)
1864#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1865 class_shift, hook) \
1866 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1867 hook, vendor, device, class, class_shift, hook)
1868#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1869 class_shift, hook) \
1870 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1871 hook, vendor, device, class, class_shift, hook)
1872#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1873 class_shift, hook) \
1874 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1875 resume##hook, vendor, device, class, class_shift, hook)
1876#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1877 class_shift, hook) \
1878 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1879 resume_early##hook, vendor, device, class, class_shift, hook)
1880#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1881 class_shift, hook) \
1882 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1883 suspend##hook, vendor, device, class, class_shift, hook)
1884#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1885 class_shift, hook) \
1886 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1887 suspend_late##hook, vendor, device, class, class_shift, hook)
1888
1889#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1890 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1891 hook, vendor, device, PCI_ANY_ID, 0, hook)
1892#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1893 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1894 hook, vendor, device, PCI_ANY_ID, 0, hook)
1895#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1896 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1897 hook, vendor, device, PCI_ANY_ID, 0, hook)
1898#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1899 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1900 hook, vendor, device, PCI_ANY_ID, 0, hook)
1901#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1902 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1903 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1904#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1905 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1906 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1907#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1908 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1909 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1910#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1911 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1912 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1913
1914#ifdef CONFIG_PCI_QUIRKS
1915void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1916#else
1917static inline void pci_fixup_device(enum pci_fixup_pass pass,
1918 struct pci_dev *dev) { }
1919#endif
1920
1921void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1922void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1923void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1924int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1925int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1926 const char *name);
1927void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1928
1929extern int pci_pci_problems;
1930#define PCIPCI_FAIL 1
1931#define PCIPCI_TRITON 2
1932#define PCIPCI_NATOMA 4
1933#define PCIPCI_VIAETBF 8
1934#define PCIPCI_VSFX 16
1935#define PCIPCI_ALIMAGIK 32
1936#define PCIAGP_FAIL 64
1937
1938extern unsigned long pci_cardbus_io_size;
1939extern unsigned long pci_cardbus_mem_size;
1940extern u8 pci_dfl_cache_line_size;
1941extern u8 pci_cache_line_size;
1942
1943extern unsigned long pci_hotplug_io_size;
1944extern unsigned long pci_hotplug_mem_size;
1945extern unsigned long pci_hotplug_bus_size;
1946
1947
1948void pcibios_disable_device(struct pci_dev *dev);
1949void pcibios_set_master(struct pci_dev *dev);
1950int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1951 enum pcie_reset_state state);
1952int pcibios_add_device(struct pci_dev *dev);
1953void pcibios_release_device(struct pci_dev *dev);
1954void pcibios_penalize_isa_irq(int irq, int active);
1955int pcibios_alloc_irq(struct pci_dev *dev);
1956void pcibios_free_irq(struct pci_dev *dev);
1957resource_size_t pcibios_default_alignment(void);
1958
1959#ifdef CONFIG_HIBERNATE_CALLBACKS
1960extern struct dev_pm_ops pcibios_pm_ops;
1961#endif
1962
1963#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1964void __init pci_mmcfg_early_init(void);
1965void __init pci_mmcfg_late_init(void);
1966#else
1967static inline void pci_mmcfg_early_init(void) { }
1968static inline void pci_mmcfg_late_init(void) { }
1969#endif
1970
1971int pci_ext_cfg_avail(void);
1972
1973void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1974void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1975
1976#ifdef CONFIG_PCI_IOV
1977int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1978int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1979
1980int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1981void pci_disable_sriov(struct pci_dev *dev);
1982int pci_iov_add_virtfn(struct pci_dev *dev, int id);
1983void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
1984int pci_num_vf(struct pci_dev *dev);
1985int pci_vfs_assigned(struct pci_dev *dev);
1986int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1987int pci_sriov_get_totalvfs(struct pci_dev *dev);
1988int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
1989resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1990void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
1991
1992
1993int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
1994int pcibios_sriov_disable(struct pci_dev *pdev);
1995resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1996#else
1997static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1998{
1999 return -ENOSYS;
2000}
2001static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2002{
2003 return -ENOSYS;
2004}
2005static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2006{ return -ENODEV; }
2007static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2008{
2009 return -ENOSYS;
2010}
2011static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2012 int id) { }
2013static inline void pci_disable_sriov(struct pci_dev *dev) { }
2014static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2015static inline int pci_vfs_assigned(struct pci_dev *dev)
2016{ return 0; }
2017static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2018{ return 0; }
2019static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2020{ return 0; }
2021#define pci_sriov_configure_simple NULL
2022static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2023{ return 0; }
2024static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2025#endif
2026
2027#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2028void pci_hp_create_module_link(struct pci_slot *pci_slot);
2029void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2030#endif
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043static inline int pci_pcie_cap(struct pci_dev *dev)
2044{
2045 return dev->pcie_cap;
2046}
2047
2048
2049
2050
2051
2052
2053
2054static inline bool pci_is_pcie(struct pci_dev *dev)
2055{
2056 return pci_pcie_cap(dev);
2057}
2058
2059
2060
2061
2062
2063static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2064{
2065 return dev->pcie_flags_reg;
2066}
2067
2068
2069
2070
2071
2072static inline int pci_pcie_type(const struct pci_dev *dev)
2073{
2074 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2075}
2076
2077static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2078{
2079 while (1) {
2080 if (!pci_is_pcie(dev))
2081 break;
2082 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2083 return dev;
2084 if (!dev->bus->self)
2085 break;
2086 dev = dev->bus->self;
2087 }
2088 return NULL;
2089}
2090
2091void pci_request_acs(void);
2092bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2093bool pci_acs_path_enabled(struct pci_dev *start,
2094 struct pci_dev *end, u16 acs_flags);
2095int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2096
2097#define PCI_VPD_LRDT 0x80
2098#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2099
2100
2101#define PCI_VPD_LTIN_ID_STRING 0x02
2102#define PCI_VPD_LTIN_RO_DATA 0x10
2103#define PCI_VPD_LTIN_RW_DATA 0x11
2104
2105#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2106#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2107#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2108
2109
2110#define PCI_VPD_STIN_END 0x0f
2111
2112#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2113
2114#define PCI_VPD_SRDT_TIN_MASK 0x78
2115#define PCI_VPD_SRDT_LEN_MASK 0x07
2116#define PCI_VPD_LRDT_TIN_MASK 0x7f
2117
2118#define PCI_VPD_LRDT_TAG_SIZE 3
2119#define PCI_VPD_SRDT_TAG_SIZE 1
2120
2121#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2122
2123#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2124#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2125#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2126#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2127
2128
2129
2130
2131
2132
2133
2134static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2135{
2136 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2137}
2138
2139
2140
2141
2142
2143
2144
2145static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2146{
2147 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2148}
2149
2150
2151
2152
2153
2154
2155
2156static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2157{
2158 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2159}
2160
2161
2162
2163
2164
2165
2166
2167static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2168{
2169 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2170}
2171
2172
2173
2174
2175
2176
2177
2178static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2179{
2180 return info_field[2];
2181}
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2206 unsigned int len, const char *kw);
2207
2208
2209#ifdef CONFIG_OF
2210struct device_node;
2211struct irq_domain;
2212void pci_set_of_node(struct pci_dev *dev);
2213void pci_release_of_node(struct pci_dev *dev);
2214void pci_set_bus_of_node(struct pci_bus *bus);
2215void pci_release_bus_of_node(struct pci_bus *bus);
2216struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2217int pci_parse_request_of_pci_ranges(struct device *dev,
2218 struct list_head *resources,
2219 struct resource **bus_range);
2220
2221
2222struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2223
2224#else
2225static inline void pci_set_of_node(struct pci_dev *dev) { }
2226static inline void pci_release_of_node(struct pci_dev *dev) { }
2227static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2228static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2229static inline struct irq_domain *
2230pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2231static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2232 struct list_head *resources,
2233 struct resource **bus_range)
2234{
2235 return -EINVAL;
2236}
2237#endif
2238
2239static inline struct device_node *
2240pci_device_to_OF_node(const struct pci_dev *pdev)
2241{
2242 return pdev ? pdev->dev.of_node : NULL;
2243}
2244
2245static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2246{
2247 return bus ? bus->dev.of_node : NULL;
2248}
2249
2250#ifdef CONFIG_ACPI
2251struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2252
2253void
2254pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2255#else
2256static inline struct irq_domain *
2257pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2258#endif
2259
2260#ifdef CONFIG_EEH
2261static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2262{
2263 return pdev->dev.archdata.edev;
2264}
2265#endif
2266
2267void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2268bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2269int pci_for_each_dma_alias(struct pci_dev *pdev,
2270 int (*fn)(struct pci_dev *pdev,
2271 u16 alias, void *data), void *data);
2272
2273
2274static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2275{
2276 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2277}
2278static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2279{
2280 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2281}
2282static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2283{
2284 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2285}
2286
2287
2288
2289
2290
2291
2292
2293static inline bool pci_ari_enabled(struct pci_bus *bus)
2294{
2295 return bus->self && bus->self->ari_enabled;
2296}
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2307{
2308 struct pci_dev *parent = pdev;
2309
2310 if (pdev->is_thunderbolt)
2311 return true;
2312
2313 while ((parent = pci_upstream_bridge(parent)))
2314 if (parent->is_thunderbolt)
2315 return true;
2316
2317 return false;
2318}
2319
2320#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2321void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2322#endif
2323
2324
2325#include <linux/pci-dma-compat.h>
2326
2327#define pci_printk(level, pdev, fmt, arg...) \
2328 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2329
2330#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2331#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2332#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2333#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2334#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2335#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2336#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2337#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2338
2339#endif
2340