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16#ifndef _SWITCHTEC_H
17#define _SWITCHTEC_H
18
19#include <linux/pci.h>
20#include <linux/cdev.h>
21
22#define SWITCHTEC_MRPC_PAYLOAD_SIZE 1024
23#define SWITCHTEC_MAX_PFF_CSR 48
24
25#define SWITCHTEC_EVENT_OCCURRED BIT(0)
26#define SWITCHTEC_EVENT_CLEAR BIT(0)
27#define SWITCHTEC_EVENT_EN_LOG BIT(1)
28#define SWITCHTEC_EVENT_EN_CLI BIT(2)
29#define SWITCHTEC_EVENT_EN_IRQ BIT(3)
30#define SWITCHTEC_EVENT_FATAL BIT(4)
31
32enum {
33 SWITCHTEC_GAS_MRPC_OFFSET = 0x0000,
34 SWITCHTEC_GAS_TOP_CFG_OFFSET = 0x1000,
35 SWITCHTEC_GAS_SW_EVENT_OFFSET = 0x1800,
36 SWITCHTEC_GAS_SYS_INFO_OFFSET = 0x2000,
37 SWITCHTEC_GAS_FLASH_INFO_OFFSET = 0x2200,
38 SWITCHTEC_GAS_PART_CFG_OFFSET = 0x4000,
39 SWITCHTEC_GAS_NTB_OFFSET = 0x10000,
40 SWITCHTEC_GAS_PFF_CSR_OFFSET = 0x134000,
41};
42
43struct mrpc_regs {
44 u8 input_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
45 u8 output_data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
46 u32 cmd;
47 u32 status;
48 u32 ret_value;
49} __packed;
50
51enum mrpc_status {
52 SWITCHTEC_MRPC_STATUS_INPROGRESS = 1,
53 SWITCHTEC_MRPC_STATUS_DONE = 2,
54 SWITCHTEC_MRPC_STATUS_ERROR = 0xFF,
55 SWITCHTEC_MRPC_STATUS_INTERRUPTED = 0x100,
56};
57
58struct sw_event_regs {
59 u64 event_report_ctrl;
60 u64 reserved1;
61 u64 part_event_bitmap;
62 u64 reserved2;
63 u32 global_summary;
64 u32 reserved3[3];
65 u32 stack_error_event_hdr;
66 u32 stack_error_event_data;
67 u32 reserved4[4];
68 u32 ppu_error_event_hdr;
69 u32 ppu_error_event_data;
70 u32 reserved5[4];
71 u32 isp_error_event_hdr;
72 u32 isp_error_event_data;
73 u32 reserved6[4];
74 u32 sys_reset_event_hdr;
75 u32 reserved7[5];
76 u32 fw_exception_hdr;
77 u32 reserved8[5];
78 u32 fw_nmi_hdr;
79 u32 reserved9[5];
80 u32 fw_non_fatal_hdr;
81 u32 reserved10[5];
82 u32 fw_fatal_hdr;
83 u32 reserved11[5];
84 u32 twi_mrpc_comp_hdr;
85 u32 twi_mrpc_comp_data;
86 u32 reserved12[4];
87 u32 twi_mrpc_comp_async_hdr;
88 u32 twi_mrpc_comp_async_data;
89 u32 reserved13[4];
90 u32 cli_mrpc_comp_hdr;
91 u32 cli_mrpc_comp_data;
92 u32 reserved14[4];
93 u32 cli_mrpc_comp_async_hdr;
94 u32 cli_mrpc_comp_async_data;
95 u32 reserved15[4];
96 u32 gpio_interrupt_hdr;
97 u32 gpio_interrupt_data;
98 u32 reserved16[4];
99 u32 gfms_event_hdr;
100 u32 gfms_event_data;
101 u32 reserved17[4];
102} __packed;
103
104enum {
105 SWITCHTEC_CFG0_RUNNING = 0x04,
106 SWITCHTEC_CFG1_RUNNING = 0x05,
107 SWITCHTEC_IMG0_RUNNING = 0x03,
108 SWITCHTEC_IMG1_RUNNING = 0x07,
109};
110
111struct sys_info_regs {
112 u32 device_id;
113 u32 device_version;
114 u32 firmware_version;
115 u32 reserved1;
116 u32 vendor_table_revision;
117 u32 table_format_version;
118 u32 partition_id;
119 u32 cfg_file_fmt_version;
120 u16 cfg_running;
121 u16 img_running;
122 u32 reserved2[57];
123 char vendor_id[8];
124 char product_id[16];
125 char product_revision[4];
126 char component_vendor[8];
127 u16 component_id;
128 u8 component_revision;
129} __packed;
130
131struct flash_info_regs {
132 u32 flash_part_map_upd_idx;
133
134 struct active_partition_info {
135 u32 address;
136 u32 build_version;
137 u32 build_string;
138 } active_img;
139
140 struct active_partition_info active_cfg;
141 struct active_partition_info inactive_img;
142 struct active_partition_info inactive_cfg;
143
144 u32 flash_length;
145
146 struct partition_info {
147 u32 address;
148 u32 length;
149 } cfg0;
150
151 struct partition_info cfg1;
152 struct partition_info img0;
153 struct partition_info img1;
154 struct partition_info nvlog;
155 struct partition_info vendor[8];
156};
157
158enum {
159 SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
160 SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
161 SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
162};
163
164struct ntb_info_regs {
165 u8 partition_count;
166 u8 partition_id;
167 u16 reserved1;
168 u64 ep_map;
169 u16 requester_id;
170 u16 reserved2;
171 u32 reserved3[4];
172 struct nt_partition_info {
173 u32 xlink_enabled;
174 u32 target_part_low;
175 u32 target_part_high;
176 u32 reserved;
177 } ntp_info[48];
178} __packed;
179
180struct part_cfg_regs {
181 u32 status;
182 u32 state;
183 u32 port_cnt;
184 u32 usp_port_mode;
185 u32 usp_pff_inst_id;
186 u32 vep_pff_inst_id;
187 u32 dsp_pff_inst_id[47];
188 u32 reserved1[11];
189 u16 vep_vector_number;
190 u16 usp_vector_number;
191 u32 port_event_bitmap;
192 u32 reserved2[3];
193 u32 part_event_summary;
194 u32 reserved3[3];
195 u32 part_reset_hdr;
196 u32 part_reset_data[5];
197 u32 mrpc_comp_hdr;
198 u32 mrpc_comp_data[5];
199 u32 mrpc_comp_async_hdr;
200 u32 mrpc_comp_async_data[5];
201 u32 dyn_binding_hdr;
202 u32 dyn_binding_data[5];
203 u32 reserved4[159];
204} __packed;
205
206enum {
207 NTB_CTRL_PART_OP_LOCK = 0x1,
208 NTB_CTRL_PART_OP_CFG = 0x2,
209 NTB_CTRL_PART_OP_RESET = 0x3,
210
211 NTB_CTRL_PART_STATUS_NORMAL = 0x1,
212 NTB_CTRL_PART_STATUS_LOCKED = 0x2,
213 NTB_CTRL_PART_STATUS_LOCKING = 0x3,
214 NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
215 NTB_CTRL_PART_STATUS_RESETTING = 0x5,
216
217 NTB_CTRL_BAR_VALID = 1 << 0,
218 NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
219 NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
220
221 NTB_CTRL_REQ_ID_EN = 1 << 0,
222
223 NTB_CTRL_LUT_EN = 1 << 0,
224
225 NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
226};
227
228struct ntb_ctrl_regs {
229 u32 partition_status;
230 u32 partition_op;
231 u32 partition_ctrl;
232 u32 bar_setup;
233 u32 bar_error;
234 u16 lut_table_entries;
235 u16 lut_table_offset;
236 u32 lut_error;
237 u16 req_id_table_size;
238 u16 req_id_table_offset;
239 u32 req_id_error;
240 u32 reserved1[7];
241 struct {
242 u32 ctl;
243 u32 win_size;
244 u64 xlate_addr;
245 } bar_entry[6];
246 u32 reserved2[216];
247 u32 req_id_table[256];
248 u32 reserved3[512];
249 u64 lut_entry[512];
250} __packed;
251
252#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
253#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
254
255struct ntb_dbmsg_regs {
256 u32 reserved1[1024];
257 u64 odb;
258 u64 odb_mask;
259 u64 idb;
260 u64 idb_mask;
261 u8 idb_vec_map[64];
262 u32 msg_map;
263 u32 reserved2;
264 struct {
265 u32 msg;
266 u32 status;
267 } omsg[4];
268
269 struct {
270 u32 msg;
271 u8 status;
272 u8 mask;
273 u8 src;
274 u8 reserved;
275 } imsg[4];
276
277 u8 reserved3[3928];
278 u8 msix_table[1024];
279 u8 reserved4[3072];
280 u8 pba[24];
281 u8 reserved5[4072];
282} __packed;
283
284enum {
285 SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
286 SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
287 SWITCHTEC_PART_CFG_EVENT_MRPC_ASYNC_CMP = 1 << 2,
288 SWITCHTEC_PART_CFG_EVENT_DYN_PART_CMP = 1 << 3,
289};
290
291struct pff_csr_regs {
292 u16 vendor_id;
293 u16 device_id;
294 u16 pcicmd;
295 u16 pcists;
296 u32 pci_class;
297 u32 pci_opts;
298 union {
299 u32 pci_bar[6];
300 u64 pci_bar64[3];
301 };
302 u32 pci_cardbus;
303 u32 pci_subsystem_id;
304 u32 pci_expansion_rom;
305 u32 pci_cap_ptr;
306 u32 reserved1;
307 u32 pci_irq;
308 u32 pci_cap_region[48];
309 u32 pcie_cap_region[448];
310 u32 indirect_gas_window[128];
311 u32 indirect_gas_window_off;
312 u32 reserved[127];
313 u32 pff_event_summary;
314 u32 reserved2[3];
315 u32 aer_in_p2p_hdr;
316 u32 aer_in_p2p_data[5];
317 u32 aer_in_vep_hdr;
318 u32 aer_in_vep_data[5];
319 u32 dpc_hdr;
320 u32 dpc_data[5];
321 u32 cts_hdr;
322 u32 cts_data[5];
323 u32 reserved3[6];
324 u32 hotplug_hdr;
325 u32 hotplug_data[5];
326 u32 ier_hdr;
327 u32 ier_data[5];
328 u32 threshold_hdr;
329 u32 threshold_data[5];
330 u32 power_mgmt_hdr;
331 u32 power_mgmt_data[5];
332 u32 tlp_throttling_hdr;
333 u32 tlp_throttling_data[5];
334 u32 force_speed_hdr;
335 u32 force_speed_data[5];
336 u32 credit_timeout_hdr;
337 u32 credit_timeout_data[5];
338 u32 link_state_hdr;
339 u32 link_state_data[5];
340 u32 reserved4[174];
341} __packed;
342
343struct switchtec_ntb;
344
345struct switchtec_dev {
346 struct pci_dev *pdev;
347 struct device dev;
348 struct cdev cdev;
349
350 int partition;
351 int partition_count;
352 int pff_csr_count;
353 char pff_local[SWITCHTEC_MAX_PFF_CSR];
354
355 void __iomem *mmio;
356 struct mrpc_regs __iomem *mmio_mrpc;
357 struct sw_event_regs __iomem *mmio_sw_event;
358 struct sys_info_regs __iomem *mmio_sys_info;
359 struct flash_info_regs __iomem *mmio_flash_info;
360 struct ntb_info_regs __iomem *mmio_ntb;
361 struct part_cfg_regs __iomem *mmio_part_cfg;
362 struct part_cfg_regs __iomem *mmio_part_cfg_all;
363 struct pff_csr_regs __iomem *mmio_pff_csr;
364
365
366
367
368
369 struct mutex mrpc_mutex;
370 struct list_head mrpc_queue;
371 int mrpc_busy;
372 struct work_struct mrpc_work;
373 struct delayed_work mrpc_timeout;
374 bool alive;
375
376 wait_queue_head_t event_wq;
377 atomic_t event_cnt;
378
379 struct work_struct link_event_work;
380 void (*link_notifier)(struct switchtec_dev *stdev);
381 u8 link_event_count[SWITCHTEC_MAX_PFF_CSR];
382
383 struct switchtec_ntb *sndev;
384};
385
386static inline struct switchtec_dev *to_stdev(struct device *dev)
387{
388 return container_of(dev, struct switchtec_dev, dev);
389}
390
391extern struct class *switchtec_class;
392
393#endif
394
