1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30#define SOURCEFILE_NAME "hpi6205.c"
31
32#include "hpi_internal.h"
33#include "hpimsginit.h"
34#include "hpidebug.h"
35#include "hpi6205.h"
36#include "hpidspcd.h"
37#include "hpicmn.h"
38
39
40
41#define HPI6205_ERROR_BASE 1000
42
43
44#define HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT 1015
45#define HPI6205_ERROR_MSG_RESP_TIMEOUT 1016
46
47
48#define HPI6205_ERROR_6205_NO_IRQ 1002
49#define HPI6205_ERROR_6205_INIT_FAILED 1003
50#define HPI6205_ERROR_6205_REG 1006
51#define HPI6205_ERROR_6205_DSPPAGE 1007
52#define HPI6205_ERROR_C6713_HPIC 1009
53#define HPI6205_ERROR_C6713_HPIA 1010
54#define HPI6205_ERROR_C6713_PLL 1011
55#define HPI6205_ERROR_DSP_INTMEM 1012
56#define HPI6205_ERROR_DSP_EXTMEM 1013
57#define HPI6205_ERROR_DSP_PLD 1014
58#define HPI6205_ERROR_6205_EEPROM 1017
59#define HPI6205_ERROR_DSP_EMIF1 1018
60#define HPI6205_ERROR_DSP_EMIF2 1019
61#define HPI6205_ERROR_DSP_EMIF3 1020
62#define HPI6205_ERROR_DSP_EMIF4 1021
63
64
65
66
67#define C6205_HSR_INTSRC 0x01
68#define C6205_HSR_INTAVAL 0x02
69#define C6205_HSR_INTAM 0x04
70#define C6205_HSR_CFGERR 0x08
71#define C6205_HSR_EEREAD 0x10
72
73#define C6205_HDCR_WARMRESET 0x01
74#define C6205_HDCR_DSPINT 0x02
75#define C6205_HDCR_PCIBOOT 0x04
76
77
78#define C6205_DSPP_MAP1 0x400
79
80
81
82
83
84
85
86#define C6205_BAR1_PCI_IO_OFFSET (0x027FFF0L)
87#define C6205_BAR1_HSR (C6205_BAR1_PCI_IO_OFFSET)
88#define C6205_BAR1_HDCR (C6205_BAR1_PCI_IO_OFFSET+4)
89#define C6205_BAR1_DSPP (C6205_BAR1_PCI_IO_OFFSET+8)
90
91
92#define C6205_BAR0_TIMER1_CTL (0x01980000L)
93
94
95#define HPICL_ADDR 0x01400000L
96#define HPICH_ADDR 0x01400004L
97#define HPIAL_ADDR 0x01410000L
98#define HPIAH_ADDR 0x01410004L
99#define HPIDIL_ADDR 0x01420000L
100#define HPIDIH_ADDR 0x01420004L
101#define HPIDL_ADDR 0x01430000L
102#define HPIDH_ADDR 0x01430004L
103
104#define C6713_EMIF_GCTL 0x01800000
105#define C6713_EMIF_CE1 0x01800004
106#define C6713_EMIF_CE0 0x01800008
107#define C6713_EMIF_CE2 0x01800010
108#define C6713_EMIF_CE3 0x01800014
109#define C6713_EMIF_SDRAMCTL 0x01800018
110#define C6713_EMIF_SDRAMTIMING 0x0180001C
111#define C6713_EMIF_SDRAMEXT 0x01800020
112
113struct hpi_hw_obj {
114
115 __iomem u32 *prHSR;
116 __iomem u32 *prHDCR;
117 __iomem u32 *prDSPP;
118
119 u32 dsp_page;
120
121 struct consistent_dma_area h_locked_mem;
122 struct bus_master_interface *p_interface_buffer;
123
124 u16 flag_outstream_just_reset[HPI_MAX_STREAMS];
125
126 struct consistent_dma_area instream_host_buffers[HPI_MAX_STREAMS];
127 struct consistent_dma_area outstream_host_buffers[HPI_MAX_STREAMS];
128
129 u32 instream_host_buffer_size[HPI_MAX_STREAMS];
130 u32 outstream_host_buffer_size[HPI_MAX_STREAMS];
131
132 struct consistent_dma_area h_control_cache;
133 struct hpi_control_cache *p_cache;
134};
135
136
137
138
139#define check_before_bbm_copy(status, p_bbm_data, l_first_write, l_second_write)
140
141static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us);
142
143static void send_dsp_command(struct hpi_hw_obj *phw, int cmd);
144
145static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
146 u32 *pos_error_code);
147
148static u16 message_response_sequence(struct hpi_adapter_obj *pao,
149 struct hpi_message *phm, struct hpi_response *phr);
150
151static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
152 struct hpi_response *phr);
153
154#define HPI6205_TIMEOUT 1000000
155
156static void subsys_create_adapter(struct hpi_message *phm,
157 struct hpi_response *phr);
158static void adapter_delete(struct hpi_adapter_obj *pao,
159 struct hpi_message *phm, struct hpi_response *phr);
160
161static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
162 u32 *pos_error_code);
163
164static void delete_adapter_obj(struct hpi_adapter_obj *pao);
165
166static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
167 u32 message);
168
169static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
170 struct hpi_message *phm, struct hpi_response *phr);
171
172static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
173 struct hpi_message *phm, struct hpi_response *phr);
174
175static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
176 struct hpi_message *phm, struct hpi_response *phr);
177static void outstream_write(struct hpi_adapter_obj *pao,
178 struct hpi_message *phm, struct hpi_response *phr);
179
180static void outstream_get_info(struct hpi_adapter_obj *pao,
181 struct hpi_message *phm, struct hpi_response *phr);
182
183static void outstream_start(struct hpi_adapter_obj *pao,
184 struct hpi_message *phm, struct hpi_response *phr);
185
186static void outstream_open(struct hpi_adapter_obj *pao,
187 struct hpi_message *phm, struct hpi_response *phr);
188
189static void outstream_reset(struct hpi_adapter_obj *pao,
190 struct hpi_message *phm, struct hpi_response *phr);
191
192static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
193 struct hpi_message *phm, struct hpi_response *phr);
194
195static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
196 struct hpi_message *phm, struct hpi_response *phr);
197
198static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
199 struct hpi_message *phm, struct hpi_response *phr);
200
201static void instream_read(struct hpi_adapter_obj *pao,
202 struct hpi_message *phm, struct hpi_response *phr);
203
204static void instream_get_info(struct hpi_adapter_obj *pao,
205 struct hpi_message *phm, struct hpi_response *phr);
206
207static void instream_start(struct hpi_adapter_obj *pao,
208 struct hpi_message *phm, struct hpi_response *phr);
209
210static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
211 u32 address);
212
213static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
214 int dsp_index, u32 address, u32 data);
215
216static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao,
217 int dsp_index);
218
219static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
220 u32 address, u32 length);
221
222static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
223 int dsp_index);
224
225static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
226 int dsp_index);
227
228static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index);
229
230
231
232static void subsys_message(struct hpi_adapter_obj *pao,
233 struct hpi_message *phm, struct hpi_response *phr)
234{
235 switch (phm->function) {
236 case HPI_SUBSYS_CREATE_ADAPTER:
237 subsys_create_adapter(phm, phr);
238 break;
239 default:
240 phr->error = HPI_ERROR_INVALID_FUNC;
241 break;
242 }
243}
244
245static void control_message(struct hpi_adapter_obj *pao,
246 struct hpi_message *phm, struct hpi_response *phr)
247{
248
249 struct hpi_hw_obj *phw = pao->priv;
250 u16 pending_cache_error = 0;
251
252 switch (phm->function) {
253 case HPI_CONTROL_GET_STATE:
254 if (pao->has_control_cache) {
255 rmb();
256 if (hpi_check_control_cache(phw->p_cache, phm, phr)) {
257 break;
258 } else if (phm->u.c.attribute == HPI_METER_PEAK) {
259 pending_cache_error =
260 HPI_ERROR_CONTROL_CACHING;
261 }
262 }
263 hw_message(pao, phm, phr);
264 if (pending_cache_error && !phr->error)
265 phr->error = pending_cache_error;
266 break;
267 case HPI_CONTROL_GET_INFO:
268 hw_message(pao, phm, phr);
269 break;
270 case HPI_CONTROL_SET_STATE:
271 hw_message(pao, phm, phr);
272 if (pao->has_control_cache)
273 hpi_cmn_control_cache_sync_to_msg(phw->p_cache, phm,
274 phr);
275 break;
276 default:
277 phr->error = HPI_ERROR_INVALID_FUNC;
278 break;
279 }
280}
281
282static void adapter_message(struct hpi_adapter_obj *pao,
283 struct hpi_message *phm, struct hpi_response *phr)
284{
285 switch (phm->function) {
286 case HPI_ADAPTER_DELETE:
287 adapter_delete(pao, phm, phr);
288 break;
289 default:
290 hw_message(pao, phm, phr);
291 break;
292 }
293}
294
295static void outstream_message(struct hpi_adapter_obj *pao,
296 struct hpi_message *phm, struct hpi_response *phr)
297{
298
299 if (phm->obj_index >= HPI_MAX_STREAMS) {
300 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
301 HPI_DEBUG_LOG(WARNING,
302 "Message referencing invalid stream %d "
303 "on adapter index %d\n", phm->obj_index,
304 phm->adapter_index);
305 return;
306 }
307
308 switch (phm->function) {
309 case HPI_OSTREAM_WRITE:
310 outstream_write(pao, phm, phr);
311 break;
312 case HPI_OSTREAM_GET_INFO:
313 outstream_get_info(pao, phm, phr);
314 break;
315 case HPI_OSTREAM_HOSTBUFFER_ALLOC:
316 outstream_host_buffer_allocate(pao, phm, phr);
317 break;
318 case HPI_OSTREAM_HOSTBUFFER_GET_INFO:
319 outstream_host_buffer_get_info(pao, phm, phr);
320 break;
321 case HPI_OSTREAM_HOSTBUFFER_FREE:
322 outstream_host_buffer_free(pao, phm, phr);
323 break;
324 case HPI_OSTREAM_START:
325 outstream_start(pao, phm, phr);
326 break;
327 case HPI_OSTREAM_OPEN:
328 outstream_open(pao, phm, phr);
329 break;
330 case HPI_OSTREAM_RESET:
331 outstream_reset(pao, phm, phr);
332 break;
333 default:
334 hw_message(pao, phm, phr);
335 break;
336 }
337}
338
339static void instream_message(struct hpi_adapter_obj *pao,
340 struct hpi_message *phm, struct hpi_response *phr)
341{
342
343 if (phm->obj_index >= HPI_MAX_STREAMS) {
344 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
345 HPI_DEBUG_LOG(WARNING,
346 "Message referencing invalid stream %d "
347 "on adapter index %d\n", phm->obj_index,
348 phm->adapter_index);
349 return;
350 }
351
352 switch (phm->function) {
353 case HPI_ISTREAM_READ:
354 instream_read(pao, phm, phr);
355 break;
356 case HPI_ISTREAM_GET_INFO:
357 instream_get_info(pao, phm, phr);
358 break;
359 case HPI_ISTREAM_HOSTBUFFER_ALLOC:
360 instream_host_buffer_allocate(pao, phm, phr);
361 break;
362 case HPI_ISTREAM_HOSTBUFFER_GET_INFO:
363 instream_host_buffer_get_info(pao, phm, phr);
364 break;
365 case HPI_ISTREAM_HOSTBUFFER_FREE:
366 instream_host_buffer_free(pao, phm, phr);
367 break;
368 case HPI_ISTREAM_START:
369 instream_start(pao, phm, phr);
370 break;
371 default:
372 hw_message(pao, phm, phr);
373 break;
374 }
375}
376
377
378
379
380
381static
382void _HPI_6205(struct hpi_adapter_obj *pao, struct hpi_message *phm,
383 struct hpi_response *phr)
384{
385 if (pao && (pao->dsp_crashed >= 10)
386 && (phm->function != HPI_ADAPTER_DEBUG_READ)) {
387
388 hpi_init_response(phr, phm->object, phm->function,
389 HPI_ERROR_DSP_HARDWARE);
390 HPI_DEBUG_LOG(WARNING, " %d,%d dsp crashed.\n", phm->object,
391 phm->function);
392 return;
393 }
394
395
396 if (phm->function != HPI_SUBSYS_CREATE_ADAPTER)
397 phr->error = HPI_ERROR_PROCESSING_MESSAGE;
398
399 HPI_DEBUG_LOG(VERBOSE, "start of switch\n");
400 switch (phm->type) {
401 case HPI_TYPE_REQUEST:
402 switch (phm->object) {
403 case HPI_OBJ_SUBSYSTEM:
404 subsys_message(pao, phm, phr);
405 break;
406
407 case HPI_OBJ_ADAPTER:
408 adapter_message(pao, phm, phr);
409 break;
410
411 case HPI_OBJ_CONTROL:
412 control_message(pao, phm, phr);
413 break;
414
415 case HPI_OBJ_OSTREAM:
416 outstream_message(pao, phm, phr);
417 break;
418
419 case HPI_OBJ_ISTREAM:
420 instream_message(pao, phm, phr);
421 break;
422
423 default:
424 hw_message(pao, phm, phr);
425 break;
426 }
427 break;
428
429 default:
430 phr->error = HPI_ERROR_INVALID_TYPE;
431 break;
432 }
433}
434
435void HPI_6205(struct hpi_message *phm, struct hpi_response *phr)
436{
437 struct hpi_adapter_obj *pao = NULL;
438
439 if (phm->object != HPI_OBJ_SUBSYSTEM) {
440
441 pao = hpi_find_adapter(phm->adapter_index);
442 } else {
443
444 _HPI_6205(NULL, phm, phr);
445 return;
446 }
447
448 if (pao)
449 _HPI_6205(pao, phm, phr);
450 else
451 hpi_init_response(phr, phm->object, phm->function,
452 HPI_ERROR_BAD_ADAPTER_NUMBER);
453}
454
455
456
457
458
459
460
461
462
463static void subsys_create_adapter(struct hpi_message *phm,
464 struct hpi_response *phr)
465{
466
467 struct hpi_adapter_obj ao;
468 u32 os_error_code;
469 u16 err;
470
471 HPI_DEBUG_LOG(DEBUG, " subsys_create_adapter\n");
472
473 memset(&ao, 0, sizeof(ao));
474
475 ao.priv = kzalloc(sizeof(struct hpi_hw_obj), GFP_KERNEL);
476 if (!ao.priv) {
477 HPI_DEBUG_LOG(ERROR, "can't get mem for adapter object\n");
478 phr->error = HPI_ERROR_MEMORY_ALLOC;
479 return;
480 }
481
482 ao.pci = *phm->u.s.resource.r.pci;
483 err = create_adapter_obj(&ao, &os_error_code);
484 if (err) {
485 delete_adapter_obj(&ao);
486 if (err >= HPI_ERROR_BACKEND_BASE) {
487 phr->error = HPI_ERROR_DSP_BOOTLOAD;
488 phr->specific_error = err;
489 } else {
490 phr->error = err;
491 }
492 phr->u.s.data = os_error_code;
493 return;
494 }
495
496 phr->u.s.adapter_type = ao.type;
497 phr->u.s.adapter_index = ao.index;
498 phr->error = 0;
499}
500
501
502static void adapter_delete(struct hpi_adapter_obj *pao,
503 struct hpi_message *phm, struct hpi_response *phr)
504{
505 struct hpi_hw_obj *phw;
506
507 if (!pao) {
508 phr->error = HPI_ERROR_INVALID_OBJ_INDEX;
509 return;
510 }
511 phw = pao->priv;
512
513
514 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
515
516 iowrite32(C6205_HDCR_WARMRESET, phw->prHDCR);
517
518 delete_adapter_obj(pao);
519 hpi_delete_adapter(pao);
520 phr->error = 0;
521}
522
523
524
525
526static u16 create_adapter_obj(struct hpi_adapter_obj *pao,
527 u32 *pos_error_code)
528{
529 struct hpi_hw_obj *phw = pao->priv;
530 struct bus_master_interface *interface;
531 u32 phys_addr;
532 int i;
533 u16 err;
534
535
536 pao->dsp_crashed = 0;
537
538 for (i = 0; i < HPI_MAX_STREAMS; i++)
539 phw->flag_outstream_just_reset[i] = 1;
540
541
542 phw->prHSR =
543 pao->pci.ap_mem_base[1] +
544 C6205_BAR1_HSR / sizeof(*pao->pci.ap_mem_base[1]);
545 phw->prHDCR =
546 pao->pci.ap_mem_base[1] +
547 C6205_BAR1_HDCR / sizeof(*pao->pci.ap_mem_base[1]);
548 phw->prDSPP =
549 pao->pci.ap_mem_base[1] +
550 C6205_BAR1_DSPP / sizeof(*pao->pci.ap_mem_base[1]);
551
552 pao->has_control_cache = 0;
553
554 if (hpios_locked_mem_alloc(&phw->h_locked_mem,
555 sizeof(struct bus_master_interface),
556 pao->pci.pci_dev))
557 phw->p_interface_buffer = NULL;
558 else if (hpios_locked_mem_get_virt_addr(&phw->h_locked_mem,
559 (void *)&phw->p_interface_buffer))
560 phw->p_interface_buffer = NULL;
561
562 HPI_DEBUG_LOG(DEBUG, "interface buffer address %p\n",
563 phw->p_interface_buffer);
564
565 if (phw->p_interface_buffer) {
566 memset((void *)phw->p_interface_buffer, 0,
567 sizeof(struct bus_master_interface));
568 phw->p_interface_buffer->dsp_ack = H620_HIF_UNKNOWN;
569 }
570
571 err = adapter_boot_load_dsp(pao, pos_error_code);
572 if (err) {
573 HPI_DEBUG_LOG(ERROR, "DSP code load failed\n");
574
575
576 return err;
577 }
578 HPI_DEBUG_LOG(INFO, "load DSP code OK\n");
579
580
581 if (!phw->p_interface_buffer)
582 return HPI_ERROR_MEMORY_ALLOC;
583
584 interface = phw->p_interface_buffer;
585
586
587 if (!wait_dsp_ack(phw, H620_HIF_RESET, HPI6205_TIMEOUT * 10)) {
588 HPI_DEBUG_LOG(ERROR, "timed out waiting reset state \n");
589 return HPI6205_ERROR_6205_INIT_FAILED;
590 }
591
592
593
594
595 if (interface->control_cache.number_of_controls) {
596 u8 *p_control_cache_virtual;
597
598 err = hpios_locked_mem_alloc(&phw->h_control_cache,
599 interface->control_cache.size_in_bytes,
600 pao->pci.pci_dev);
601 if (!err)
602 err = hpios_locked_mem_get_virt_addr(&phw->
603 h_control_cache,
604 (void *)&p_control_cache_virtual);
605 if (!err) {
606 memset(p_control_cache_virtual, 0,
607 interface->control_cache.size_in_bytes);
608
609 phw->p_cache =
610 hpi_alloc_control_cache(interface->
611 control_cache.number_of_controls,
612 interface->control_cache.size_in_bytes,
613 p_control_cache_virtual);
614
615 if (!phw->p_cache)
616 err = HPI_ERROR_MEMORY_ALLOC;
617 }
618 if (!err) {
619 err = hpios_locked_mem_get_phys_addr(&phw->
620 h_control_cache, &phys_addr);
621 interface->control_cache.physical_address32 =
622 phys_addr;
623 }
624
625 if (!err)
626 pao->has_control_cache = 1;
627 else {
628 if (hpios_locked_mem_valid(&phw->h_control_cache))
629 hpios_locked_mem_free(&phw->h_control_cache);
630 pao->has_control_cache = 0;
631 }
632 }
633 send_dsp_command(phw, H620_HIF_IDLE);
634
635 {
636 struct hpi_message hm;
637 struct hpi_response hr;
638
639 HPI_DEBUG_LOG(VERBOSE, "init ADAPTER_GET_INFO\n");
640 memset(&hm, 0, sizeof(hm));
641
642 hm.type = HPI_TYPE_REQUEST;
643 hm.size = sizeof(hm);
644 hm.object = HPI_OBJ_ADAPTER;
645 hm.function = HPI_ADAPTER_GET_INFO;
646
647 memset(&hr, 0, sizeof(hr));
648 hr.size = sizeof(hr);
649
650 err = message_response_sequence(pao, &hm, &hr);
651 if (err) {
652 HPI_DEBUG_LOG(ERROR, "message transport error %d\n",
653 err);
654 return err;
655 }
656 if (hr.error)
657 return hr.error;
658
659 pao->type = hr.u.ax.info.adapter_type;
660 pao->index = hr.u.ax.info.adapter_index;
661
662 HPI_DEBUG_LOG(VERBOSE,
663 "got adapter info type %x index %d serial %d\n",
664 hr.u.ax.info.adapter_type, hr.u.ax.info.adapter_index,
665 hr.u.ax.info.serial_number);
666 }
667
668 if (phw->p_cache)
669 phw->p_cache->adap_idx = pao->index;
670
671 HPI_DEBUG_LOG(INFO, "bootload DSP OK\n");
672
673 pao->irq_query_and_clear = adapter_irq_query_and_clear;
674 pao->instream_host_buffer_status =
675 phw->p_interface_buffer->instream_host_buffer_status;
676 pao->outstream_host_buffer_status =
677 phw->p_interface_buffer->outstream_host_buffer_status;
678
679 return hpi_add_adapter(pao);
680}
681
682
683
684
685
686static void delete_adapter_obj(struct hpi_adapter_obj *pao)
687{
688 struct hpi_hw_obj *phw = pao->priv;
689 int i;
690
691 if (hpios_locked_mem_valid(&phw->h_control_cache)) {
692 hpios_locked_mem_free(&phw->h_control_cache);
693 hpi_free_control_cache(phw->p_cache);
694 }
695
696 if (hpios_locked_mem_valid(&phw->h_locked_mem)) {
697 hpios_locked_mem_free(&phw->h_locked_mem);
698 phw->p_interface_buffer = NULL;
699 }
700
701 for (i = 0; i < HPI_MAX_STREAMS; i++)
702 if (hpios_locked_mem_valid(&phw->instream_host_buffers[i])) {
703 hpios_locked_mem_free(&phw->instream_host_buffers[i]);
704
705 phw->instream_host_buffer_size[i] = 0;
706 }
707
708 for (i = 0; i < HPI_MAX_STREAMS; i++)
709 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[i])) {
710 hpios_locked_mem_free(&phw->outstream_host_buffers
711 [i]);
712 phw->outstream_host_buffer_size[i] = 0;
713 }
714 kfree(phw);
715}
716
717
718
719static int adapter_irq_query_and_clear(struct hpi_adapter_obj *pao,
720 u32 message)
721{
722 struct hpi_hw_obj *phw = pao->priv;
723 u32 hsr = 0;
724
725 hsr = ioread32(phw->prHSR);
726 if (hsr & C6205_HSR_INTSRC) {
727
728 iowrite32(C6205_HSR_INTSRC, phw->prHSR);
729 return HPI_IRQ_MIXER;
730 }
731
732 return HPI_IRQ_NONE;
733}
734
735
736
737
738
739
740static void outstream_host_buffer_allocate(struct hpi_adapter_obj *pao,
741 struct hpi_message *phm, struct hpi_response *phr)
742{
743 u16 err = 0;
744 u32 command = phm->u.d.u.buffer.command;
745 struct hpi_hw_obj *phw = pao->priv;
746 struct bus_master_interface *interface = phw->p_interface_buffer;
747
748 hpi_init_response(phr, phm->object, phm->function, 0);
749
750 if (command == HPI_BUFFER_CMD_EXTERNAL
751 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
752
753
754
755 phm->u.d.u.buffer.buffer_size =
756 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
757
758
759 phr->u.d.u.stream_info.data_available =
760 phw->outstream_host_buffer_size[phm->obj_index];
761 phr->u.d.u.stream_info.buffer_size =
762 phm->u.d.u.buffer.buffer_size;
763
764 if (phw->outstream_host_buffer_size[phm->obj_index] ==
765 phm->u.d.u.buffer.buffer_size) {
766
767 return;
768 }
769
770 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
771 obj_index]))
772 hpios_locked_mem_free(&phw->outstream_host_buffers
773 [phm->obj_index]);
774
775 err = hpios_locked_mem_alloc(&phw->outstream_host_buffers
776 [phm->obj_index], phm->u.d.u.buffer.buffer_size,
777 pao->pci.pci_dev);
778
779 if (err) {
780 phr->error = HPI_ERROR_INVALID_DATASIZE;
781 phw->outstream_host_buffer_size[phm->obj_index] = 0;
782 return;
783 }
784
785 err = hpios_locked_mem_get_phys_addr
786 (&phw->outstream_host_buffers[phm->obj_index],
787 &phm->u.d.u.buffer.pci_address);
788
789
790
791
792 phr->u.d.u.stream_info.auxiliary_data_available =
793 phm->u.d.u.buffer.pci_address;
794
795 if (err) {
796 hpios_locked_mem_free(&phw->outstream_host_buffers
797 [phm->obj_index]);
798 phw->outstream_host_buffer_size[phm->obj_index] = 0;
799 phr->error = HPI_ERROR_MEMORY_ALLOC;
800 return;
801 }
802 }
803
804 if (command == HPI_BUFFER_CMD_EXTERNAL
805 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
806
807
808
809 struct hpi_hostbuffer_status *status;
810
811 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
812 buffer_size - 1)) {
813 HPI_DEBUG_LOG(ERROR,
814 "Buffer size must be 2^N not %d\n",
815 phm->u.d.u.buffer.buffer_size);
816 phr->error = HPI_ERROR_INVALID_DATASIZE;
817 return;
818 }
819 phw->outstream_host_buffer_size[phm->obj_index] =
820 phm->u.d.u.buffer.buffer_size;
821 status = &interface->outstream_host_buffer_status[phm->
822 obj_index];
823 status->samples_processed = 0;
824 status->stream_state = HPI_STATE_STOPPED;
825 status->dsp_index = 0;
826 status->host_index = status->dsp_index;
827 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
828 status->auxiliary_data_available = 0;
829
830 hw_message(pao, phm, phr);
831
832 if (phr->error
833 && hpios_locked_mem_valid(&phw->
834 outstream_host_buffers[phm->obj_index])) {
835 hpios_locked_mem_free(&phw->outstream_host_buffers
836 [phm->obj_index]);
837 phw->outstream_host_buffer_size[phm->obj_index] = 0;
838 }
839 }
840}
841
842static void outstream_host_buffer_get_info(struct hpi_adapter_obj *pao,
843 struct hpi_message *phm, struct hpi_response *phr)
844{
845 struct hpi_hw_obj *phw = pao->priv;
846 struct bus_master_interface *interface = phw->p_interface_buffer;
847 struct hpi_hostbuffer_status *status;
848 u8 *p_bbm_data;
849
850 if (hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
851 obj_index])) {
852 if (hpios_locked_mem_get_virt_addr(&phw->
853 outstream_host_buffers[phm->obj_index],
854 (void *)&p_bbm_data)) {
855 phr->error = HPI_ERROR_INVALID_OPERATION;
856 return;
857 }
858 status = &interface->outstream_host_buffer_status[phm->
859 obj_index];
860 hpi_init_response(phr, HPI_OBJ_OSTREAM,
861 HPI_OSTREAM_HOSTBUFFER_GET_INFO, 0);
862 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
863 phr->u.d.u.hostbuffer_info.p_status = status;
864 } else {
865 hpi_init_response(phr, HPI_OBJ_OSTREAM,
866 HPI_OSTREAM_HOSTBUFFER_GET_INFO,
867 HPI_ERROR_INVALID_OPERATION);
868 }
869}
870
871static void outstream_host_buffer_free(struct hpi_adapter_obj *pao,
872 struct hpi_message *phm, struct hpi_response *phr)
873{
874 struct hpi_hw_obj *phw = pao->priv;
875 u32 command = phm->u.d.u.buffer.command;
876
877 if (phw->outstream_host_buffer_size[phm->obj_index]) {
878 if (command == HPI_BUFFER_CMD_EXTERNAL
879 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
880 phw->outstream_host_buffer_size[phm->obj_index] = 0;
881 hw_message(pao, phm, phr);
882
883 }
884 if (command == HPI_BUFFER_CMD_EXTERNAL
885 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
886 hpios_locked_mem_free(&phw->outstream_host_buffers
887 [phm->obj_index]);
888 }
889
890
891 else
892 hpi_init_response(phr, HPI_OBJ_OSTREAM,
893 HPI_OSTREAM_HOSTBUFFER_FREE, 0);
894
895}
896
897static u32 outstream_get_space_available(struct hpi_hostbuffer_status *status)
898{
899 return status->size_in_bytes - (status->host_index -
900 status->dsp_index);
901}
902
903static void outstream_write(struct hpi_adapter_obj *pao,
904 struct hpi_message *phm, struct hpi_response *phr)
905{
906 struct hpi_hw_obj *phw = pao->priv;
907 struct bus_master_interface *interface = phw->p_interface_buffer;
908 struct hpi_hostbuffer_status *status;
909 u32 space_available;
910
911 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
912
913 hw_message(pao, phm, phr);
914 return;
915 }
916
917 hpi_init_response(phr, phm->object, phm->function, 0);
918 status = &interface->outstream_host_buffer_status[phm->obj_index];
919
920 space_available = outstream_get_space_available(status);
921 if (space_available < phm->u.d.u.data.data_size) {
922 phr->error = HPI_ERROR_INVALID_DATASIZE;
923 return;
924 }
925
926
927
928 if (phm->u.d.u.data.pb_data
929 && hpios_locked_mem_valid(&phw->outstream_host_buffers[phm->
930 obj_index])) {
931 u8 *p_bbm_data;
932 u32 l_first_write;
933 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
934
935 if (hpios_locked_mem_get_virt_addr(&phw->
936 outstream_host_buffers[phm->obj_index],
937 (void *)&p_bbm_data)) {
938 phr->error = HPI_ERROR_INVALID_OPERATION;
939 return;
940 }
941
942
943
944 l_first_write =
945 min(phm->u.d.u.data.data_size,
946 status->size_in_bytes -
947 (status->host_index & (status->size_in_bytes - 1)));
948
949 memcpy(p_bbm_data +
950 (status->host_index & (status->size_in_bytes - 1)),
951 p_app_data, l_first_write);
952
953 memcpy(p_bbm_data, p_app_data + l_first_write,
954 phm->u.d.u.data.data_size - l_first_write);
955 }
956
957
958
959
960
961
962
963 if (phw->flag_outstream_just_reset[phm->obj_index]) {
964
965 u16 function = phm->function;
966 phw->flag_outstream_just_reset[phm->obj_index] = 0;
967 phm->function = HPI_OSTREAM_SET_FORMAT;
968 hw_message(pao, phm, phr);
969 phm->function = function;
970 if (phr->error)
971 return;
972 }
973
974 status->host_index += phm->u.d.u.data.data_size;
975}
976
977static void outstream_get_info(struct hpi_adapter_obj *pao,
978 struct hpi_message *phm, struct hpi_response *phr)
979{
980 struct hpi_hw_obj *phw = pao->priv;
981 struct bus_master_interface *interface = phw->p_interface_buffer;
982 struct hpi_hostbuffer_status *status;
983
984 if (!phw->outstream_host_buffer_size[phm->obj_index]) {
985 hw_message(pao, phm, phr);
986 return;
987 }
988
989 hpi_init_response(phr, phm->object, phm->function, 0);
990
991 status = &interface->outstream_host_buffer_status[phm->obj_index];
992
993 phr->u.d.u.stream_info.state = (u16)status->stream_state;
994 phr->u.d.u.stream_info.samples_transferred =
995 status->samples_processed;
996 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
997 phr->u.d.u.stream_info.data_available =
998 status->size_in_bytes - outstream_get_space_available(status);
999 phr->u.d.u.stream_info.auxiliary_data_available =
1000 status->auxiliary_data_available;
1001}
1002
1003static void outstream_start(struct hpi_adapter_obj *pao,
1004 struct hpi_message *phm, struct hpi_response *phr)
1005{
1006 hw_message(pao, phm, phr);
1007}
1008
1009static void outstream_reset(struct hpi_adapter_obj *pao,
1010 struct hpi_message *phm, struct hpi_response *phr)
1011{
1012 struct hpi_hw_obj *phw = pao->priv;
1013 phw->flag_outstream_just_reset[phm->obj_index] = 1;
1014 hw_message(pao, phm, phr);
1015}
1016
1017static void outstream_open(struct hpi_adapter_obj *pao,
1018 struct hpi_message *phm, struct hpi_response *phr)
1019{
1020 outstream_reset(pao, phm, phr);
1021}
1022
1023
1024
1025
1026static void instream_host_buffer_allocate(struct hpi_adapter_obj *pao,
1027 struct hpi_message *phm, struct hpi_response *phr)
1028{
1029 u16 err = 0;
1030 u32 command = phm->u.d.u.buffer.command;
1031 struct hpi_hw_obj *phw = pao->priv;
1032 struct bus_master_interface *interface = phw->p_interface_buffer;
1033
1034 hpi_init_response(phr, phm->object, phm->function, 0);
1035
1036 if (command == HPI_BUFFER_CMD_EXTERNAL
1037 || command == HPI_BUFFER_CMD_INTERNAL_ALLOC) {
1038
1039 phm->u.d.u.buffer.buffer_size =
1040 roundup_pow_of_two(phm->u.d.u.buffer.buffer_size);
1041 phr->u.d.u.stream_info.data_available =
1042 phw->instream_host_buffer_size[phm->obj_index];
1043 phr->u.d.u.stream_info.buffer_size =
1044 phm->u.d.u.buffer.buffer_size;
1045
1046 if (phw->instream_host_buffer_size[phm->obj_index] ==
1047 phm->u.d.u.buffer.buffer_size) {
1048
1049 return;
1050 }
1051
1052 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1053 obj_index]))
1054 hpios_locked_mem_free(&phw->instream_host_buffers
1055 [phm->obj_index]);
1056
1057 err = hpios_locked_mem_alloc(&phw->instream_host_buffers[phm->
1058 obj_index], phm->u.d.u.buffer.buffer_size,
1059 pao->pci.pci_dev);
1060
1061 if (err) {
1062 phr->error = HPI_ERROR_INVALID_DATASIZE;
1063 phw->instream_host_buffer_size[phm->obj_index] = 0;
1064 return;
1065 }
1066
1067 err = hpios_locked_mem_get_phys_addr
1068 (&phw->instream_host_buffers[phm->obj_index],
1069 &phm->u.d.u.buffer.pci_address);
1070
1071
1072 phr->u.d.u.stream_info.auxiliary_data_available =
1073 phm->u.d.u.buffer.pci_address;
1074 if (err) {
1075 hpios_locked_mem_free(&phw->instream_host_buffers
1076 [phm->obj_index]);
1077 phw->instream_host_buffer_size[phm->obj_index] = 0;
1078 phr->error = HPI_ERROR_MEMORY_ALLOC;
1079 return;
1080 }
1081 }
1082
1083 if (command == HPI_BUFFER_CMD_EXTERNAL
1084 || command == HPI_BUFFER_CMD_INTERNAL_GRANTADAPTER) {
1085 struct hpi_hostbuffer_status *status;
1086
1087 if (phm->u.d.u.buffer.buffer_size & (phm->u.d.u.buffer.
1088 buffer_size - 1)) {
1089 HPI_DEBUG_LOG(ERROR,
1090 "Buffer size must be 2^N not %d\n",
1091 phm->u.d.u.buffer.buffer_size);
1092 phr->error = HPI_ERROR_INVALID_DATASIZE;
1093 return;
1094 }
1095
1096 phw->instream_host_buffer_size[phm->obj_index] =
1097 phm->u.d.u.buffer.buffer_size;
1098 status = &interface->instream_host_buffer_status[phm->
1099 obj_index];
1100 status->samples_processed = 0;
1101 status->stream_state = HPI_STATE_STOPPED;
1102 status->dsp_index = 0;
1103 status->host_index = status->dsp_index;
1104 status->size_in_bytes = phm->u.d.u.buffer.buffer_size;
1105 status->auxiliary_data_available = 0;
1106
1107 hw_message(pao, phm, phr);
1108
1109 if (phr->error
1110 && hpios_locked_mem_valid(&phw->
1111 instream_host_buffers[phm->obj_index])) {
1112 hpios_locked_mem_free(&phw->instream_host_buffers
1113 [phm->obj_index]);
1114 phw->instream_host_buffer_size[phm->obj_index] = 0;
1115 }
1116 }
1117}
1118
1119static void instream_host_buffer_get_info(struct hpi_adapter_obj *pao,
1120 struct hpi_message *phm, struct hpi_response *phr)
1121{
1122 struct hpi_hw_obj *phw = pao->priv;
1123 struct bus_master_interface *interface = phw->p_interface_buffer;
1124 struct hpi_hostbuffer_status *status;
1125 u8 *p_bbm_data;
1126
1127 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1128 obj_index])) {
1129 if (hpios_locked_mem_get_virt_addr(&phw->
1130 instream_host_buffers[phm->obj_index],
1131 (void *)&p_bbm_data)) {
1132 phr->error = HPI_ERROR_INVALID_OPERATION;
1133 return;
1134 }
1135 status = &interface->instream_host_buffer_status[phm->
1136 obj_index];
1137 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1138 HPI_ISTREAM_HOSTBUFFER_GET_INFO, 0);
1139 phr->u.d.u.hostbuffer_info.p_buffer = p_bbm_data;
1140 phr->u.d.u.hostbuffer_info.p_status = status;
1141 } else {
1142 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1143 HPI_ISTREAM_HOSTBUFFER_GET_INFO,
1144 HPI_ERROR_INVALID_OPERATION);
1145 }
1146}
1147
1148static void instream_host_buffer_free(struct hpi_adapter_obj *pao,
1149 struct hpi_message *phm, struct hpi_response *phr)
1150{
1151 struct hpi_hw_obj *phw = pao->priv;
1152 u32 command = phm->u.d.u.buffer.command;
1153
1154 if (phw->instream_host_buffer_size[phm->obj_index]) {
1155 if (command == HPI_BUFFER_CMD_EXTERNAL
1156 || command == HPI_BUFFER_CMD_INTERNAL_REVOKEADAPTER) {
1157 phw->instream_host_buffer_size[phm->obj_index] = 0;
1158 hw_message(pao, phm, phr);
1159 }
1160
1161 if (command == HPI_BUFFER_CMD_EXTERNAL
1162 || command == HPI_BUFFER_CMD_INTERNAL_FREE)
1163 hpios_locked_mem_free(&phw->instream_host_buffers
1164 [phm->obj_index]);
1165
1166 } else {
1167
1168
1169 hpi_init_response(phr, HPI_OBJ_ISTREAM,
1170 HPI_ISTREAM_HOSTBUFFER_FREE, 0);
1171
1172 }
1173
1174}
1175
1176static void instream_start(struct hpi_adapter_obj *pao,
1177 struct hpi_message *phm, struct hpi_response *phr)
1178{
1179 hw_message(pao, phm, phr);
1180}
1181
1182static u32 instream_get_bytes_available(struct hpi_hostbuffer_status *status)
1183{
1184 return status->dsp_index - status->host_index;
1185}
1186
1187static void instream_read(struct hpi_adapter_obj *pao,
1188 struct hpi_message *phm, struct hpi_response *phr)
1189{
1190 struct hpi_hw_obj *phw = pao->priv;
1191 struct bus_master_interface *interface = phw->p_interface_buffer;
1192 struct hpi_hostbuffer_status *status;
1193 u32 data_available;
1194 u8 *p_bbm_data;
1195 u32 l_first_read;
1196 u8 *p_app_data = (u8 *)phm->u.d.u.data.pb_data;
1197
1198 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1199 hw_message(pao, phm, phr);
1200 return;
1201 }
1202 hpi_init_response(phr, phm->object, phm->function, 0);
1203
1204 status = &interface->instream_host_buffer_status[phm->obj_index];
1205 data_available = instream_get_bytes_available(status);
1206 if (data_available < phm->u.d.u.data.data_size) {
1207 phr->error = HPI_ERROR_INVALID_DATASIZE;
1208 return;
1209 }
1210
1211 if (hpios_locked_mem_valid(&phw->instream_host_buffers[phm->
1212 obj_index])) {
1213 if (hpios_locked_mem_get_virt_addr(&phw->
1214 instream_host_buffers[phm->obj_index],
1215 (void *)&p_bbm_data)) {
1216 phr->error = HPI_ERROR_INVALID_OPERATION;
1217 return;
1218 }
1219
1220
1221
1222 l_first_read =
1223 min(phm->u.d.u.data.data_size,
1224 status->size_in_bytes -
1225 (status->host_index & (status->size_in_bytes - 1)));
1226
1227 memcpy(p_app_data,
1228 p_bbm_data +
1229 (status->host_index & (status->size_in_bytes - 1)),
1230 l_first_read);
1231
1232 memcpy(p_app_data + l_first_read, p_bbm_data,
1233 phm->u.d.u.data.data_size - l_first_read);
1234 }
1235 status->host_index += phm->u.d.u.data.data_size;
1236}
1237
1238static void instream_get_info(struct hpi_adapter_obj *pao,
1239 struct hpi_message *phm, struct hpi_response *phr)
1240{
1241 struct hpi_hw_obj *phw = pao->priv;
1242 struct bus_master_interface *interface = phw->p_interface_buffer;
1243 struct hpi_hostbuffer_status *status;
1244 if (!phw->instream_host_buffer_size[phm->obj_index]) {
1245 hw_message(pao, phm, phr);
1246 return;
1247 }
1248
1249 status = &interface->instream_host_buffer_status[phm->obj_index];
1250
1251 hpi_init_response(phr, phm->object, phm->function, 0);
1252
1253 phr->u.d.u.stream_info.state = (u16)status->stream_state;
1254 phr->u.d.u.stream_info.samples_transferred =
1255 status->samples_processed;
1256 phr->u.d.u.stream_info.buffer_size = status->size_in_bytes;
1257 phr->u.d.u.stream_info.data_available =
1258 instream_get_bytes_available(status);
1259 phr->u.d.u.stream_info.auxiliary_data_available =
1260 status->auxiliary_data_available;
1261}
1262
1263
1264
1265#define HPI6205_MAX_FILES_TO_LOAD 2
1266
1267static u16 adapter_boot_load_dsp(struct hpi_adapter_obj *pao,
1268 u32 *pos_error_code)
1269{
1270 struct hpi_hw_obj *phw = pao->priv;
1271 struct dsp_code dsp_code;
1272 u16 boot_code_id[HPI6205_MAX_FILES_TO_LOAD];
1273 u32 temp;
1274 int dsp = 0, i = 0;
1275 u16 err = 0;
1276
1277 boot_code_id[0] = HPI_ADAPTER_ASI(0x6205);
1278
1279 boot_code_id[1] = pao->pci.pci_dev->subsystem_device;
1280 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(boot_code_id[1]);
1281
1282
1283 switch (boot_code_id[1]) {
1284 case HPI_ADAPTER_FAMILY_ASI(0x5000):
1285 boot_code_id[0] = boot_code_id[1];
1286 boot_code_id[1] = 0;
1287 break;
1288 case HPI_ADAPTER_FAMILY_ASI(0x5300):
1289 case HPI_ADAPTER_FAMILY_ASI(0x5400):
1290 case HPI_ADAPTER_FAMILY_ASI(0x6300):
1291 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6400);
1292 break;
1293 case HPI_ADAPTER_FAMILY_ASI(0x5500):
1294 case HPI_ADAPTER_FAMILY_ASI(0x5600):
1295 case HPI_ADAPTER_FAMILY_ASI(0x6500):
1296 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x6600);
1297 break;
1298 case HPI_ADAPTER_FAMILY_ASI(0x8800):
1299 boot_code_id[1] = HPI_ADAPTER_FAMILY_ASI(0x8900);
1300 break;
1301 default:
1302 break;
1303 }
1304
1305
1306 temp = C6205_HDCR_WARMRESET;
1307 iowrite32(temp, phw->prHDCR);
1308 hpios_delay_micro_seconds(1000);
1309
1310
1311 temp = ioread32(phw->prHSR);
1312 if ((temp & (C6205_HSR_CFGERR | C6205_HSR_EEREAD)) !=
1313 C6205_HSR_EEREAD)
1314 return HPI6205_ERROR_6205_EEPROM;
1315 temp |= 0x04;
1316
1317 iowrite32(temp, phw->prHSR);
1318
1319
1320 temp = ioread32(phw->prHDCR);
1321 if (!(temp & C6205_HDCR_PCIBOOT))
1322 return HPI6205_ERROR_6205_REG;
1323
1324
1325
1326 temp = 3;
1327 iowrite32(temp, phw->prDSPP);
1328 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1329 return HPI6205_ERROR_6205_DSPPAGE;
1330 temp = 2;
1331 iowrite32(temp, phw->prDSPP);
1332 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1333 return HPI6205_ERROR_6205_DSPPAGE;
1334 temp = 1;
1335 iowrite32(temp, phw->prDSPP);
1336 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1337 return HPI6205_ERROR_6205_DSPPAGE;
1338
1339 temp = 0;
1340 iowrite32(temp, phw->prDSPP);
1341 if ((temp | C6205_DSPP_MAP1) != ioread32(phw->prDSPP))
1342 return HPI6205_ERROR_6205_DSPPAGE;
1343 phw->dsp_page = 0;
1344
1345
1346
1347
1348
1349 if (boot_code_id[1] != 0) {
1350
1351
1352 boot_loader_write_mem32(pao, 0, 0x018C0024, 0x00002202);
1353 hpios_delay_micro_seconds(100);
1354
1355 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 0);
1356
1357 if (0 != (boot_loader_read_mem32(pao, 0,
1358 (C6205_BAR0_TIMER1_CTL)) & ~8))
1359 return HPI6205_ERROR_6205_REG;
1360 hpios_delay_micro_seconds(100);
1361
1362
1363 boot_loader_write_mem32(pao, 0, C6205_BAR0_TIMER1_CTL, 4);
1364 if (4 != (boot_loader_read_mem32(pao, 0,
1365 (C6205_BAR0_TIMER1_CTL)) & ~8))
1366 return HPI6205_ERROR_6205_REG;
1367 hpios_delay_micro_seconds(100);
1368 }
1369
1370 for (dsp = 0; dsp < HPI6205_MAX_FILES_TO_LOAD; dsp++) {
1371
1372 if (boot_code_id[dsp] == 0)
1373 continue;
1374
1375 err = boot_loader_config_emif(pao, dsp);
1376 if (err)
1377 return err;
1378
1379 err = boot_loader_test_internal_memory(pao, dsp);
1380 if (err)
1381 return err;
1382
1383 err = boot_loader_test_external_memory(pao, dsp);
1384 if (err)
1385 return err;
1386
1387 err = boot_loader_test_pld(pao, dsp);
1388 if (err)
1389 return err;
1390
1391
1392 err = hpi_dsp_code_open(boot_code_id[dsp], pao->pci.pci_dev,
1393 &dsp_code, pos_error_code);
1394 if (err)
1395 return err;
1396
1397 while (1) {
1398 u32 length;
1399 u32 address;
1400 u32 type;
1401 u32 *pcode;
1402
1403 err = hpi_dsp_code_read_word(&dsp_code, &length);
1404 if (err)
1405 break;
1406 if (length == 0xFFFFFFFF)
1407 break;
1408
1409 err = hpi_dsp_code_read_word(&dsp_code, &address);
1410 if (err)
1411 break;
1412 err = hpi_dsp_code_read_word(&dsp_code, &type);
1413 if (err)
1414 break;
1415 err = hpi_dsp_code_read_block(length, &dsp_code,
1416 &pcode);
1417 if (err)
1418 break;
1419 for (i = 0; i < (int)length; i++) {
1420 boot_loader_write_mem32(pao, dsp, address,
1421 *pcode);
1422
1423
1424 if (i % 4 == 0)
1425 boot_loader_read_mem32(pao, dsp,
1426 address);
1427 pcode++;
1428 address += 4;
1429 }
1430
1431 }
1432 if (err) {
1433 hpi_dsp_code_close(&dsp_code);
1434 return err;
1435 }
1436
1437
1438 hpi_dsp_code_rewind(&dsp_code);
1439 while (1) {
1440 u32 length = 0;
1441 u32 address = 0;
1442 u32 type = 0;
1443 u32 *pcode = NULL;
1444 u32 data = 0;
1445
1446 hpi_dsp_code_read_word(&dsp_code, &length);
1447 if (length == 0xFFFFFFFF)
1448 break;
1449
1450 hpi_dsp_code_read_word(&dsp_code, &address);
1451 hpi_dsp_code_read_word(&dsp_code, &type);
1452 hpi_dsp_code_read_block(length, &dsp_code, &pcode);
1453
1454 for (i = 0; i < (int)length; i++) {
1455 data = boot_loader_read_mem32(pao, dsp,
1456 address);
1457 if (data != *pcode) {
1458 err = 0;
1459 break;
1460 }
1461 pcode++;
1462 address += 4;
1463 }
1464 if (err)
1465 break;
1466 }
1467 hpi_dsp_code_close(&dsp_code);
1468 if (err)
1469 return err;
1470 }
1471
1472
1473
1474
1475 if (phw->p_interface_buffer) {
1476
1477 u32 physicalPC_iaddress;
1478 struct bus_master_interface *interface =
1479 phw->p_interface_buffer;
1480 u32 host_mailbox_address_on_dsp;
1481 u32 physicalPC_iaddress_verify = 0;
1482 int time_out = 10;
1483
1484
1485 interface->dsp_ack = H620_HIF_UNKNOWN;
1486 wmb();
1487
1488 err = hpios_locked_mem_get_phys_addr(&phw->h_locked_mem,
1489 &physicalPC_iaddress);
1490
1491
1492 host_mailbox_address_on_dsp = 0x80000000;
1493 while ((physicalPC_iaddress != physicalPC_iaddress_verify)
1494 && time_out--) {
1495 boot_loader_write_mem32(pao, 0,
1496 host_mailbox_address_on_dsp,
1497 physicalPC_iaddress);
1498 physicalPC_iaddress_verify =
1499 boot_loader_read_mem32(pao, 0,
1500 host_mailbox_address_on_dsp);
1501 }
1502 }
1503 HPI_DEBUG_LOG(DEBUG, "starting DS_ps running\n");
1504
1505 temp = ioread32(phw->prHSR);
1506 temp &= ~(u32)C6205_HSR_INTAM;
1507 iowrite32(temp, phw->prHSR);
1508
1509
1510 temp = ioread32(phw->prHDCR);
1511 temp |= (u32)C6205_HDCR_DSPINT;
1512 iowrite32(temp, phw->prHDCR);
1513
1514
1515 hpios_delay_micro_seconds(10000);
1516 return err;
1517
1518}
1519
1520
1521
1522
1523static u32 boot_loader_read_mem32(struct hpi_adapter_obj *pao, int dsp_index,
1524 u32 address)
1525{
1526 struct hpi_hw_obj *phw = pao->priv;
1527 u32 data = 0;
1528 __iomem u32 *p_data;
1529
1530 if (dsp_index == 0) {
1531
1532 if ((address >= 0x01800000) & (address < 0x02000000)) {
1533
1534 p_data = pao->pci.ap_mem_base[1] +
1535 (address & 0x007fffff) /
1536 sizeof(*pao->pci.ap_mem_base[1]);
1537
1538
1539 } else {
1540 u32 dw4M_page = address >> 22L;
1541 if (dw4M_page != phw->dsp_page) {
1542 phw->dsp_page = dw4M_page;
1543
1544 iowrite32(phw->dsp_page, phw->prDSPP);
1545
1546 }
1547 address &= 0x3fffff;
1548
1549 p_data = pao->pci.ap_mem_base[0] +
1550 address / sizeof(u32);
1551 }
1552 data = ioread32(p_data);
1553 } else if (dsp_index == 1) {
1554
1555 u32 lsb;
1556 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1557 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1558 lsb = boot_loader_read_mem32(pao, 0, HPIDL_ADDR);
1559 data = boot_loader_read_mem32(pao, 0, HPIDH_ADDR);
1560 data = (data << 16) | (lsb & 0xFFFF);
1561 }
1562 return data;
1563}
1564
1565static void boot_loader_write_mem32(struct hpi_adapter_obj *pao,
1566 int dsp_index, u32 address, u32 data)
1567{
1568 struct hpi_hw_obj *phw = pao->priv;
1569 __iomem u32 *p_data;
1570
1571
1572 if (dsp_index == 0) {
1573
1574 if ((address >= 0x01800000) & (address < 0x02000000)) {
1575
1576
1577 p_data = pao->pci.ap_mem_base[1] +
1578 (address & 0x007fffff) /
1579 sizeof(*pao->pci.ap_mem_base[1]);
1580 } else {
1581
1582
1583 u32 dw4M_page = address >> 22L;
1584 if (dw4M_page != phw->dsp_page) {
1585 phw->dsp_page = dw4M_page;
1586
1587 iowrite32(phw->dsp_page, phw->prDSPP);
1588
1589 }
1590 address &= 0x3fffff;
1591 p_data = pao->pci.ap_mem_base[0] +
1592 address / sizeof(u32);
1593 }
1594 iowrite32(data, p_data);
1595 } else if (dsp_index == 1) {
1596
1597 boot_loader_write_mem32(pao, 0, HPIAL_ADDR, address);
1598 boot_loader_write_mem32(pao, 0, HPIAH_ADDR, address >> 16);
1599
1600
1601 boot_loader_read_mem32(pao, 0, 0);
1602
1603 boot_loader_write_mem32(pao, 0, HPIDL_ADDR, data);
1604 boot_loader_write_mem32(pao, 0, HPIDH_ADDR, data >> 16);
1605
1606
1607 boot_loader_read_mem32(pao, 0, 0);
1608 }
1609}
1610
1611static u16 boot_loader_config_emif(struct hpi_adapter_obj *pao, int dsp_index)
1612{
1613 if (dsp_index == 0) {
1614 u32 setting;
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626 boot_loader_write_mem32(pao, dsp_index, 0x01800000, 0x3779);
1627#define WS_OFS 28
1628#define WST_OFS 22
1629#define WH_OFS 20
1630#define RS_OFS 16
1631#define RST_OFS 8
1632#define MTYPE_OFS 4
1633#define RH_OFS 0
1634
1635
1636 setting = 0x00000030;
1637 boot_loader_write_mem32(pao, dsp_index, 0x01800008, setting);
1638 if (setting != boot_loader_read_mem32(pao, dsp_index,
1639 0x01800008))
1640 return HPI6205_ERROR_DSP_EMIF1;
1641
1642
1643
1644
1645
1646 setting =
1647 (1L << WS_OFS) | (63L << WST_OFS) | (1L << WH_OFS) |
1648 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1649 (2L << MTYPE_OFS);
1650 boot_loader_write_mem32(pao, dsp_index, 0x01800004, setting);
1651 if (setting != boot_loader_read_mem32(pao, dsp_index,
1652 0x01800004))
1653 return HPI6205_ERROR_DSP_EMIF2;
1654
1655
1656
1657
1658 setting =
1659 (1L << WS_OFS) | (28L << WST_OFS) | (1L << WH_OFS) |
1660 (1L << RS_OFS) | (63L << RST_OFS) | (1L << RH_OFS) |
1661 (2L << MTYPE_OFS);
1662 boot_loader_write_mem32(pao, dsp_index, 0x01800010, setting);
1663 if (setting != boot_loader_read_mem32(pao, dsp_index,
1664 0x01800010))
1665 return HPI6205_ERROR_DSP_EMIF3;
1666
1667
1668
1669 setting =
1670 (1L << WS_OFS) | (10L << WST_OFS) | (1L << WH_OFS) |
1671 (1L << RS_OFS) | (10L << RST_OFS) | (1L << RH_OFS) |
1672 (2L << MTYPE_OFS);
1673 boot_loader_write_mem32(pao, dsp_index, 0x01800014, setting);
1674 if (setting != boot_loader_read_mem32(pao, dsp_index,
1675 0x01800014))
1676 return HPI6205_ERROR_DSP_EMIF4;
1677
1678
1679
1680 boot_loader_write_mem32(pao, dsp_index, 0x01800018,
1681 0x07117000);
1682
1683
1684
1685 boot_loader_write_mem32(pao, dsp_index, 0x0180001C,
1686 0x00000410);
1687
1688 } else if (dsp_index == 1) {
1689
1690 u32 write_data = 0, read_data = 0, i = 0;
1691
1692
1693 write_data = 1;
1694 boot_loader_write_mem32(pao, 0, HPICL_ADDR, write_data);
1695 boot_loader_write_mem32(pao, 0, HPICH_ADDR, write_data);
1696
1697 read_data =
1698 0xFFF7 & boot_loader_read_mem32(pao, 0, HPICL_ADDR);
1699 if (write_data != read_data) {
1700 HPI_DEBUG_LOG(ERROR, "HPICL %x %x\n", write_data,
1701 read_data);
1702 return HPI6205_ERROR_C6713_HPIC;
1703 }
1704
1705 write_data = 1;
1706 for (i = 0; i < 32; i++) {
1707 boot_loader_write_mem32(pao, 0, HPIAL_ADDR,
1708 write_data);
1709 boot_loader_write_mem32(pao, 0, HPIAH_ADDR,
1710 (write_data >> 16));
1711 read_data =
1712 0xFFFF & boot_loader_read_mem32(pao, 0,
1713 HPIAL_ADDR);
1714 read_data =
1715 read_data | ((0xFFFF &
1716 boot_loader_read_mem32(pao, 0,
1717 HPIAH_ADDR))
1718 << 16);
1719 if (read_data != write_data) {
1720 HPI_DEBUG_LOG(ERROR, "HPIA %x %x\n",
1721 write_data, read_data);
1722 return HPI6205_ERROR_C6713_HPIA;
1723 }
1724 write_data = write_data << 1;
1725 }
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0000);
1736 hpios_delay_micro_seconds(1000);
1737
1738 boot_loader_write_mem32(pao, dsp_index, 0x01B7C120, 0x8002);
1739
1740 boot_loader_write_mem32(pao, dsp_index, 0x01B7C11C, 0x8001);
1741
1742 boot_loader_write_mem32(pao, dsp_index, 0x01B7C118, 0x8000);
1743 hpios_delay_micro_seconds(1000);
1744
1745
1746
1747 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A0A);
1748
1749 boot_loader_write_mem32(pao, dsp_index, 0x01B7C100, 0x0001);
1750 hpios_delay_micro_seconds(1000);
1751
1752 boot_loader_write_mem32(pao, 0, (0x018C0024L), 0x00002A02);
1753
1754
1755
1756 boot_loader_write_mem32(pao, 0, 0x01800004,
1757 (1L << WS_OFS) | (8L << WST_OFS) | (1L << WH_OFS) |
1758 (1L << RS_OFS) | (12L << RST_OFS) | (1L << RH_OFS) |
1759 (2L << MTYPE_OFS));
1760
1761 hpios_delay_micro_seconds(1000);
1762
1763
1764
1765 if ((boot_loader_read_mem32(pao, dsp_index, 0x01B7C100) & 0xF)
1766 != 0x0001) {
1767 return HPI6205_ERROR_C6713_PLL;
1768 }
1769
1770
1771 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_GCTL,
1772 0x000034A8);
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_CE0,
1786 0x00000030);
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMEXT,
1808 0x001BDF29);
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827 boot_loader_write_mem32(pao, dsp_index, C6713_EMIF_SDRAMCTL,
1828 0x47116000);
1829
1830
1831
1832
1833 boot_loader_write_mem32(pao, dsp_index,
1834 C6713_EMIF_SDRAMTIMING, 0x00000410);
1835
1836 hpios_delay_micro_seconds(1000);
1837 } else if (dsp_index == 2) {
1838
1839 }
1840
1841 return 0;
1842}
1843
1844static u16 boot_loader_test_memory(struct hpi_adapter_obj *pao, int dsp_index,
1845 u32 start_address, u32 length)
1846{
1847 u32 i = 0, j = 0;
1848 u32 test_addr = 0;
1849 u32 test_data = 0, data = 0;
1850
1851 length = 1000;
1852
1853
1854
1855
1856 i = 0;
1857 {
1858 test_addr = start_address + i * 4;
1859 test_data = 0x00000001;
1860 for (j = 0; j < 32; j++) {
1861 boot_loader_write_mem32(pao, dsp_index, test_addr,
1862 test_data);
1863 data = boot_loader_read_mem32(pao, dsp_index,
1864 test_addr);
1865 if (data != test_data) {
1866 HPI_DEBUG_LOG(VERBOSE,
1867 "Memtest error details "
1868 "%08x %08x %08x %i\n", test_addr,
1869 test_data, data, dsp_index);
1870 return 1;
1871 }
1872 test_data = test_data << 1;
1873 }
1874 }
1875
1876
1877
1878
1879 for (i = 0; i < 100; i++) {
1880 test_addr = start_address + i * 4;
1881 test_data = 0xA5A55A5A;
1882 boot_loader_write_mem32(pao, dsp_index, test_addr, test_data);
1883 boot_loader_write_mem32(pao, dsp_index, test_addr + 4, 0);
1884 data = boot_loader_read_mem32(pao, dsp_index, test_addr);
1885 if (data != test_data) {
1886 HPI_DEBUG_LOG(VERBOSE,
1887 "Memtest error details "
1888 "%08x %08x %08x %i\n", test_addr, test_data,
1889 data, dsp_index);
1890 return 1;
1891 }
1892
1893 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1894 }
1895
1896
1897 for (i = 0; i < length; i++) {
1898 test_addr = start_address + i * 4;
1899 boot_loader_write_mem32(pao, dsp_index, test_addr, 0x0);
1900 }
1901 return 0;
1902}
1903
1904static u16 boot_loader_test_internal_memory(struct hpi_adapter_obj *pao,
1905 int dsp_index)
1906{
1907 int err = 0;
1908 if (dsp_index == 0) {
1909
1910
1911 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1912 0x10000);
1913 if (!err)
1914
1915 err = boot_loader_test_memory(pao, dsp_index,
1916 0x80000000, 0x10000);
1917 } else if (dsp_index == 1) {
1918
1919
1920 err = boot_loader_test_memory(pao, dsp_index, 0x00000000,
1921 0x30000);
1922 if (!err)
1923
1924 err = boot_loader_test_memory(pao, dsp_index,
1925 0x00030000, 0x10000);
1926 }
1927
1928 if (err)
1929 return HPI6205_ERROR_DSP_INTMEM;
1930 else
1931 return 0;
1932}
1933
1934static u16 boot_loader_test_external_memory(struct hpi_adapter_obj *pao,
1935 int dsp_index)
1936{
1937 u32 dRAM_start_address = 0;
1938 u32 dRAM_size = 0;
1939
1940 if (dsp_index == 0) {
1941
1942 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1943
1944 dRAM_start_address = 0x00400000;
1945 dRAM_size = 0x200000;
1946
1947 } else
1948 return 0;
1949 } else if (dsp_index == 1) {
1950
1951 dRAM_start_address = 0x80000000;
1952 dRAM_size = 0x200000;
1953
1954 }
1955
1956 if (boot_loader_test_memory(pao, dsp_index, dRAM_start_address,
1957 dRAM_size))
1958 return HPI6205_ERROR_DSP_EXTMEM;
1959 return 0;
1960}
1961
1962static u16 boot_loader_test_pld(struct hpi_adapter_obj *pao, int dsp_index)
1963{
1964 u32 data = 0;
1965 if (dsp_index == 0) {
1966
1967 if (pao->pci.pci_dev->subsystem_device == 0x5000) {
1968
1969 data = boot_loader_read_mem32(pao, dsp_index,
1970 0x03000008);
1971 if ((data & 0xF) != 0x5)
1972 return HPI6205_ERROR_DSP_PLD;
1973 data = boot_loader_read_mem32(pao, dsp_index,
1974 0x0300000C);
1975 if ((data & 0xF) != 0xA)
1976 return HPI6205_ERROR_DSP_PLD;
1977 }
1978 } else if (dsp_index == 1) {
1979
1980 if (pao->pci.pci_dev->subsystem_device == 0x8700) {
1981
1982 data = boot_loader_read_mem32(pao, dsp_index,
1983 0x90000010);
1984 if ((data & 0xFF) != 0xAA)
1985 return HPI6205_ERROR_DSP_PLD;
1986
1987 boot_loader_write_mem32(pao, dsp_index, 0x90000000,
1988 0x02);
1989 }
1990 }
1991 return 0;
1992}
1993
1994
1995
1996
1997static short hpi6205_transfer_data(struct hpi_adapter_obj *pao, u8 *p_data,
1998 u32 data_size, int operation)
1999{
2000 struct hpi_hw_obj *phw = pao->priv;
2001 u32 data_transferred = 0;
2002 u16 err = 0;
2003 u32 temp2;
2004 struct bus_master_interface *interface = phw->p_interface_buffer;
2005
2006 if (!p_data)
2007 return HPI_ERROR_INVALID_DATA_POINTER;
2008
2009 data_size &= ~3L;
2010
2011
2012 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT))
2013 return HPI_ERROR_DSP_HARDWARE;
2014
2015 while (data_transferred < data_size) {
2016 u32 this_copy = data_size - data_transferred;
2017
2018 if (this_copy > HPI6205_SIZEOF_DATA)
2019 this_copy = HPI6205_SIZEOF_DATA;
2020
2021 if (operation == H620_HIF_SEND_DATA)
2022 memcpy((void *)&interface->u.b_data[0],
2023 &p_data[data_transferred], this_copy);
2024
2025 interface->transfer_size_in_bytes = this_copy;
2026
2027
2028 interface->dsp_ack = H620_HIF_IDLE;
2029 send_dsp_command(phw, operation);
2030
2031 temp2 = wait_dsp_ack(phw, operation, HPI6205_TIMEOUT);
2032 HPI_DEBUG_LOG(DEBUG, "spun %d times for data xfer of %d\n",
2033 HPI6205_TIMEOUT - temp2, this_copy);
2034
2035 if (!temp2) {
2036
2037 HPI_DEBUG_LOG(ERROR,
2038 "Timed out waiting for " "state %d got %d\n",
2039 operation, interface->dsp_ack);
2040
2041 break;
2042 }
2043 if (operation == H620_HIF_GET_DATA)
2044 memcpy(&p_data[data_transferred],
2045 (void *)&interface->u.b_data[0], this_copy);
2046
2047 data_transferred += this_copy;
2048 }
2049 if (interface->dsp_ack != operation)
2050 HPI_DEBUG_LOG(DEBUG, "interface->dsp_ack=%d, expected %d\n",
2051 interface->dsp_ack, operation);
2052
2053
2054 send_dsp_command(phw, H620_HIF_IDLE);
2055
2056 return err;
2057}
2058
2059
2060
2061
2062static int wait_dsp_ack(struct hpi_hw_obj *phw, int state, int timeout_us)
2063{
2064 struct bus_master_interface *interface = phw->p_interface_buffer;
2065 int t = timeout_us / 4;
2066
2067 rmb();
2068 while ((interface->dsp_ack != state) && --t) {
2069 hpios_delay_micro_seconds(4);
2070 rmb();
2071 }
2072
2073
2074 return t * 4;
2075}
2076
2077
2078static void send_dsp_command(struct hpi_hw_obj *phw, int cmd)
2079{
2080 struct bus_master_interface *interface = phw->p_interface_buffer;
2081 u32 r;
2082
2083 interface->host_cmd = cmd;
2084 wmb();
2085
2086 r = ioread32(phw->prHDCR);
2087 r |= (u32)C6205_HDCR_DSPINT;
2088 iowrite32(r, phw->prHDCR);
2089 r &= ~(u32)C6205_HDCR_DSPINT;
2090 iowrite32(r, phw->prHDCR);
2091}
2092
2093static unsigned int message_count;
2094
2095static u16 message_response_sequence(struct hpi_adapter_obj *pao,
2096 struct hpi_message *phm, struct hpi_response *phr)
2097{
2098 u32 time_out, time_out2;
2099 struct hpi_hw_obj *phw = pao->priv;
2100 struct bus_master_interface *interface = phw->p_interface_buffer;
2101 u16 err = 0;
2102
2103 message_count++;
2104 if (phm->size > sizeof(interface->u.message_buffer)) {
2105 phr->error = HPI_ERROR_MESSAGE_BUFFER_TOO_SMALL;
2106 phr->specific_error = sizeof(interface->u.message_buffer);
2107 phr->size = sizeof(struct hpi_response_header);
2108 HPI_DEBUG_LOG(ERROR,
2109 "message len %d too big for buffer %zd \n", phm->size,
2110 sizeof(interface->u.message_buffer));
2111 return 0;
2112 }
2113
2114
2115
2116
2117 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2118 HPI_DEBUG_LOG(DEBUG, "timeout waiting for idle\n");
2119 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2120 }
2121
2122 memcpy(&interface->u.message_buffer, phm, phm->size);
2123
2124 send_dsp_command(phw, H620_HIF_GET_RESP);
2125
2126 time_out2 = wait_dsp_ack(phw, H620_HIF_GET_RESP, HPI6205_TIMEOUT);
2127
2128 if (!time_out2) {
2129 HPI_DEBUG_LOG(ERROR,
2130 "(%u) Timed out waiting for " "GET_RESP state [%x]\n",
2131 message_count, interface->dsp_ack);
2132 } else {
2133 HPI_DEBUG_LOG(VERBOSE,
2134 "(%u) transition to GET_RESP after %u\n",
2135 message_count, HPI6205_TIMEOUT - time_out2);
2136 }
2137
2138 time_out = HPI6205_TIMEOUT;
2139
2140
2141 if (time_out) {
2142 if (interface->u.response_buffer.response.size <= phr->size)
2143 memcpy(phr, &interface->u.response_buffer,
2144 interface->u.response_buffer.response.size);
2145 else {
2146 HPI_DEBUG_LOG(ERROR,
2147 "response len %d too big for buffer %d\n",
2148 interface->u.response_buffer.response.size,
2149 phr->size);
2150 memcpy(phr, &interface->u.response_buffer,
2151 sizeof(struct hpi_response_header));
2152 phr->error = HPI_ERROR_RESPONSE_BUFFER_TOO_SMALL;
2153 phr->specific_error =
2154 interface->u.response_buffer.response.size;
2155 phr->size = sizeof(struct hpi_response_header);
2156 }
2157 }
2158
2159 send_dsp_command(phw, H620_HIF_IDLE);
2160
2161 if (!time_out || !time_out2) {
2162 HPI_DEBUG_LOG(DEBUG, "something timed out!\n");
2163 return HPI6205_ERROR_MSG_RESP_TIMEOUT;
2164 }
2165
2166
2167 if (phm->function == HPI_ADAPTER_CLOSE) {
2168 if (!wait_dsp_ack(phw, H620_HIF_IDLE, HPI6205_TIMEOUT)) {
2169 HPI_DEBUG_LOG(DEBUG,
2170 "Timeout waiting for idle "
2171 "(on adapter_close)\n");
2172 return HPI6205_ERROR_MSG_RESP_IDLE_TIMEOUT;
2173 }
2174 }
2175 err = hpi_validate_response(phm, phr);
2176 return err;
2177}
2178
2179static void hw_message(struct hpi_adapter_obj *pao, struct hpi_message *phm,
2180 struct hpi_response *phr)
2181{
2182
2183 u16 err = 0;
2184
2185 hpios_dsplock_lock(pao);
2186
2187 err = message_response_sequence(pao, phm, phr);
2188
2189
2190 if (err) {
2191
2192 if (err >= HPI_ERROR_BACKEND_BASE) {
2193 phr->error = HPI_ERROR_DSP_COMMUNICATION;
2194 phr->specific_error = err;
2195 } else {
2196 phr->error = err;
2197 }
2198
2199 pao->dsp_crashed++;
2200
2201
2202 phr->size = sizeof(struct hpi_response_header);
2203 goto err;
2204 } else
2205 pao->dsp_crashed = 0;
2206
2207 if (phr->error != 0)
2208 goto err;
2209
2210 switch (phm->function) {
2211 case HPI_OSTREAM_WRITE:
2212 case HPI_ISTREAM_ANC_WRITE:
2213 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2214 phm->u.d.u.data.data_size, H620_HIF_SEND_DATA);
2215 break;
2216
2217 case HPI_ISTREAM_READ:
2218 case HPI_OSTREAM_ANC_READ:
2219 err = hpi6205_transfer_data(pao, phm->u.d.u.data.pb_data,
2220 phm->u.d.u.data.data_size, H620_HIF_GET_DATA);
2221 break;
2222
2223 }
2224 phr->error = err;
2225
2226err:
2227 hpios_dsplock_unlock(pao);
2228
2229 return;
2230}
2231